1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
4 *
5 * DTS for SolidRun CN9132 Clearfog.
6 *
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13
14 #include "cn9130.dtsi"
15 #include "cn9132-sr-cex7.dtsi"
16
17 / {
18 model = "SolidRun CN9132 Clearfog";
19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
21
22 aliases {
23 ethernet1 = &cp0_eth2;
24 ethernet2 = &cp0_eth0;
25 ethernet3 = &cp2_eth0;
26 ethernet4 = &cp1_eth0;
27 i2c7 = &carrier_mpcie_i2c;
28 i2c8 = &carrier_ptp_i2c;
29 mmc1 = &cp0_sdhci0;
30 };
31
32 gpio-keys {
33 compatible = "gpio-keys";
34 pinctrl-names = "default";
35 pinctrl-0 = <&cp1_wake0_pins>;
36
37 button-0 {
38 label = "SW2";
39 gpios = <&cp1_gpio2 8 GPIO_ACTIVE_LOW>;
40 linux,can-disable;
41 linux,code = <BTN_2>;
42 };
43 };
44
45 leds {
46 compatible = "gpio-leds";
47 pinctrl-names = "default";
48 pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>;
49
50 /* LED11 */
51 led-io-0 {
52 color = <LED_COLOR_ID_GREEN>;
53 function = LED_FUNCTION_DISK;
54 function-enumerator = <0>;
55 default-state = "off";
56 gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
57 };
58
59 /* LED12 */
60 led-io-1 {
61 color = <LED_COLOR_ID_GREEN>;
62 function = LED_FUNCTION_DISK;
63 function-enumerator = <1>;
64 default-state = "off";
65 gpios = <&cp2_gpio1 4 GPIO_ACTIVE_HIGH>;
66 };
67 };
68
69 /* CON4 W_DISABLE1/W_DISABLE2 */
70 rfkill-m2-wlan {
71 compatible = "rfkill-gpio";
72 label = "m.2 wlan (CON4)";
73 radio-type = "wlan";
74 pinctrl-names = "default";
75 pinctrl-0 = <&cp1_10g_phy_rst_01_pins>;
76 /* rfkill-gpio inverts internally */
77 shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>;
78 };
79
80 /* CON5 W_DISABLE1/W_DISABLE2 */
81 rfkill-m2-wlan {
82 compatible = "rfkill-gpio";
83 label = "m.2 wlan (CON5)";
84 radio-type = "wlan";
85 pinctrl-names = "default";
86 pinctrl-0 = <&cp1_10g_phy_rst_23_pins>;
87 /* rfkill-gpio inverts internally */
88 shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>;
89 };
90
91 /* J21 W_DISABLE1 */
92 rfkill-m2-wwan {
93 compatible = "rfkill-gpio";
94 label = "m.2 wwan (J21)";
95 radio-type = "wwan";
96 pinctrl-names = "default";
97 pinctrl-0 = <&cp2_rsvd3_pins>;
98 /* rfkill-gpio inverts internally */
99 shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
100 };
101
102 /* J21 W_DISABLE1 */
103 rfkill-m2-gnss {
104 compatible = "rfkill-gpio";
105 label = "m.2 gnss (J21)";
106 radio-type = "gps";
107 pinctrl-names = "default";
108 pinctrl-0 = <&cp2_rsvd8_pins>;
109 /* rfkill-gpio inverts internally */
110 shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>;
111 };
112
113 /* J14 W_DISABLE */
114 rfkill-mpcie-wlan {
115 compatible = "rfkill-gpio";
116 label = "mpcie wlan (J14)";
117 radio-type = "wlan";
118 pinctrl-names = "default";
119 pinctrl-0 = <&cp2_rsvd2_pins>;
120 /* rfkill-gpio inverts internally */
121 shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
122 };
123
124 sfp: sfp {
125 compatible = "sff,sfp";
126 i2c-bus = <&com_10g_sfp_i2c0>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&com_10g_int0_pins>;
129 mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
130 maximum-power-milliwatt = <2000>;
131 };
132 };
133
134 &com_smbus {
135 /* This bus is also routed to STM32 BMC Microcontroller (U2) */
136
137 power-sensor@40 {
138 compatible = "ti,ina220";
139 reg = <0x40>;
140 #io-channel-cells = <1>;
141 label = "vdd_12v0";
142 shunt-resistor = <2000>;
143 };
144
145 adc@48 {
146 compatible = "ti,tla2021";
147 reg = <0x48>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 /* supplied by chaoskey hardware noise generator circuit */
152 channel@0 {
153 reg = <0>;
154 };
155 };
156 };
157
158 &cp0_eth_phy0 {
159 /*
160 * Configure LEDs default behaviour:
161 * - LED[0]: link is 1000Mbps: On (yellow): 0111
162 * - LED[1]: link/activity: On/Blink (green): 0001
163 * - LED[2]: Off (green): 1000
164 */
165 marvell,reg-init = <3 16 0xf000 0x0817>;
166
167 leds {
168 #address-cells = <1>;
169 #size-cells = <0>;
170
171 led@0 {
172 /* link */
173 reg = <0>;
174 color = <LED_COLOR_ID_YELLOW>;
175 function = LED_FUNCTION_LAN;
176 default-state = "keep";
177 };
178
179 led@1 {
180 /* act */
181 reg = <1>;
182 color = <LED_COLOR_ID_GREEN>;
183 function = LED_FUNCTION_LAN;
184 default-state = "keep";
185 };
186
187 led@2 {
188 /* 1000 */
189 reg = <2>;
190 color = <LED_COLOR_ID_GREEN>;
191 function = LED_FUNCTION_LAN;
192 default-state = "keep";
193 };
194 };
195 };
196
197 /* SRDS #4 - 10GE */
198 &cp0_eth0 {
199 phys = <&cp0_comphy4 0>;
200 phy-mode = "10gbase-r";
201 managed = "in-band-status";
202 sfp = <&sfp>;
203 status = "okay";
204 };
205
206 &cp0_eth2 {
207 phy-mode = "2500base-x";
208 phys = <&cp0_comphy5 2>;
209 status = "okay";
210
211 fixed-link {
212 speed = <2500>;
213 full-duplex;
214 pause;
215 };
216 };
217
218 &cp0_i2c1 {
219 /*
220 * Both COM and Carrier Board have a PCA9547 i2c mux at 0x77.
221 * Describe them as a single device merging each child bus.
222 */
223
224 i2c-mux@77 {
225 i2c@0 {
226 /* Routed to Full PCIe (J4) */
227 };
228
229 i2c@1 {
230 /* Routed to USB Hub (U29) */
231 };
232
233 i2c@2 {
234 /* Routed to M.2 (CON4) */
235 };
236
237 i2c@3 {
238 /* Routed to M.2 (CON5) */
239 };
240
241 i2c@4 {
242 /* Routed to M.2 (J21) */
243 };
244
245 carrier_mpcie_i2c: i2c@5 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 reg = <5>;
249
250 /* Routed to mini-PCIe (J14) */
251 };
252
253 carrier_ptp_i2c: i2c@6 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <6>;
257
258 /* Routed to various optional PTP related components */
259 };
260 };
261 };
262
263 &cp0_mdio {
264 ethernet-switch@4 {
265 compatible = "marvell,mv88e6085";
266 reg = <4>;
267
268 mdio {
269 #address-cells = <1>;
270 #size-cells = <0>;
271
272 sw_phy1: ethernet-phy@1 {
273 reg = <0x11>;
274 };
275
276 sw_phy2: ethernet-phy@2 {
277 reg = <0x12>;
278 };
279
280 sw_phy3: ethernet-phy@3 {
281 reg = <0x13>;
282 };
283
284 sw_phy4: ethernet-phy@4 {
285 reg = <0x14>;
286 };
287 };
288
289 ethernet-ports {
290 #address-cells = <1>;
291 #size-cells = <0>;
292
293 ethernet-port@1 {
294 reg = <1>;
295 label = "lan1";
296 phy-handle = <&sw_phy1>;
297 phy-mode = "internal";
298
299 leds {
300 #address-cells = <1>;
301 #size-cells = <0>;
302
303 led@0 {
304 reg = <0>;
305 color = <LED_COLOR_ID_GREEN>;
306 function = LED_FUNCTION_LAN;
307 default-state = "keep";
308 };
309
310 led@1 {
311 reg = <1>;
312 color = <LED_COLOR_ID_YELLOW>;
313 function = LED_FUNCTION_LAN;
314 default-state = "keep";
315 };
316 };
317 };
318
319 ethernet-port@2 {
320 reg = <2>;
321 label = "lan2";
322 phy-handle = <&sw_phy2>;
323 phy-mode = "internal";
324
325 leds {
326 #address-cells = <1>;
327 #size-cells = <0>;
328
329 led@0 {
330 reg = <0>;
331 color = <LED_COLOR_ID_GREEN>;
332 function = LED_FUNCTION_LAN;
333 default-state = "keep";
334 };
335
336 led@1 {
337 reg = <1>;
338 color = <LED_COLOR_ID_YELLOW>;
339 function = LED_FUNCTION_LAN;
340 default-state = "keep";
341 };
342 };
343 };
344
345 ethernet-port@3 {
346 reg = <3>;
347 label = "lan3";
348 phy-handle = <&sw_phy3>;
349 phy-mode = "internal";
350
351 leds {
352 #address-cells = <1>;
353 #size-cells = <0>;
354
355 led@0 {
356 reg = <0>;
357 color = <LED_COLOR_ID_GREEN>;
358 function = LED_FUNCTION_LAN;
359 default-state = "keep";
360 };
361
362 led@1 {
363 reg = <1>;
364 color = <LED_COLOR_ID_YELLOW>;
365 function = LED_FUNCTION_LAN;
366 default-state = "keep";
367 };
368 };
369 };
370
371 ethernet-port@4 {
372 reg = <4>;
373 label = "lan4";
374 phy-handle = <&sw_phy4>;
375 phy-mode = "internal";
376
377 leds {
378 #address-cells = <1>;
379 #size-cells = <0>;
380
381 led@0 {
382 reg = <0>;
383 color = <LED_COLOR_ID_GREEN>;
384 function = LED_FUNCTION_LAN;
385 default-state = "keep";
386 };
387
388 led@1 {
389 reg = <1>;
390 color = <LED_COLOR_ID_YELLOW>;
391 function = LED_FUNCTION_LAN;
392 default-state = "keep";
393 };
394 };
395 };
396
397 ethernet-port@5 {
398 reg = <5>;
399 label = "cpu";
400 ethernet = <&cp0_eth2>;
401 phy-mode = "2500base-x";
402
403 fixed-link {
404 speed = <2500>;
405 full-duplex;
406 pause;
407 };
408 };
409 };
410 };
411 };
412
413 /* SRDS #0,#1,#2,#3 - PCIe */
414 &cp0_pcie0 {
415 num-lanes = <4>;
416 phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
417 status = "okay";
418 };
419
420 &cp0_pinctrl {
421 /*
422 * configure unused gpios exposed via pin headers:
423 * - J7-10: PWRBTN
424 */
425 pinctrl-names = "default";
426 pinctrl-0 = <&cp0_pwrbtn_pins>;
427 };
428
429 /* microSD */
430 &cp0_sdhci0 {
431 pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>;
432 pinctrl-names = "default";
433 bus-width = <4>;
434 no-1-8-v;
435 status = "okay";
436 };
437
438 &cp0_spi1 {
439 /* add CS1 */
440 pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>;
441
442 flash@1 {
443 compatible = "jedec,spi-nor";
444 reg = <1>;
445 /* read command supports max. 50MHz */
446 spi-max-frequency = <50000000>;
447 };
448 };
449
450 /* J38 */
451 &cp0_uart2 {
452 pinctrl-names = "default";
453 pinctrl-0 = <&cp0_uart2_pins>;
454 status = "okay";
455 };
456
457 &cp0_utmi {
458 /* M.2 "CON5" swaps D+/D- */
459 swap-dx-lanes = <1>;
460 };
461
462 &cp1_ethernet {
463 status = "okay";
464 };
465
466 /* SRDS #2 - 5GE */
467 &cp1_eth0 {
468 phys = <&cp1_comphy2 0>;
469 phy-mode = "5gbase-r";
470 phy = <&cp1_eth_phy0>;
471 managed = "in-band-status";
472 status = "okay";
473 };
474
475 /* SRDS #0,#1 - PCIe */
476 &cp1_pcie0 {
477 num-lanes = <2>;
478 phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
479 status = "okay";
480 };
481
482 /* SRDS #4 - PCIe */
483 &cp1_pcie1 {
484 num-lanes = <1>;
485 phys = <&cp1_comphy4 1>;
486 status = "okay";
487 };
488
489 /* SRDS #5 - PCIe */
490 &cp1_pcie2 {
491 num-lanes = <1>;
492 phys = <&cp1_comphy5 2>;
493 status = "okay";
494 };
495
496 &cp1_pinctrl {
497 /*
498 * configure unused gpios exposed via pin headers:
499 * - J7-8: RSVD16
500 * - J7-10: THRM
501 * - J10-1: WAKE1
502 * - J10-2: SATA_ACT
503 * - J10-8: THERMTRIP
504 */
505 pinctrl-names = "default";
506 pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>,
507 <&cp1_thrm_trip_pins &cp1_wake1_pins>;
508 };
509
510 /* SRDS #3 - SATA */
511 &cp1_sata0 {
512 status = "okay";
513
514 /* only port 1 is available */
515 /delete-node/ sata-port@0;
516
517 sata-port@1 {
518 phys = <&cp1_comphy3 1>;
519 };
520 };
521
522 &cp1_utmi {
523 /* M.2 "CON4" swaps D+/D- */
524 swap-dx-lanes = <0>;
525 };
526
527 &cp1_xmdio {
528 pinctrl-names = "default";
529 pinctrl-0 = <&cp1_xmdio_pins>;
530 status = "okay";
531
532 cp1_eth_phy0: ethernet-phy@8 {
533 compatible = "ethernet-phy-ieee802.3-c45";
534 reg = <8>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&com_10g_int1_pins>;
537 interrupt-parent = <&cp1_gpio2>;
538 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
539
540 leds {
541 #address-cells = <1>;
542 #size-cells = <0>;
543
544 led@1 {
545 reg = <1>;
546 color = <LED_COLOR_ID_YELLOW>;
547 function = LED_FUNCTION_LAN;
548 default-state = "keep";
549 };
550
551 led@2 {
552 reg = <2>;
553 color = <LED_COLOR_ID_GREEN>;
554 function = LED_FUNCTION_LAN;
555 default-state = "keep";
556 };
557 };
558 };
559 };
560
561 &cp2_ethernet {
562 status = "okay";
563 };
564
565 /* SRDS #2 - 5GE */
566 &cp2_eth0 {
567 phys = <&cp2_comphy2 0>;
568 phy-mode = "5gbase-r";
569 phy = <&cp2_eth_phy0>;
570 managed = "in-band-status";
571 status = "okay";
572 };
573
574 &cp2_gpio1 {
575 pinctrl-names= "default";
576 pinctrl-0 = <&cp2_rsvd9_pins>;
577
578 /* J21 */
579 m2-wwan-reset-hog {
580 gpio-hog;
581 gpios = <9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
582 output-low;
583 line-name = "m2-wwan-reset";
584 };
585 };
586
587 /* SRDS #0 - PCIe */
588 &cp2_pcie0 {
589 num-lanes = <1>;
590 phys = <&cp2_comphy0 0>;
591 status = "okay";
592 };
593
594 /* SRDS #4 - PCIe */
595 &cp2_pcie1 {
596 num-lanes = <1>;
597 phys = <&cp2_comphy4 1>;
598 status = "okay";
599 };
600
601 /* SRDS #5 - PCIe */
602 &cp2_pcie2 {
603 num-lanes = <1>;
604 phys = <&cp2_comphy5 2>;
605 status = "okay";
606 };
607
608 &cp2_pinctrl {
609 /*
610 * configure unused gpios exposed via pin headers:
611 * - J7-1: RSVD10
612 * - J7-3: RSVD11
613 * - J7-5: RSVD56
614 * - J7-6: RSVD7
615 * - J7-7: RSVD27
616 * - J10-3: RSVD31
617 * - J10-5: RSVD5
618 * - J10-6: RSVD32
619 * - J10-7: RSVD0
620 * - J10-9: RSVD1
621 */
622 pinctrl-names = "default";
623 pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>,
624 <&cp2_rsvd7_pins &cp2_rsvd10_pins &cp2_rsvd11_pins>,
625 <&cp2_rsvd27_pins &cp2_rsvd31_pins &cp2_rsvd32_pins>,
626 <&cp2_rsvd56_pins>;
627 };
628
629 /* SRDS #3 - SATA */
630 &cp2_sata0 {
631 status = "okay";
632
633 /* only port 1 is available */
634 /delete-node/ sata-port@0;
635
636 sata-port@1 {
637 phys = <&cp2_comphy3 1>;
638 };
639 };
640
641 &cp2_xmdio {
642 pinctrl-names = "default";
643 pinctrl-0 = <&cp2_xmdio_pins>;
644 status = "okay";
645
646 cp2_eth_phy0: ethernet-phy@8 {
647 compatible = "ethernet-phy-ieee802.3-c45";
648 reg = <8>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&com_10g_int2_pins>;
651 interrupt-parent = <&cp2_gpio2>;
652 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
653
654 leds {
655 #address-cells = <1>;
656 #size-cells = <0>;
657
658 led@1 {
659 reg = <1>;
660 color = <LED_COLOR_ID_YELLOW>;
661 function = LED_FUNCTION_LAN;
662 default-state = "keep";
663 };
664
665 led@2 {
666 reg = <2>;
667 color = <LED_COLOR_ID_GREEN>;
668 function = LED_FUNCTION_LAN;
669 default-state = "keep";
670 };
671 };
672 };
673 };
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