1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "mt8183.dtsi"
11 #include "mt6358.dtsi"
12
13 / {
14 aliases {
15 serial0 = &uart0;
16 mmc0 = &mmc0;
17 mmc1 = &mmc1;
18 };
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23
24 backlight_lcd0: backlight_lcd0 {
25 compatible = "pwm-backlight";
26 pwms = <&pwm0 0 500000>;
27 power-supply = <®_vsys>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
32 status = "okay";
33 };
34
35 memory@40000000 {
36 device_type = "memory";
37 reg = <0 0x40000000 0 0x80000000>;
38 };
39
40 clk32k: oscillator1 {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32768>;
44 clock-output-names = "clk32k";
45 };
46
47 it6505_pp18_reg: regulator0 {
48 compatible = "regulator-fixed";
49 regulator-name = "it6505_pp18";
50 gpio = <&pio 178 0>;
51 enable-active-high;
52 vin-supply = <&pp1800_alw>;
53 };
54
55 lcd_pp3300: regulator1 {
56 compatible = "regulator-fixed";
57 regulator-name = "lcd_pp3300";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 regulator-always-on;
61 regulator-boot-on;
62 };
63
64 mmc1_fixed_power: regulator3 {
65 compatible = "regulator-fixed";
66 regulator-name = "mmc1_power";
67 vin-supply = <&pp3300_alw>;
68 };
69
70 mmc1_fixed_io: regulator4 {
71 compatible = "regulator-fixed";
72 regulator-name = "mmc1_io";
73 vin-supply = <&pp1800_alw>;
74 };
75
76 pp1800_alw: regulator5 {
77 compatible = "regulator-fixed";
78 regulator-name = "pp1800_alw";
79 regulator-always-on;
80 regulator-boot-on;
81 regulator-min-microvolt = <1800000>;
82 regulator-max-microvolt = <1800000>;
83 vin-supply = <®_vsys>;
84 };
85
86 pp3300_alw: regulator6 {
87 compatible = "regulator-fixed";
88 regulator-name = "pp3300_alw";
89 regulator-always-on;
90 regulator-boot-on;
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 vin-supply = <®_vsys>;
94 };
95
96 /* system wide semi-regulated power rail from charger */
97 reg_vsys: regulator-vsys {
98 compatible = "regulator-fixed";
99 regulator-name = "vsys";
100 regulator-always-on;
101 regulator-boot-on;
102 };
103
104 reserved_memory: reserved-memory {
105 #address-cells = <2>;
106 #size-cells = <2>;
107 ranges;
108
109 scp_mem_reserved: memory@50000000 {
110 compatible = "shared-dma-pool";
111 reg = <0 0x50000000 0 0x2900000>;
112 no-map;
113 };
114 };
115
116 sound: mt8183-sound {
117 mediatek,platform = <&afe>;
118 pinctrl-names = "default",
119 "aud_tdm_out_on",
120 "aud_tdm_out_off";
121 pinctrl-0 = <&aud_pins_default>;
122 pinctrl-1 = <&aud_pins_tdm_out_on>;
123 pinctrl-2 = <&aud_pins_tdm_out_off>;
124 status = "okay";
125 };
126
127 btsco: bt-sco {
128 compatible = "linux,bt-sco";
129 };
130
131 wifi_pwrseq: wifi-pwrseq {
132 compatible = "mmc-pwrseq-simple";
133 pinctrl-names = "default";
134 pinctrl-0 = <&wifi_pins_pwrseq>;
135
136 /* Toggle WIFI_ENABLE to reset the chip. */
137 reset-gpios = <&pio 119 1>;
138 };
139
140 wifi_wakeup: wifi-wakeup {
141 compatible = "gpio-keys";
142 pinctrl-names = "default";
143 pinctrl-0 = <&wifi_pins_wakeup>;
144
145 wifi_wakeup_event: event-wowlan {
146 label = "Wake on WiFi";
147 gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
148 linux,code = <KEY_WAKEUP>;
149 wakeup-source;
150 };
151 };
152
153 tboard_thermistor1: thermal-sensor1 {
154 compatible = "generic-adc-thermal";
155 #thermal-sensor-cells = <0>;
156 io-channels = <&auxadc 0>;
157 io-channel-names = "sensor-channel";
158 temperature-lookup-table = < (-5000) 1553
159 0 1488
160 5000 1412
161 10000 1326
162 15000 1232
163 20000 1132
164 25000 1029
165 30000 925
166 35000 823
167 40000 726
168 45000 635
169 50000 552
170 55000 478
171 60000 411
172 65000 353
173 70000 303
174 75000 260
175 80000 222
176 85000 190
177 90000 163
178 95000 140
179 100000 121
180 105000 104
181 110000 90
182 115000 78
183 120000 67
184 125000 59>;
185 };
186
187 tboard_thermistor2: thermal-sensor2 {
188 compatible = "generic-adc-thermal";
189 #thermal-sensor-cells = <0>;
190 io-channels = <&auxadc 1>;
191 io-channel-names = "sensor-channel";
192 temperature-lookup-table = < (-5000) 1553
193 0 1488
194 5000 1412
195 10000 1326
196 15000 1232
197 20000 1132
198 25000 1029
199 30000 925
200 35000 823
201 40000 726
202 45000 635
203 50000 552
204 55000 478
205 60000 411
206 65000 353
207 70000 303
208 75000 260
209 80000 222
210 85000 190
211 90000 163
212 95000 140
213 100000 121
214 105000 104
215 110000 90
216 115000 78
217 120000 67
218 125000 59>;
219 };
220 };
221
222 &auxadc {
223 status = "okay";
224 };
225
226 &cci {
227 proc-supply = <&mt6358_vproc12_reg>;
228 };
229
230 &cpu0 {
231 proc-supply = <&mt6358_vproc12_reg>;
232 };
233
234 &cpu1 {
235 proc-supply = <&mt6358_vproc12_reg>;
236 };
237
238 &cpu2 {
239 proc-supply = <&mt6358_vproc12_reg>;
240 };
241
242 &cpu3 {
243 proc-supply = <&mt6358_vproc12_reg>;
244 };
245
246 &cpu4 {
247 proc-supply = <&mt6358_vproc11_reg>;
248 };
249
250 &cpu5 {
251 proc-supply = <&mt6358_vproc11_reg>;
252 };
253
254 &cpu6 {
255 proc-supply = <&mt6358_vproc11_reg>;
256 };
257
258 &cpu7 {
259 proc-supply = <&mt6358_vproc11_reg>;
260 };
261
262 &dsi0 {
263 status = "okay";
264 #address-cells = <1>;
265 #size-cells = <0>;
266 panel: panel@0 {
267 /* compatible will be set in board dts */
268 reg = <0>;
269 enable-gpios = <&pio 45 0>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&panel_pins_default>;
272 avdd-supply = <&ppvarn_lcd>;
273 avee-supply = <&ppvarp_lcd>;
274 pp1800-supply = <&pp1800_lcd>;
275 backlight = <&backlight_lcd0>;
276 rotation = <270>;
277 port {
278 panel_in: endpoint {
279 remote-endpoint = <&dsi_out>;
280 };
281 };
282 };
283
284 ports {
285 port {
286 dsi_out: endpoint {
287 remote-endpoint = <&panel_in>;
288 };
289 };
290 };
291 };
292
293 &gic {
294 mediatek,broken-save-restore-fw;
295 };
296
297 &gpu {
298 mali-supply = <&mt6358_vgpu_reg>;
299 };
300
301 &i2c0 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&i2c0_pins>;
304 status = "okay";
305 clock-frequency = <400000>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 };
309
310 &i2c1 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&i2c1_pins>;
313 status = "okay";
314 clock-frequency = <100000>;
315 };
316
317 &i2c3 {
318 pinctrl-names = "default";
319 pinctrl-0 = <&i2c3_pins>;
320 status = "okay";
321 clock-frequency = <100000>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 };
325
326 &i2c5 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c5_pins>;
329 status = "okay";
330 clock-frequency = <100000>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 };
334
335 &i2c6 {
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c6_pins>;
338 status = "okay";
339 clock-frequency = <100000>;
340 };
341
342 &mipi_tx0 {
343 status = "okay";
344 };
345
346 &mmc0 {
347 status = "okay";
348 pinctrl-names = "default", "state_uhs";
349 pinctrl-0 = <&mmc0_pins_default>;
350 pinctrl-1 = <&mmc0_pins_uhs>;
351 bus-width = <8>;
352 max-frequency = <200000000>;
353 cap-mmc-highspeed;
354 mmc-hs200-1_8v;
355 mmc-hs400-1_8v;
356 cap-mmc-hw-reset;
357 no-sdio;
358 no-sd;
359 hs400-ds-delay = <0x12814>;
360 vmmc-supply = <&mt6358_vemc_reg>;
361 vqmmc-supply = <&mt6358_vio18_reg>;
362 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
363 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
364 non-removable;
365 };
366
367 &mmc1 {
368 status = "okay";
369 pinctrl-names = "default", "state_uhs";
370 pinctrl-0 = <&mmc1_pins_default>;
371 pinctrl-1 = <&mmc1_pins_uhs>;
372 vmmc-supply = <&mmc1_fixed_power>;
373 vqmmc-supply = <&mmc1_fixed_io>;
374 mmc-pwrseq = <&wifi_pwrseq>;
375 bus-width = <4>;
376 max-frequency = <200000000>;
377 cap-sd-highspeed;
378 sd-uhs-sdr50;
379 sd-uhs-sdr104;
380 keep-power-in-suspend;
381 wakeup-source;
382 cap-sdio-irq;
383 non-removable;
384 no-mmc;
385 no-sd;
386 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
387 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390
391 qca_wifi: qca-wifi@1 {
392 compatible = "qcom,ath10k";
393 reg = <1>;
394 };
395 };
396
397 &mt6358_vdram2_reg {
398 regulator-always-on;
399 };
400
401 &mt6358codec {
402 Avdd-supply = <&mt6358_vaud28_reg>;
403 };
404
405 &mt6358regulator {
406 vsys-ldo1-supply = <®_vsys>;
407 vsys-ldo2-supply = <®_vsys>;
408 vsys-ldo3-supply = <®_vsys>;
409 vsys-vcore-supply = <®_vsys>;
410 vsys-vdram1-supply = <®_vsys>;
411 vsys-vgpu-supply = <®_vsys>;
412 vsys-vmodem-supply = <®_vsys>;
413 vsys-vpa-supply = <®_vsys>;
414 vsys-vproc11-supply = <®_vsys>;
415 vsys-vproc12-supply = <®_vsys>;
416 vsys-vs1-supply = <®_vsys>;
417 vsys-vs2-supply = <®_vsys>;
418 vs1-ldo1-supply = <&mt6358_vs1_reg>;
419 vs2-ldo1-supply = <&mt6358_vdram1_reg>;
420 vs2-ldo2-supply = <&mt6358_vs2_reg>;
421 vs2-ldo3-supply = <&mt6358_vs2_reg>;
422 vs2-ldo4-supply = <&mt6358_vs2_reg>;
423 };
424
425 &mt6358_vgpu_reg {
426 regulator-max-microvolt = <900000>;
427
428 regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
429 regulator-coupled-max-spread = <100000>;
430 };
431
432 &mt6358_vsim1_reg {
433 regulator-min-microvolt = <2700000>;
434 regulator-max-microvolt = <2700000>;
435 };
436
437 &mt6358_vsim2_reg {
438 regulator-min-microvolt = <2700000>;
439 regulator-max-microvolt = <2700000>;
440 };
441
442 &mt6358_vsram_gpu_reg {
443 regulator-min-microvolt = <850000>;
444 regulator-max-microvolt = <1000000>;
445
446 regulator-coupled-with = <&mt6358_vgpu_reg>;
447 regulator-coupled-max-spread = <100000>;
448 };
449
450 &pio {
451 aud_pins_default: audiopins {
452 pins-bus {
453 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
454 <PINMUX_GPIO98__FUNC_I2S2_BCK>,
455 <PINMUX_GPIO101__FUNC_I2S2_LRCK>,
456 <PINMUX_GPIO102__FUNC_I2S2_DI>,
457 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
458 <PINMUX_GPIO89__FUNC_I2S5_BCK>,
459 <PINMUX_GPIO90__FUNC_I2S5_LRCK>,
460 <PINMUX_GPIO91__FUNC_I2S5_DO>,
461 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
462 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
463 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
464 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
465 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
466 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
467 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
468 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
469 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
470 };
471 };
472
473 aud_pins_tdm_out_on: audiotdmouton {
474 pins-bus {
475 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
476 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
477 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
478 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
479 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
480 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
481 drive-strength = <6>;
482 };
483 };
484
485 aud_pins_tdm_out_off: audiotdmoutoff {
486 pins-bus {
487 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
488 <PINMUX_GPIO170__FUNC_GPIO170>,
489 <PINMUX_GPIO171__FUNC_GPIO171>,
490 <PINMUX_GPIO172__FUNC_GPIO172>,
491 <PINMUX_GPIO173__FUNC_GPIO173>,
492 <PINMUX_GPIO10__FUNC_GPIO10>;
493 input-enable;
494 bias-pull-down;
495 drive-strength = <2>;
496 };
497 };
498
499 bt_pins: bt-pins {
500 pins-bt-en {
501 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
502 output-low;
503 };
504 };
505
506 ec_ap_int_odl: ec-ap-int-odl {
507 pins1 {
508 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
509 input-enable;
510 bias-pull-up;
511 };
512 };
513
514 h1_int_od_l: h1-int-od-l {
515 pins1 {
516 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
517 input-enable;
518 };
519 };
520
521 i2c0_pins: i2c0 {
522 pins-bus {
523 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
524 <PINMUX_GPIO83__FUNC_SCL0>;
525 mediatek,pull-up-adv = <3>;
526 };
527 };
528
529 i2c1_pins: i2c1 {
530 pins-bus {
531 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
532 <PINMUX_GPIO84__FUNC_SCL1>;
533 mediatek,pull-up-adv = <3>;
534 };
535 };
536
537 i2c2_pins: i2c2 {
538 pins-bus {
539 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
540 <PINMUX_GPIO104__FUNC_SDA2>;
541 bias-disable;
542 };
543 };
544
545 i2c3_pins: i2c3 {
546 pins-bus {
547 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
548 <PINMUX_GPIO51__FUNC_SDA3>;
549 mediatek,pull-up-adv = <3>;
550 };
551 };
552
553 i2c4_pins: i2c4 {
554 pins-bus {
555 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
556 <PINMUX_GPIO106__FUNC_SDA4>;
557 bias-disable;
558 };
559 };
560
561 i2c5_pins: i2c5 {
562 pins-bus {
563 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
564 <PINMUX_GPIO49__FUNC_SDA5>;
565 mediatek,pull-up-adv = <3>;
566 };
567 };
568
569 i2c6_pins: i2c6 {
570 pins-bus {
571 pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
572 <PINMUX_GPIO12__FUNC_SDA6>;
573 bias-disable;
574 };
575 };
576
577 mmc0_pins_default: mmc0-pins-default {
578 pins-cmd-dat {
579 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
580 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
581 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
582 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
583 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
584 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
585 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
586 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
587 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
588 input-enable;
589 drive-strength = <MTK_DRIVE_14mA>;
590 mediatek,pull-up-adv = <01>;
591 };
592
593 pins-clk {
594 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
595 drive-strength = <MTK_DRIVE_14mA>;
596 mediatek,pull-down-adv = <10>;
597 };
598
599 pins-rst {
600 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
601 drive-strength = <MTK_DRIVE_14mA>;
602 mediatek,pull-down-adv = <01>;
603 };
604 };
605
606 mmc0_pins_uhs: mmc0-pins-uhs {
607 pins-cmd-dat {
608 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
609 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
610 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
611 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
612 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
613 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
614 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
615 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
616 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
617 input-enable;
618 drive-strength = <MTK_DRIVE_14mA>;
619 mediatek,pull-up-adv = <01>;
620 };
621
622 pins-clk {
623 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
624 drive-strength = <MTK_DRIVE_14mA>;
625 mediatek,pull-down-adv = <10>;
626 };
627
628 pins-ds {
629 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
630 drive-strength = <MTK_DRIVE_14mA>;
631 mediatek,pull-down-adv = <10>;
632 };
633
634 pins-rst {
635 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
636 drive-strength = <MTK_DRIVE_14mA>;
637 mediatek,pull-up-adv = <01>;
638 };
639 };
640
641 mmc1_pins_default: mmc1-pins-default {
642 pins-cmd-dat {
643 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
644 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
645 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
646 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
647 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
648 input-enable;
649 mediatek,pull-up-adv = <10>;
650 };
651
652 pins-clk {
653 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
654 input-enable;
655 mediatek,pull-down-adv = <10>;
656 };
657 };
658
659 mmc1_pins_uhs: mmc1-pins-uhs {
660 pins-cmd-dat {
661 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
662 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
663 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
664 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
665 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
666 drive-strength = <6>;
667 input-enable;
668 mediatek,pull-up-adv = <10>;
669 };
670
671 pins-clk {
672 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
673 drive-strength = <8>;
674 mediatek,pull-down-adv = <10>;
675 input-enable;
676 };
677 };
678
679 panel_pins_default: panel-pins-default {
680 panel-reset {
681 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
682 output-low;
683 bias-pull-up;
684 };
685 };
686
687 pwm0_pin_default: pwm0-pin-default {
688 pins1 {
689 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
690 output-high;
691 bias-pull-up;
692 };
693 pins2 {
694 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
695 };
696 };
697
698 scp_pins: scp {
699 pins-scp-uart {
700 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
701 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
702 };
703 };
704
705 spi0_pins: spi0 {
706 pins-spi {
707 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
708 <PINMUX_GPIO86__FUNC_GPIO86>,
709 <PINMUX_GPIO87__FUNC_SPI0_MO>,
710 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
711 bias-disable;
712 };
713 };
714
715 spi1_pins: spi1 {
716 pins-spi {
717 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
718 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
719 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
720 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
721 bias-disable;
722 };
723 };
724
725 spi2_pins: spi2 {
726 pins-spi {
727 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
728 <PINMUX_GPIO1__FUNC_SPI2_MO>,
729 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
730 bias-disable;
731 };
732 pins-spi-mi {
733 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
734 mediatek,pull-down-adv = <00>;
735 };
736 };
737
738 spi3_pins: spi3 {
739 pins-spi {
740 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
741 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
742 <PINMUX_GPIO23__FUNC_SPI3_MO>,
743 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
744 bias-disable;
745 };
746 };
747
748 spi4_pins: spi4 {
749 pins-spi {
750 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
751 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
752 <PINMUX_GPIO19__FUNC_SPI4_MO>,
753 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
754 bias-disable;
755 };
756 };
757
758 spi5_pins: spi5 {
759 pins-spi {
760 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
761 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
762 <PINMUX_GPIO15__FUNC_SPI5_MO>,
763 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
764 bias-disable;
765 };
766 };
767
768 uart0_pins_default: uart0-pins-default {
769 pins-rx {
770 pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
771 input-enable;
772 bias-pull-up;
773 };
774 pins-tx {
775 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
776 };
777 };
778
779 uart1_pins_default: uart1-pins-default {
780 pins-rx {
781 pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
782 input-enable;
783 bias-pull-up;
784 };
785 pins-tx {
786 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
787 };
788 pins-rts {
789 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
790 };
791 pins-cts {
792 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
793 input-enable;
794 };
795 };
796
797 uart1_pins_sleep: uart1-pins-sleep {
798 pins-rx {
799 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
800 input-enable;
801 bias-pull-up;
802 };
803 pins-tx {
804 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
805 };
806 pins-rts {
807 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
808 };
809 pins-cts {
810 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
811 input-enable;
812 };
813 };
814
815 wifi_pins_pwrseq: wifi-pins-pwrseq {
816 pins-wifi-enable {
817 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
818 output-low;
819 };
820 };
821
822 wifi_pins_wakeup: wifi-pins-wakeup {
823 pins-wifi-wakeup {
824 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
825 input-enable;
826 };
827 };
828 };
829
830 &pmic {
831 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
832 };
833
834 &pwm0 {
835 status = "okay";
836 pinctrl-names = "default";
837 pinctrl-0 = <&pwm0_pin_default>;
838 };
839
840 &scp {
841 status = "okay";
842
843 firmware-name = "mediatek/mt8183/scp.img";
844 pinctrl-names = "default";
845 pinctrl-0 = <&scp_pins>;
846
847 cros-ec-rpmsg {
848 compatible = "google,cros-ec-rpmsg";
849 mediatek,rpmsg-name = "cros-ec-rpmsg";
850 };
851 };
852
853 &mfg_async {
854 domain-supply = <&mt6358_vsram_gpu_reg>;
855 };
856
857 &mfg {
858 domain-supply = <&mt6358_vgpu_reg>;
859 };
860
861 &spi0 {
862 pinctrl-names = "default";
863 pinctrl-0 = <&spi0_pins>;
864 mediatek,pad-select = <0>;
865 status = "okay";
866 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
867
868 tpm@0 {
869 compatible = "google,cr50";
870 reg = <0>;
871 spi-max-frequency = <1000000>;
872 pinctrl-names = "default";
873 pinctrl-0 = <&h1_int_od_l>;
874 interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>;
875 };
876 };
877
878 &spi1 {
879 pinctrl-names = "default";
880 pinctrl-0 = <&spi1_pins>;
881 mediatek,pad-select = <0>;
882 status = "okay";
883
884 w25q64dw: flash@0 {
885 compatible = "winbond,w25q64dw", "jedec,spi-nor";
886 reg = <0>;
887 spi-max-frequency = <25000000>;
888 };
889 };
890
891 &spi2 {
892 pinctrl-names = "default";
893 pinctrl-0 = <&spi2_pins>;
894 mediatek,pad-select = <0>;
895 status = "okay";
896
897 cros_ec: cros-ec@0 {
898 compatible = "google,cros-ec-spi";
899 reg = <0>;
900 spi-max-frequency = <3000000>;
901 interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>;
902 pinctrl-names = "default";
903 pinctrl-0 = <&ec_ap_int_odl>;
904 wakeup-source;
905
906 i2c_tunnel: i2c-tunnel {
907 compatible = "google,cros-ec-i2c-tunnel";
908 google,remote-bus = <1>;
909 #address-cells = <1>;
910 #size-cells = <0>;
911 };
912
913 usbc_extcon: extcon0 {
914 compatible = "google,extcon-usbc-cros-ec";
915 google,usb-port-id = <0>;
916 };
917
918 typec {
919 compatible = "google,cros-ec-typec";
920 #address-cells = <1>;
921 #size-cells = <0>;
922
923 usb_c0: connector@0 {
924 compatible = "usb-c-connector";
925 reg = <0>;
926 power-role = "dual";
927 data-role = "host";
928 try-power-role = "sink";
929 };
930 };
931 };
932 };
933
934 &spi3 {
935 pinctrl-names = "default";
936 pinctrl-0 = <&spi3_pins>;
937 mediatek,pad-select = <0>;
938 status = "disabled";
939 };
940
941 &spi4 {
942 pinctrl-names = "default";
943 pinctrl-0 = <&spi4_pins>;
944 mediatek,pad-select = <0>;
945 status = "disabled";
946 };
947
948 &spi5 {
949 pinctrl-names = "default";
950 pinctrl-0 = <&spi5_pins>;
951 mediatek,pad-select = <0>;
952 status = "disabled";
953 };
954
955 &ssusb {
956 dr_mode = "host";
957 wakeup-source;
958 vusb33-supply = <&mt6358_vusb_reg>;
959 status = "okay";
960 };
961
962 &thermal_zones {
963 tboard1 {
964 polling-delay = <1000>; /* milliseconds */
965 polling-delay-passive = <0>; /* milliseconds */
966 thermal-sensors = <&tboard_thermistor1>;
967 };
968
969 tboard2 {
970 polling-delay = <1000>; /* milliseconds */
971 polling-delay-passive = <0>; /* milliseconds */
972 thermal-sensors = <&tboard_thermistor2>;
973 };
974 };
975
976 &u3phy {
977 status = "okay";
978 };
979
980 &uart0 {
981 pinctrl-names = "default";
982 pinctrl-0 = <&uart0_pins_default>;
983 status = "okay";
984 };
985
986 &uart1 {
987 pinctrl-names = "default", "sleep";
988 pinctrl-0 = <&uart1_pins_default>;
989 pinctrl-1 = <&uart1_pins_sleep>;
990 status = "okay";
991 /delete-property/ interrupts;
992 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
993 <&pio 121 IRQ_TYPE_EDGE_FALLING>;
994
995 bluetooth: bluetooth {
996 pinctrl-names = "default";
997 pinctrl-0 = <&bt_pins>;
998 status = "okay";
999 compatible = "qcom,qca6174-bt";
1000 enable-gpios = <&pio 120 0>;
1001 clocks = <&clk32k>;
1002 firmware-name = "nvm_00440302_i2s.bin";
1003 };
1004 };
1005
1006 &usb_host {
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1009 vusb33-supply = <&mt6358_vusb_reg>;
1010 status = "okay";
1011
1012 hub@1 {
1013 compatible = "usb5e3,610";
1014 reg = <1>;
1015 };
1016 };
1017
1018 #include <arm/cros-ec-sbs.dtsi>
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