1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2023 MediaTek Inc.
4 *
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
14 #include <dt-bindings/power/mediatek,mt8188-power.h>
15 #include <dt-bindings/reset/mt8188-resets.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
18
19 / {
20 compatible = "mediatek,mt8188";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a55";
32 reg = <0x000>;
33 enable-method = "psci";
34 clock-frequency = <2000000000>;
35 capacity-dmips-mhz = <282>;
36 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
37 i-cache-size = <32768>;
38 i-cache-line-size = <64>;
39 i-cache-sets = <128>;
40 d-cache-size = <32768>;
41 d-cache-line-size = <64>;
42 d-cache-sets = <128>;
43 next-level-cache = <&l2_0>;
44 #cooling-cells = <2>;
45 };
46
47 cpu1: cpu@100 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a55";
50 reg = <0x100>;
51 enable-method = "psci";
52 clock-frequency = <2000000000>;
53 capacity-dmips-mhz = <282>;
54 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
55 i-cache-size = <32768>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <128>;
58 d-cache-size = <32768>;
59 d-cache-line-size = <64>;
60 d-cache-sets = <128>;
61 next-level-cache = <&l2_0>;
62 #cooling-cells = <2>;
63 };
64
65 cpu2: cpu@200 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a55";
68 reg = <0x200>;
69 enable-method = "psci";
70 clock-frequency = <2000000000>;
71 capacity-dmips-mhz = <282>;
72 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
73 i-cache-size = <32768>;
74 i-cache-line-size = <64>;
75 i-cache-sets = <128>;
76 d-cache-size = <32768>;
77 d-cache-line-size = <64>;
78 d-cache-sets = <128>;
79 next-level-cache = <&l2_0>;
80 #cooling-cells = <2>;
81 };
82
83 cpu3: cpu@300 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a55";
86 reg = <0x300>;
87 enable-method = "psci";
88 clock-frequency = <2000000000>;
89 capacity-dmips-mhz = <282>;
90 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
91 i-cache-size = <32768>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <128>;
94 d-cache-size = <32768>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&l2_0>;
98 #cooling-cells = <2>;
99 };
100
101 cpu4: cpu@400 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a55";
104 reg = <0x400>;
105 enable-method = "psci";
106 clock-frequency = <2000000000>;
107 capacity-dmips-mhz = <282>;
108 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
109 i-cache-size = <32768>;
110 i-cache-line-size = <64>;
111 i-cache-sets = <128>;
112 d-cache-size = <32768>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <128>;
115 next-level-cache = <&l2_0>;
116 #cooling-cells = <2>;
117 };
118
119 cpu5: cpu@500 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a55";
122 reg = <0x500>;
123 enable-method = "psci";
124 clock-frequency = <2000000000>;
125 capacity-dmips-mhz = <282>;
126 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
127 i-cache-size = <32768>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <128>;
130 d-cache-size = <32768>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&l2_0>;
134 #cooling-cells = <2>;
135 };
136
137 cpu6: cpu@600 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a78";
140 reg = <0x600>;
141 enable-method = "psci";
142 clock-frequency = <2600000000>;
143 capacity-dmips-mhz = <1024>;
144 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
145 i-cache-size = <65536>;
146 i-cache-line-size = <64>;
147 i-cache-sets = <256>;
148 d-cache-size = <65536>;
149 d-cache-line-size = <64>;
150 d-cache-sets = <256>;
151 next-level-cache = <&l2_1>;
152 #cooling-cells = <2>;
153 };
154
155 cpu7: cpu@700 {
156 device_type = "cpu";
157 compatible = "arm,cortex-a78";
158 reg = <0x700>;
159 enable-method = "psci";
160 clock-frequency = <2600000000>;
161 capacity-dmips-mhz = <1024>;
162 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
163 i-cache-size = <65536>;
164 i-cache-line-size = <64>;
165 i-cache-sets = <256>;
166 d-cache-size = <65536>;
167 d-cache-line-size = <64>;
168 d-cache-sets = <256>;
169 next-level-cache = <&l2_1>;
170 #cooling-cells = <2>;
171 };
172
173 cpu-map {
174 cluster0 {
175 core0 {
176 cpu = <&cpu0>;
177 };
178
179 core1 {
180 cpu = <&cpu1>;
181 };
182
183 core2 {
184 cpu = <&cpu2>;
185 };
186
187 core3 {
188 cpu = <&cpu3>;
189 };
190
191 core4 {
192 cpu = <&cpu4>;
193 };
194
195 core5 {
196 cpu = <&cpu5>;
197 };
198
199 core6 {
200 cpu = <&cpu6>;
201 };
202
203 core7 {
204 cpu = <&cpu7>;
205 };
206 };
207 };
208
209 idle-states {
210 entry-method = "psci";
211
212 cpu_off_l: cpu-off-l {
213 compatible = "arm,idle-state";
214 arm,psci-suspend-param = <0x00010000>;
215 local-timer-stop;
216 entry-latency-us = <50>;
217 exit-latency-us = <95>;
218 min-residency-us = <580>;
219 };
220
221 cpu_off_b: cpu-off-b {
222 compatible = "arm,idle-state";
223 arm,psci-suspend-param = <0x00010000>;
224 local-timer-stop;
225 entry-latency-us = <45>;
226 exit-latency-us = <140>;
227 min-residency-us = <740>;
228 };
229
230 cluster_off_l: cluster-off-l {
231 compatible = "arm,idle-state";
232 arm,psci-suspend-param = <0x01010010>;
233 local-timer-stop;
234 entry-latency-us = <55>;
235 exit-latency-us = <155>;
236 min-residency-us = <840>;
237 };
238
239 cluster_off_b: cluster-off-b {
240 compatible = "arm,idle-state";
241 arm,psci-suspend-param = <0x01010010>;
242 local-timer-stop;
243 entry-latency-us = <50>;
244 exit-latency-us = <200>;
245 min-residency-us = <1000>;
246 };
247 };
248
249 l2_0: l2-cache0 {
250 compatible = "cache";
251 cache-level = <2>;
252 cache-size = <131072>;
253 cache-line-size = <64>;
254 cache-sets = <512>;
255 next-level-cache = <&l3_0>;
256 cache-unified;
257 };
258
259 l2_1: l2-cache1 {
260 compatible = "cache";
261 cache-level = <2>;
262 cache-size = <262144>;
263 cache-line-size = <64>;
264 cache-sets = <512>;
265 next-level-cache = <&l3_0>;
266 cache-unified;
267 };
268
269 l3_0: l3-cache {
270 compatible = "cache";
271 cache-level = <3>;
272 cache-size = <2097152>;
273 cache-line-size = <64>;
274 cache-sets = <2048>;
275 cache-unified;
276 };
277 };
278
279 clk13m: oscillator-13m {
280 compatible = "fixed-clock";
281 #clock-cells = <0>;
282 clock-frequency = <13000000>;
283 clock-output-names = "clk13m";
284 };
285
286 clk26m: oscillator-26m {
287 compatible = "fixed-clock";
288 #clock-cells = <0>;
289 clock-frequency = <26000000>;
290 clock-output-names = "clk26m";
291 };
292
293 clk32k: oscillator-32k {
294 compatible = "fixed-clock";
295 #clock-cells = <0>;
296 clock-frequency = <32768>;
297 clock-output-names = "clk32k";
298 };
299
300 gpu_opp_table: opp-table-gpu {
301 compatible = "operating-points-v2";
302 opp-shared;
303
304 opp-390000000 {
305 opp-hz = /bits/ 64 <390000000>;
306 opp-microvolt = <575000>;
307 opp-supported-hw = <0xff>;
308 };
309 opp-431000000 {
310 opp-hz = /bits/ 64 <431000000>;
311 opp-microvolt = <587500>;
312 opp-supported-hw = <0xff>;
313 };
314 opp-473000000 {
315 opp-hz = /bits/ 64 <473000000>;
316 opp-microvolt = <600000>;
317 opp-supported-hw = <0xff>;
318 };
319 opp-515000000 {
320 opp-hz = /bits/ 64 <515000000>;
321 opp-microvolt = <612500>;
322 opp-supported-hw = <0xff>;
323 };
324 opp-556000000 {
325 opp-hz = /bits/ 64 <556000000>;
326 opp-microvolt = <625000>;
327 opp-supported-hw = <0xff>;
328 };
329 opp-598000000 {
330 opp-hz = /bits/ 64 <598000000>;
331 opp-microvolt = <637500>;
332 opp-supported-hw = <0xff>;
333 };
334 opp-640000000 {
335 opp-hz = /bits/ 64 <640000000>;
336 opp-microvolt = <650000>;
337 opp-supported-hw = <0xff>;
338 };
339 opp-670000000 {
340 opp-hz = /bits/ 64 <670000000>;
341 opp-microvolt = <662500>;
342 opp-supported-hw = <0xff>;
343 };
344 opp-700000000 {
345 opp-hz = /bits/ 64 <700000000>;
346 opp-microvolt = <675000>;
347 opp-supported-hw = <0xff>;
348 };
349 opp-730000000 {
350 opp-hz = /bits/ 64 <730000000>;
351 opp-microvolt = <687500>;
352 opp-supported-hw = <0xff>;
353 };
354 opp-760000000 {
355 opp-hz = /bits/ 64 <760000000>;
356 opp-microvolt = <700000>;
357 opp-supported-hw = <0xff>;
358 };
359 opp-790000000 {
360 opp-hz = /bits/ 64 <790000000>;
361 opp-microvolt = <712500>;
362 opp-supported-hw = <0xff>;
363 };
364 opp-835000000 {
365 opp-hz = /bits/ 64 <835000000>;
366 opp-microvolt = <731250>;
367 opp-supported-hw = <0xff>;
368 };
369 opp-880000000 {
370 opp-hz = /bits/ 64 <880000000>;
371 opp-microvolt = <750000>;
372 opp-supported-hw = <0xff>;
373 };
374 opp-915000000 {
375 opp-hz = /bits/ 64 <915000000>;
376 opp-microvolt = <775000>;
377 opp-supported-hw = <0x8f>;
378 };
379 opp-915000000-5 {
380 opp-hz = /bits/ 64 <915000000>;
381 opp-microvolt = <762500>;
382 opp-supported-hw = <0x30>;
383 };
384 opp-915000000-6 {
385 opp-hz = /bits/ 64 <915000000>;
386 opp-microvolt = <750000>;
387 opp-supported-hw = <0x70>;
388 };
389 opp-950000000 {
390 opp-hz = /bits/ 64 <950000000>;
391 opp-microvolt = <800000>;
392 opp-supported-hw = <0x8f>;
393 };
394 opp-950000000-5 {
395 opp-hz = /bits/ 64 <950000000>;
396 opp-microvolt = <775000>;
397 opp-supported-hw = <0x30>;
398 };
399 opp-950000000-6 {
400 opp-hz = /bits/ 64 <950000000>;
401 opp-microvolt = <750000>;
402 opp-supported-hw = <0x70>;
403 };
404 };
405
406 pmu-a55 {
407 compatible = "arm,cortex-a55-pmu";
408 interrupt-parent = <&gic>;
409 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
410 };
411
412 pmu-a78 {
413 compatible = "arm,cortex-a78-pmu";
414 interrupt-parent = <&gic>;
415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
416 };
417
418 psci {
419 compatible = "arm,psci-1.0";
420 method = "smc";
421 };
422
423 thermal_zones: thermal-zones {
424 cpu-little0-thermal {
425 polling-delay = <1000>;
426 polling-delay-passive = <150>;
427 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
428
429 trips {
430 cpu_little0_alert0: trip-alert0 {
431 temperature = <85000>;
432 hysteresis = <2000>;
433 type = "passive";
434 };
435
436 cpu_little0_alert1: trip-alert1 {
437 temperature = <95000>;
438 hysteresis = <2000>;
439 type = "hot";
440 };
441
442 cpu_little0_crit: trip-crit {
443 temperature = <100000>;
444 hysteresis = <0>;
445 type = "critical";
446 };
447 };
448
449 cooling-maps {
450 map0 {
451 trip = <&cpu_little0_alert0>;
452 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
453 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
454 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
455 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
456 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
457 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
458 };
459 };
460 };
461
462 cpu-little1-thermal {
463 polling-delay = <1000>;
464 polling-delay-passive = <150>;
465 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
466
467 trips {
468 cpu_little1_alert0: trip-alert0 {
469 temperature = <85000>;
470 hysteresis = <2000>;
471 type = "passive";
472 };
473
474 cpu_little1_alert1: trip-alert1 {
475 temperature = <95000>;
476 hysteresis = <2000>;
477 type = "hot";
478 };
479
480 cpu_little1_crit: trip-crit {
481 temperature = <100000>;
482 hysteresis = <0>;
483 type = "critical";
484 };
485 };
486
487 cooling-maps {
488 map0 {
489 trip = <&cpu_little1_alert0>;
490 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
491 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
492 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
493 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
494 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
495 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
496 };
497 };
498 };
499
500 cpu-little2-thermal {
501 polling-delay = <1000>;
502 polling-delay-passive = <150>;
503 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
504
505 trips {
506 cpu_little2_alert0: trip-alert0 {
507 temperature = <85000>;
508 hysteresis = <2000>;
509 type = "passive";
510 };
511
512 cpu_little2_alert1: trip-alert1 {
513 temperature = <95000>;
514 hysteresis = <2000>;
515 type = "hot";
516 };
517
518 cpu_little2_crit: trip-crit {
519 temperature = <100000>;
520 hysteresis = <0>;
521 type = "critical";
522 };
523 };
524
525 cooling-maps {
526 map0 {
527 trip = <&cpu_little2_alert0>;
528 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
529 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
530 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
531 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
532 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
533 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
534 };
535 };
536 };
537
538 cpu-little3-thermal {
539 polling-delay = <1000>;
540 polling-delay-passive = <150>;
541 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
542
543 trips {
544 cpu_little3_alert0: trip-alert0 {
545 temperature = <85000>;
546 hysteresis = <2000>;
547 type = "passive";
548 };
549
550 cpu_little3_alert1: trip-alert1 {
551 temperature = <95000>;
552 hysteresis = <2000>;
553 type = "hot";
554 };
555
556 cpu_little3_crit: trip-crit {
557 temperature = <100000>;
558 hysteresis = <0>;
559 type = "critical";
560 };
561 };
562
563 cooling-maps {
564 map0 {
565 trip = <&cpu_little3_alert0>;
566 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
567 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
568 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
569 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
570 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
571 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
572 };
573 };
574 };
575
576 cpu-big0-thermal {
577 polling-delay = <1000>;
578 polling-delay-passive = <100>;
579 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
580
581 trips {
582 cpu_big0_alert0: trip-alert0 {
583 temperature = <85000>;
584 hysteresis = <2000>;
585 type = "passive";
586 };
587
588 cpu_big0_alert1: trip-alert1 {
589 temperature = <95000>;
590 hysteresis = <2000>;
591 type = "hot";
592 };
593
594 cpu_big0_crit: trip-crit {
595 temperature = <100000>;
596 hysteresis = <0>;
597 type = "critical";
598 };
599 };
600
601 cooling-maps {
602 map0 {
603 trip = <&cpu_big0_alert0>;
604 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
605 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
606 };
607 };
608 };
609
610 cpu-big1-thermal {
611 polling-delay = <1000>;
612 polling-delay-passive = <100>;
613 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
614
615 trips {
616 cpu_big1_alert0: trip-alert0 {
617 temperature = <85000>;
618 hysteresis = <2000>;
619 type = "passive";
620 };
621
622 cpu_big1_alert1: trip-alert1 {
623 temperature = <95000>;
624 hysteresis = <2000>;
625 type = "hot";
626 };
627
628 cpu_big1_crit: trip-crit {
629 temperature = <100000>;
630 hysteresis = <0>;
631 type = "critical";
632 };
633 };
634
635 cooling-maps {
636 map0 {
637 trip = <&cpu_big1_alert0>;
638 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
639 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
640 };
641 };
642 };
643
644 apu-thermal {
645 polling-delay = <1000>;
646 polling-delay-passive = <250>;
647 thermal-sensors = <&lvts_ap MT8188_AP_APU>;
648
649 trips {
650 apu_alert0: trip-alert0 {
651 temperature = <85000>;
652 hysteresis = <2000>;
653 type = "passive";
654 };
655
656 apu_alert1: trip-alert1 {
657 temperature = <95000>;
658 hysteresis = <2000>;
659 type = "hot";
660 };
661
662 apu_crit: trip-crit {
663 temperature = <100000>;
664 hysteresis = <0>;
665 type = "critical";
666 };
667 };
668 };
669
670 gpu-thermal {
671 polling-delay = <1000>;
672 polling-delay-passive = <250>;
673 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>;
674
675 trips {
676 gpu_alert0: trip-alert0 {
677 temperature = <85000>;
678 hysteresis = <2000>;
679 type = "passive";
680 };
681
682 gpu_alert1: trip-alert1 {
683 temperature = <95000>;
684 hysteresis = <2000>;
685 type = "hot";
686 };
687
688 gpu_crit: trip-crit {
689 temperature = <100000>;
690 hysteresis = <0>;
691 type = "critical";
692 };
693 };
694
695 cooling-maps {
696 map0 {
697 trip = <&gpu_alert0>;
698 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
699 };
700 };
701 };
702
703 gpu1-thermal {
704 polling-delay = <1000>;
705 polling-delay-passive = <250>;
706 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>;
707
708 trips {
709 gpu1_alert0: trip-alert0 {
710 temperature = <85000>;
711 hysteresis = <2000>;
712 type = "passive";
713 };
714
715 gpu1_alert1: trip-alert1 {
716 temperature = <95000>;
717 hysteresis = <2000>;
718 type = "hot";
719 };
720
721 gpu1_crit: trip-crit {
722 temperature = <100000>;
723 hysteresis = <0>;
724 type = "critical";
725 };
726 };
727
728 cooling-maps {
729 map0 {
730 trip = <&gpu1_alert0>;
731 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
732 };
733 };
734 };
735
736 adsp-thermal {
737 polling-delay = <1000>;
738 polling-delay-passive = <250>;
739 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>;
740
741 trips {
742 soc_alert0: trip-alert0 {
743 temperature = <85000>;
744 hysteresis = <2000>;
745 type = "passive";
746 };
747
748 soc_alert1: trip-alert1 {
749 temperature = <95000>;
750 hysteresis = <2000>;
751 type = "hot";
752 };
753
754 soc_crit: trip-crit {
755 temperature = <100000>;
756 hysteresis = <0>;
757 type = "critical";
758 };
759 };
760 };
761
762 vdo-thermal {
763 polling-delay = <1000>;
764 polling-delay-passive = <250>;
765 thermal-sensors = <&lvts_ap MT8188_AP_VDO>;
766
767 trips {
768 soc1_alert0: trip-alert0 {
769 temperature = <85000>;
770 hysteresis = <2000>;
771 type = "passive";
772 };
773
774 soc1_alert1: trip-alert1 {
775 temperature = <95000>;
776 hysteresis = <2000>;
777 type = "hot";
778 };
779
780 soc1_crit: trip-crit {
781 temperature = <100000>;
782 hysteresis = <0>;
783 type = "critical";
784 };
785 };
786 };
787
788 infra-thermal {
789 polling-delay = <1000>;
790 polling-delay-passive = <250>;
791 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>;
792
793 trips {
794 soc2_alert0: trip-alert0 {
795 temperature = <85000>;
796 hysteresis = <2000>;
797 type = "passive";
798 };
799
800 soc2_alert1: trip-alert1 {
801 temperature = <95000>;
802 hysteresis = <2000>;
803 type = "hot";
804 };
805
806 soc2_crit: trip-crit {
807 temperature = <100000>;
808 hysteresis = <0>;
809 type = "critical";
810 };
811 };
812 };
813
814 cam1-thermal {
815 polling-delay = <1000>;
816 polling-delay-passive = <250>;
817 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>;
818
819 trips {
820 cam1_alert0: trip-alert0 {
821 temperature = <85000>;
822 hysteresis = <2000>;
823 type = "passive";
824 };
825
826 cam1_alert1: trip-alert1 {
827 temperature = <95000>;
828 hysteresis = <2000>;
829 type = "hot";
830 };
831
832 cam1_crit: trip-crit {
833 temperature = <100000>;
834 hysteresis = <0>;
835 type = "critical";
836 };
837 };
838 };
839
840 cam2-thermal {
841 polling-delay = <1000>;
842 polling-delay-passive = <250>;
843 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>;
844
845 trips {
846 cam2_alert0: trip-alert0 {
847 temperature = <85000>;
848 hysteresis = <2000>;
849 type = "passive";
850 };
851
852 cam2_alert1: trip-alert1 {
853 temperature = <95000>;
854 hysteresis = <2000>;
855 type = "hot";
856 };
857
858 cam2_crit: trip-crit {
859 temperature = <100000>;
860 hysteresis = <0>;
861 type = "critical";
862 };
863 };
864 };
865 };
866
867 timer: timer {
868 compatible = "arm,armv8-timer";
869 interrupt-parent = <&gic>;
870 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
871 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
872 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
873 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
874 clock-frequency = <13000000>;
875 };
876
877 soc {
878 #address-cells = <2>;
879 #size-cells = <2>;
880 compatible = "simple-bus";
881 ranges;
882
883 gic: interrupt-controller@c000000 {
884 compatible = "arm,gic-v3";
885 #interrupt-cells = <4>;
886 #redistributor-regions = <1>;
887 interrupt-parent = <&gic>;
888 interrupt-controller;
889 reg = <0 0x0c000000 0 0x40000>,
890 <0 0x0c040000 0 0x200000>;
891 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
892
893 ppi-partitions {
894 ppi_cluster0: interrupt-partition-0 {
895 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
896 };
897
898 ppi_cluster1: interrupt-partition-1 {
899 affinity = <&cpu6 &cpu7>;
900 };
901 };
902 };
903
904 topckgen: syscon@10000000 {
905 compatible = "mediatek,mt8188-topckgen", "syscon";
906 reg = <0 0x10000000 0 0x1000>;
907 #clock-cells = <1>;
908 };
909
910 infracfg_ao: syscon@10001000 {
911 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
912 reg = <0 0x10001000 0 0x1000>;
913 #clock-cells = <1>;
914 #reset-cells = <1>;
915 };
916
917 pericfg: syscon@10003000 {
918 compatible = "mediatek,mt8188-pericfg", "syscon";
919 reg = <0 0x10003000 0 0x1000>;
920 #clock-cells = <1>;
921 };
922
923 pio: pinctrl@10005000 {
924 compatible = "mediatek,mt8188-pinctrl";
925 reg = <0 0x10005000 0 0x1000>,
926 <0 0x11c00000 0 0x1000>,
927 <0 0x11e10000 0 0x1000>,
928 <0 0x11e20000 0 0x1000>,
929 <0 0x11ea0000 0 0x1000>,
930 <0 0x1000b000 0 0x1000>;
931 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
932 "iocfg_lm", "iocfg_rt", "eint";
933 gpio-controller;
934 #gpio-cells = <2>;
935 gpio-ranges = <&pio 0 0 176>;
936 interrupt-controller;
937 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
938 #interrupt-cells = <2>;
939 };
940
941 scpsys: syscon@10006000 {
942 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
943 reg = <0 0x10006000 0 0x1000>;
944
945 /* System Power Manager */
946 spm: power-controller {
947 compatible = "mediatek,mt8188-power-controller";
948 #address-cells = <1>;
949 #size-cells = <0>;
950 #power-domain-cells = <1>;
951
952 /* power domain of the SoC */
953 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
954 reg = <MT8188_POWER_DOMAIN_MFG0>;
955 #address-cells = <1>;
956 #size-cells = <0>;
957 #power-domain-cells = <1>;
958
959 power-domain@MT8188_POWER_DOMAIN_MFG1 {
960 reg = <MT8188_POWER_DOMAIN_MFG1>;
961 clocks = <&topckgen CLK_APMIXED_MFGPLL>,
962 <&topckgen CLK_TOP_MFG_CORE_TMP>;
963 clock-names = "mfg", "alt";
964 mediatek,infracfg = <&infracfg_ao>;
965 #address-cells = <1>;
966 #size-cells = <0>;
967 #power-domain-cells = <1>;
968
969 power-domain@MT8188_POWER_DOMAIN_MFG2 {
970 reg = <MT8188_POWER_DOMAIN_MFG2>;
971 #power-domain-cells = <0>;
972 };
973
974 power-domain@MT8188_POWER_DOMAIN_MFG3 {
975 reg = <MT8188_POWER_DOMAIN_MFG3>;
976 #power-domain-cells = <0>;
977 };
978
979 power-domain@MT8188_POWER_DOMAIN_MFG4 {
980 reg = <MT8188_POWER_DOMAIN_MFG4>;
981 #power-domain-cells = <0>;
982 };
983 };
984 };
985
986 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
987 reg = <MT8188_POWER_DOMAIN_VPPSYS0>;
988 clocks = <&topckgen CLK_TOP_VPP>,
989 <&topckgen CLK_TOP_CAM>,
990 <&topckgen CLK_TOP_CCU>,
991 <&topckgen CLK_TOP_IMG>,
992 <&topckgen CLK_TOP_VENC>,
993 <&topckgen CLK_TOP_VDEC>,
994 <&topckgen CLK_TOP_WPE_VPP>,
995 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
996 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
997 <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>,
998 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>,
999 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>,
1000 <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>,
1001 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>,
1002 <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>,
1003 <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>,
1004 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>,
1005 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>,
1006 <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>,
1007 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
1008 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
1009 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
1010 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
1011 <&vppsys0 CLK_VPP0_SMI_RSI>,
1012 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1013 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1014 <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>,
1015 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
1016 clock-names = "top", "cam", "ccu", "img", "venc",
1017 "vdec", "wpe", "cfgck", "cfgxo",
1018 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
1019 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
1020 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
1021 "ss-sram-rdr", "ss-iommu", "ss-imgcam",
1022 "ss-emi", "ss-subcmn-rdr", "ss-rsi",
1023 "ss-cmn-l4", "ss-vdec1", "ss-wpe",
1024 "ss-cvdo-ve1";
1025 mediatek,infracfg = <&infracfg_ao>;
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028 #power-domain-cells = <1>;
1029
1030 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
1031 reg = <MT8188_POWER_DOMAIN_VDOSYS0>;
1032 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>,
1033 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>,
1034 <&vdosys0 CLK_VDO0_SMI_GALS>,
1035 <&vdosys0 CLK_VDO0_SMI_COMMON>,
1036 <&vdosys0 CLK_VDO0_SMI_EMI>,
1037 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
1038 <&vdosys0 CLK_VDO0_SMI_LARB>,
1039 <&vdosys0 CLK_VDO0_SMI_RSI>,
1040 <&vdosys0 CLK_VDO0_APB_BUS>;
1041 clock-names = "cfgck", "cfgxo", "ss-gals",
1042 "ss-cmn", "ss-emi", "ss-iommu",
1043 "ss-larb", "ss-rsi", "ss-bus";
1044 mediatek,infracfg = <&infracfg_ao>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 #power-domain-cells = <1>;
1048
1049 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
1050 reg = <MT8188_POWER_DOMAIN_VPPSYS1>;
1051 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
1052 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>,
1053 <&vppsys1 CLK_VPP1_GALS5>,
1054 <&vppsys1 CLK_VPP1_GALS6>,
1055 <&vppsys1 CLK_VPP1_LARB5>,
1056 <&vppsys1 CLK_VPP1_LARB6>;
1057 clock-names = "cfgck", "cfgxo",
1058 "ss-vpp1-g5", "ss-vpp1-g6",
1059 "ss-vpp1-l5", "ss-vpp1-l6";
1060 mediatek,infracfg = <&infracfg_ao>;
1061 #power-domain-cells = <0>;
1062 };
1063
1064 power-domain@MT8188_POWER_DOMAIN_VDEC1 {
1065 reg = <MT8188_POWER_DOMAIN_VDEC1>;
1066 clocks = <&vdecsys CLK_VDEC2_LARB1>;
1067 clock-names = "ss-vdec";
1068 mediatek,infracfg = <&infracfg_ao>;
1069 #power-domain-cells = <0>;
1070 };
1071
1072 power-domain@MT8188_POWER_DOMAIN_VDEC0 {
1073 reg = <MT8188_POWER_DOMAIN_VDEC0>;
1074 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
1075 clock-names = "ss-vdec";
1076 mediatek,infracfg = <&infracfg_ao>;
1077 #power-domain-cells = <0>;
1078 };
1079
1080 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
1081 reg = <MT8188_POWER_DOMAIN_CAM_VCORE>;
1082 clocks = <&topckgen CLK_TOP_CAM>,
1083 <&topckgen CLK_TOP_CCU>,
1084 <&topckgen CLK_TOP_CCU_AHB>,
1085 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>;
1086 clock-names = "cam", "ccu", "bus", "cfgck";
1087 mediatek,infracfg = <&infracfg_ao>;
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 #power-domain-cells = <1>;
1091
1092 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
1093 reg = <MT8188_POWER_DOMAIN_CAM_MAIN>;
1094 clocks = <&camsys CLK_CAM_MAIN_LARB13>,
1095 <&camsys CLK_CAM_MAIN_LARB14>,
1096 <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
1097 <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
1098 <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>;
1099 clock-names= "ss-cam-l13", "ss-cam-l14",
1100 "ss-cam-mm0", "ss-cam-mm1",
1101 "ss-camsys";
1102 mediatek,infracfg = <&infracfg_ao>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 #power-domain-cells = <1>;
1106
1107 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
1108 reg = <MT8188_POWER_DOMAIN_CAM_SUBB>;
1109 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>,
1110 <&camsys_rawb CLK_CAM_RAWB_LARBX>,
1111 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
1112 clock-names = "ss-camb-sub",
1113 "ss-camb-raw",
1114 "ss-camb-yuv";
1115 #power-domain-cells = <0>;
1116 };
1117
1118 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
1119 reg =<MT8188_POWER_DOMAIN_CAM_SUBA>;
1120 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>,
1121 <&camsys_rawa CLK_CAM_RAWA_LARBX>,
1122 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
1123 clock-names = "ss-cama-sub",
1124 "ss-cama-raw",
1125 "ss-cama-yuv";
1126 #power-domain-cells = <0>;
1127 };
1128 };
1129 };
1130
1131 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
1132 reg = <MT8188_POWER_DOMAIN_VDOSYS1>;
1133 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>,
1134 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>,
1135 <&vdosys1 CLK_VDO1_SMI_LARB2>,
1136 <&vdosys1 CLK_VDO1_SMI_LARB3>,
1137 <&vdosys1 CLK_VDO1_GALS>;
1138 clock-names = "cfgck", "cfgxo", "ss-larb2",
1139 "ss-larb3", "ss-gals";
1140 mediatek,infracfg = <&infracfg_ao>;
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 #power-domain-cells = <1>;
1144
1145 power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
1146 reg = <MT8188_POWER_DOMAIN_HDMI_TX>;
1147 clocks = <&topckgen CLK_TOP_HDMI_APB>,
1148 <&topckgen CLK_TOP_HDCP_24M>;
1149 clock-names = "bus", "hdcp";
1150 mediatek,infracfg = <&infracfg_ao>;
1151 #power-domain-cells = <0>;
1152 };
1153
1154 power-domain@MT8188_POWER_DOMAIN_DP_TX {
1155 reg = <MT8188_POWER_DOMAIN_DP_TX>;
1156 mediatek,infracfg = <&infracfg_ao>;
1157 #power-domain-cells = <0>;
1158 };
1159
1160 power-domain@MT8188_POWER_DOMAIN_EDP_TX {
1161 reg = <MT8188_POWER_DOMAIN_EDP_TX>;
1162 mediatek,infracfg = <&infracfg_ao>;
1163 #power-domain-cells = <0>;
1164 };
1165 };
1166
1167 power-domain@MT8188_POWER_DOMAIN_VENC {
1168 reg = <MT8188_POWER_DOMAIN_VENC>;
1169 clocks = <&vencsys CLK_VENC1_LARB>,
1170 <&vencsys CLK_VENC1_VENC>,
1171 <&vencsys CLK_VENC1_GALS>,
1172 <&vencsys CLK_VENC1_GALS_SRAM>;
1173 clock-names = "ss-ve1-larb", "ss-ve1-core",
1174 "ss-ve1-gals", "ss-ve1-sram";
1175 mediatek,infracfg = <&infracfg_ao>;
1176 #power-domain-cells = <0>;
1177 };
1178
1179 power-domain@MT8188_POWER_DOMAIN_WPE {
1180 reg = <MT8188_POWER_DOMAIN_WPE>;
1181 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
1182 <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>;
1183 clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
1184 mediatek,infracfg = <&infracfg_ao>;
1185 #power-domain-cells = <0>;
1186 };
1187 };
1188 };
1189
1190 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
1191 reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
1192 mediatek,infracfg = <&infracfg_ao>;
1193 clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
1194 clock-names = "ss-pextp-fmem";
1195 #power-domain-cells = <0>;
1196 };
1197
1198 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
1199 reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>;
1200 clocks = <&topckgen CLK_TOP_SENINF>,
1201 <&topckgen CLK_TOP_SENINF1>;
1202 clock-names = "seninf0", "seninf1";
1203 #power-domain-cells = <0>;
1204 };
1205
1206 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
1207 reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
1208 #power-domain-cells = <0>;
1209 };
1210
1211 power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
1212 reg = <MT8188_POWER_DOMAIN_ADSP_AO>;
1213 clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1214 <&topckgen CLK_TOP_ADSP>;
1215 clock-names = "bus", "main";
1216 mediatek,infracfg = <&infracfg_ao>;
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219 #power-domain-cells = <1>;
1220
1221 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
1222 reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>;
1223 mediatek,infracfg = <&infracfg_ao>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 #power-domain-cells = <1>;
1227
1228 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
1229 reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>;
1230 clocks = <&topckgen CLK_TOP_ASM_H>;
1231 clock-names = "asm";
1232 mediatek,infracfg = <&infracfg_ao>;
1233 #power-domain-cells = <0>;
1234 };
1235
1236 power-domain@MT8188_POWER_DOMAIN_AUDIO {
1237 reg = <MT8188_POWER_DOMAIN_AUDIO>;
1238 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
1239 <&topckgen CLK_TOP_AUD_INTBUS>,
1240 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>;
1241 clock-names = "a1sys", "intbus", "adspck";
1242 mediatek,infracfg = <&infracfg_ao>;
1243 #power-domain-cells = <0>;
1244 };
1245
1246 power-domain@MT8188_POWER_DOMAIN_ADSP {
1247 reg = <MT8188_POWER_DOMAIN_ADSP>;
1248 mediatek,infracfg = <&infracfg_ao>;
1249 #power-domain-cells = <0>;
1250 };
1251 };
1252 };
1253
1254 power-domain@MT8188_POWER_DOMAIN_ETHER {
1255 reg = <MT8188_POWER_DOMAIN_ETHER>;
1256 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1257 clock-names = "ethermac";
1258 mediatek,infracfg = <&infracfg_ao>;
1259 #power-domain-cells = <0>;
1260 };
1261 };
1262 };
1263
1264 watchdog: watchdog@10007000 {
1265 compatible = "mediatek,mt8188-wdt";
1266 reg = <0 0x10007000 0 0x100>;
1267 mediatek,disable-extrst;
1268 #reset-cells = <1>;
1269 };
1270
1271 apmixedsys: syscon@1000c000 {
1272 compatible = "mediatek,mt8188-apmixedsys", "syscon";
1273 reg = <0 0x1000c000 0 0x1000>;
1274 #clock-cells = <1>;
1275 };
1276
1277 systimer: timer@10017000 {
1278 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
1279 reg = <0 0x10017000 0 0x1000>;
1280 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
1281 clocks = <&clk13m>;
1282 };
1283
1284 pwrap: pwrap@10024000 {
1285 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
1286 reg = <0 0x10024000 0 0x1000>;
1287 reg-names = "pwrap";
1288 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
1289 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1290 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
1291 clock-names = "spi", "wrap";
1292 };
1293
1294 gce0: mailbox@10320000 {
1295 compatible = "mediatek,mt8188-gce";
1296 reg = <0 0x10320000 0 0x4000>;
1297 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
1298 #mbox-cells = <2>;
1299 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
1300 };
1301
1302 gce1: mailbox@10330000 {
1303 compatible = "mediatek,mt8188-gce";
1304 reg = <0 0x10330000 0 0x4000>;
1305 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
1306 #mbox-cells = <2>;
1307 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
1308 };
1309
1310 scp: scp@10500000 {
1311 compatible = "mediatek,mt8188-scp";
1312 reg = <0 0x10500000 0 0x100000>,
1313 <0 0x10720000 0 0xe0000>;
1314 reg-names = "sram", "cfg";
1315 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
1316 };
1317
1318 adsp_audio26m: clock-controller@10b91100 {
1319 compatible = "mediatek,mt8188-adsp-audio26m";
1320 reg = <0 0x10b91100 0 0x100>;
1321 #clock-cells = <1>;
1322 };
1323
1324 uart0: serial@11001100 {
1325 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1326 reg = <0 0x11001100 0 0x100>;
1327 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1328 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1329 clock-names = "baud", "bus";
1330 status = "disabled";
1331 };
1332
1333 uart1: serial@11001200 {
1334 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1335 reg = <0 0x11001200 0 0x100>;
1336 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1337 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1338 clock-names = "baud", "bus";
1339 status = "disabled";
1340 };
1341
1342 uart2: serial@11001300 {
1343 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1344 reg = <0 0x11001300 0 0x100>;
1345 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1346 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1347 clock-names = "baud", "bus";
1348 status = "disabled";
1349 };
1350
1351 uart3: serial@11001400 {
1352 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1353 reg = <0 0x11001400 0 0x100>;
1354 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1355 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1356 clock-names = "baud", "bus";
1357 status = "disabled";
1358 };
1359
1360 auxadc: adc@11002000 {
1361 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
1362 reg = <0 0x11002000 0 0x1000>;
1363 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1364 clock-names = "main";
1365 #io-channel-cells = <1>;
1366 status = "disabled";
1367 };
1368
1369 pericfg_ao: syscon@11003000 {
1370 compatible = "mediatek,mt8188-pericfg-ao", "syscon";
1371 reg = <0 0x11003000 0 0x1000>;
1372 #clock-cells = <1>;
1373 };
1374
1375 spi0: spi@1100a000 {
1376 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1379 reg = <0 0x1100a000 0 0x1000>;
1380 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1381 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1382 <&topckgen CLK_TOP_SPI>,
1383 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1384 clock-names = "parent-clk", "sel-clk", "spi-clk";
1385 status = "disabled";
1386 };
1387
1388 lvts_ap: thermal-sensor@1100b000 {
1389 compatible = "mediatek,mt8188-lvts-ap";
1390 reg = <0 0x1100b000 0 0xc00>;
1391 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>;
1392 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1393 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>;
1394 nvmem-cells = <&lvts_efuse_data1>;
1395 nvmem-cell-names = "lvts-calib-data-1";
1396 #thermal-sensor-cells = <1>;
1397 };
1398
1399 spi1: spi@11010000 {
1400 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1403 reg = <0 0x11010000 0 0x1000>;
1404 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1405 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1406 <&topckgen CLK_TOP_SPI>,
1407 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1408 clock-names = "parent-clk", "sel-clk", "spi-clk";
1409 status = "disabled";
1410 };
1411
1412 spi2: spi@11012000 {
1413 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1416 reg = <0 0x11012000 0 0x1000>;
1417 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1418 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1419 <&topckgen CLK_TOP_SPI>,
1420 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1421 clock-names = "parent-clk", "sel-clk", "spi-clk";
1422 status = "disabled";
1423 };
1424
1425 spi3: spi@11013000 {
1426 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1427 #address-cells = <1>;
1428 #size-cells = <0>;
1429 reg = <0 0x11013000 0 0x1000>;
1430 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1431 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1432 <&topckgen CLK_TOP_SPI>,
1433 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1434 clock-names = "parent-clk", "sel-clk", "spi-clk";
1435 status = "disabled";
1436 };
1437
1438 spi4: spi@11018000 {
1439 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1442 reg = <0 0x11018000 0 0x1000>;
1443 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1444 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1445 <&topckgen CLK_TOP_SPI>,
1446 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1447 clock-names = "parent-clk", "sel-clk", "spi-clk";
1448 status = "disabled";
1449 };
1450
1451 spi5: spi@11019000 {
1452 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1455 reg = <0 0x11019000 0 0x1000>;
1456 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1457 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1458 <&topckgen CLK_TOP_SPI>,
1459 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1460 clock-names = "parent-clk", "sel-clk", "spi-clk";
1461 status = "disabled";
1462 };
1463
1464 xhci1: usb@11200000 {
1465 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1466 reg = <0 0x11200000 0 0x1000>,
1467 <0 0x11203e00 0 0x0100>;
1468 reg-names = "mac", "ippc";
1469 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1470 phys = <&u2port1 PHY_TYPE_USB2>,
1471 <&u3port1 PHY_TYPE_USB3>;
1472 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1473 <&topckgen CLK_TOP_SSUSB_XHCI>;
1474 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1475 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1476 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
1477 <&topckgen CLK_TOP_SSUSB_TOP_REF>,
1478 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
1479 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1480 mediatek,syscon-wakeup = <&pericfg 0x468 2>;
1481 wakeup-source;
1482 status = "disabled";
1483 };
1484
1485 mmc0: mmc@11230000 {
1486 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1487 reg = <0 0x11230000 0 0x10000>,
1488 <0 0x11f50000 0 0x1000>;
1489 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1490 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1491 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1492 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
1493 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>;
1494 clock-names = "source", "hclk", "source_cg", "crypto_clk";
1495 status = "disabled";
1496 };
1497
1498 mmc1: mmc@11240000 {
1499 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1500 reg = <0 0x11240000 0 0x1000>,
1501 <0 0x11eb0000 0 0x1000>;
1502 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1503 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1504 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1505 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1506 clock-names = "source", "hclk", "source_cg";
1507 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1508 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1509 status = "disabled";
1510 };
1511
1512 lvts_mcu: thermal-sensor@11278000 {
1513 compatible = "mediatek,mt8188-lvts-mcu";
1514 reg = <0 0x11278000 0 0x1000>;
1515 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
1516 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1517 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>;
1518 nvmem-cells = <&lvts_efuse_data1>;
1519 nvmem-cell-names = "lvts-calib-data-1";
1520 #thermal-sensor-cells = <1>;
1521 };
1522
1523 i2c0: i2c@11280000 {
1524 compatible = "mediatek,mt8188-i2c";
1525 reg = <0 0x11280000 0 0x1000>,
1526 <0 0x10220080 0 0x80>;
1527 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>;
1528 clock-div = <1>;
1529 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>,
1530 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1531 clock-names = "main", "dma";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1534 status = "disabled";
1535 };
1536
1537 i2c2: i2c@11281000 {
1538 compatible = "mediatek,mt8188-i2c";
1539 reg = <0 0x11281000 0 0x1000>,
1540 <0 0x10220180 0 0x80>;
1541 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
1542 clock-div = <1>;
1543 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>,
1544 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1545 clock-names = "main", "dma";
1546 #address-cells = <1>;
1547 #size-cells = <0>;
1548 status = "disabled";
1549 };
1550
1551 i2c3: i2c@11282000 {
1552 compatible = "mediatek,mt8188-i2c";
1553 reg = <0 0x11282000 0 0x1000>,
1554 <0 0x10220280 0 0x80>;
1555 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1556 clock-div = <1>;
1557 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>,
1558 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1559 clock-names = "main", "dma";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1562 status = "disabled";
1563 };
1564
1565 imp_iic_wrap_c: clock-controller@11283000 {
1566 compatible = "mediatek,mt8188-imp-iic-wrap-c";
1567 reg = <0 0x11283000 0 0x1000>;
1568 #clock-cells = <1>;
1569 };
1570
1571 xhci2: usb@112a0000 {
1572 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1573 reg = <0 0x112a0000 0 0x1000>,
1574 <0 0x112a3e00 0 0x0100>;
1575 reg-names = "mac", "ippc";
1576 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1577 phys = <&u2port2 PHY_TYPE_USB2>;
1578 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
1579 <&topckgen CLK_TOP_USB_TOP_3P>;
1580 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1581 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1582 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1583 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
1584 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1585 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1586 status = "disabled";
1587 };
1588
1589 xhci0: usb@112b0000 {
1590 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1591 reg = <0 0x112b0000 0 0x1000>,
1592 <0 0x112b3e00 0 0x0100>;
1593 reg-names = "mac", "ippc";
1594 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1595 phys = <&u2port0 PHY_TYPE_USB2>;
1596 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
1597 <&topckgen CLK_TOP_USB_TOP_2P>;
1598 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1599 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1600 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1601 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
1602 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1603 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1604 mediatek,syscon-wakeup = <&pericfg 0x460 2>;
1605 wakeup-source;
1606 status = "disabled";
1607 };
1608
1609 nor_flash: spi@1132c000 {
1610 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
1611 reg = <0 0x1132c000 0 0x1000>;
1612 clocks = <&topckgen CLK_TOP_SPINOR>,
1613 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>,
1614 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1615 clock-names = "spi", "sf", "axi";
1616 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1617 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1618 status = "disabled";
1619 };
1620
1621 i2c1: i2c@11e00000 {
1622 compatible = "mediatek,mt8188-i2c";
1623 reg = <0 0x11e00000 0 0x1000>,
1624 <0 0x10220100 0 0x80>;
1625 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1626 clock-div = <1>;
1627 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>,
1628 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1629 clock-names = "main", "dma";
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1632 status = "disabled";
1633 };
1634
1635 i2c4: i2c@11e01000 {
1636 compatible = "mediatek,mt8188-i2c";
1637 reg = <0 0x11e01000 0 0x1000>,
1638 <0 0x10220380 0 0x80>;
1639 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>;
1640 clock-div = <1>;
1641 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>,
1642 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1643 clock-names = "main", "dma";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1646 status = "disabled";
1647 };
1648
1649 imp_iic_wrap_w: clock-controller@11e02000 {
1650 compatible = "mediatek,mt8188-imp-iic-wrap-w";
1651 reg = <0 0x11e02000 0 0x1000>;
1652 #clock-cells = <1>;
1653 };
1654
1655 u3phy0: t-phy@11e30000 {
1656 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1657 #address-cells = <1>;
1658 #size-cells = <1>;
1659 ranges = <0x0 0x0 0x11e30000 0x1000>;
1660 status = "disabled";
1661
1662 u2port0: usb-phy@0 {
1663 reg = <0x0 0x700>;
1664 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>,
1665 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
1666 clock-names = "ref", "da_ref";
1667 #phy-cells = <1>;
1668 };
1669 };
1670
1671 u3phy1: t-phy@11e40000 {
1672 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1673 #address-cells = <1>;
1674 #size-cells = <1>;
1675 ranges = <0x0 0x0 0x11e40000 0x1000>;
1676 status = "disabled";
1677
1678 u2port1: usb-phy@0 {
1679 reg = <0x0 0x700>;
1680 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1681 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
1682 clock-names = "ref", "da_ref";
1683 #phy-cells = <1>;
1684 };
1685
1686 u3port1: usb-phy@700 {
1687 reg = <0x700 0x700>;
1688 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>,
1689 <&clk26m>;
1690 clock-names = "ref", "da_ref";
1691 #phy-cells = <1>;
1692 status = "disabled";
1693 };
1694 };
1695
1696 u3phy2: t-phy@11e80000 {
1697 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1698 #address-cells = <1>;
1699 #size-cells = <1>;
1700 ranges = <0x0 0x0 0x11e80000 0x1000>;
1701 status = "disabled";
1702
1703 u2port2: usb-phy@0 {
1704 reg = <0x0 0x700>;
1705 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>,
1706 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
1707 clock-names = "ref", "da_ref";
1708 #phy-cells = <1>;
1709 };
1710 };
1711
1712 i2c5: i2c@11ec0000 {
1713 compatible = "mediatek,mt8188-i2c";
1714 reg = <0 0x11ec0000 0 0x1000>,
1715 <0 0x10220480 0 0x80>;
1716 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
1717 clock-div = <1>;
1718 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>,
1719 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1720 clock-names = "main", "dma";
1721 #address-cells = <1>;
1722 #size-cells = <0>;
1723 status = "disabled";
1724 };
1725
1726 i2c6: i2c@11ec1000 {
1727 compatible = "mediatek,mt8188-i2c";
1728 reg = <0 0x11ec1000 0 0x1000>,
1729 <0 0x10220600 0 0x80>;
1730 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1731 clock-div = <1>;
1732 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>,
1733 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1734 clock-names = "main", "dma";
1735 #address-cells = <1>;
1736 #size-cells = <0>;
1737 status = "disabled";
1738 };
1739
1740 imp_iic_wrap_en: clock-controller@11ec2000 {
1741 compatible = "mediatek,mt8188-imp-iic-wrap-en";
1742 reg = <0 0x11ec2000 0 0x1000>;
1743 #clock-cells = <1>;
1744 };
1745
1746 efuse: efuse@11f20000 {
1747 compatible = "mediatek,mt8188-efuse", "mediatek,efuse";
1748 reg = <0 0x11f20000 0 0x1000>;
1749 #address-cells = <1>;
1750 #size-cells = <1>;
1751
1752 lvts_efuse_data1: lvts1-calib@1ac {
1753 reg = <0x1ac 0x40>;
1754 };
1755 };
1756
1757 gpu: gpu@13000000 {
1758 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
1759 reg = <0 0x13000000 0 0x4000>;
1760
1761 clocks = <&mfgcfg CLK_MFGCFG_BG3D>;
1762 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
1763 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
1764 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
1765 interrupt-names = "job", "mmu", "gpu";
1766 operating-points-v2 = <&gpu_opp_table>;
1767 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
1768 <&spm MT8188_POWER_DOMAIN_MFG3>,
1769 <&spm MT8188_POWER_DOMAIN_MFG4>;
1770 power-domain-names = "core0", "core1", "core2";
1771 #cooling-cells = <2>;
1772 status = "disabled";
1773 };
1774
1775 mfgcfg: clock-controller@13fbf000 {
1776 compatible = "mediatek,mt8188-mfgcfg";
1777 reg = <0 0x13fbf000 0 0x1000>;
1778 #clock-cells = <1>;
1779 };
1780
1781 vppsys0: clock-controller@14000000 {
1782 compatible = "mediatek,mt8188-vppsys0";
1783 reg = <0 0x14000000 0 0x1000>;
1784 #clock-cells = <1>;
1785 };
1786
1787 wpesys: clock-controller@14e00000 {
1788 compatible = "mediatek,mt8188-wpesys";
1789 reg = <0 0x14e00000 0 0x1000>;
1790 #clock-cells = <1>;
1791 };
1792
1793 wpesys_vpp0: clock-controller@14e02000 {
1794 compatible = "mediatek,mt8188-wpesys-vpp0";
1795 reg = <0 0x14e02000 0 0x1000>;
1796 #clock-cells = <1>;
1797 };
1798
1799 vppsys1: clock-controller@14f00000 {
1800 compatible = "mediatek,mt8188-vppsys1";
1801 reg = <0 0x14f00000 0 0x1000>;
1802 #clock-cells = <1>;
1803 };
1804
1805 imgsys: clock-controller@15000000 {
1806 compatible = "mediatek,mt8188-imgsys";
1807 reg = <0 0x15000000 0 0x1000>;
1808 #clock-cells = <1>;
1809 };
1810
1811 imgsys1_dip_top: clock-controller@15110000 {
1812 compatible = "mediatek,mt8188-imgsys1-dip-top";
1813 reg = <0 0x15110000 0 0x1000>;
1814 #clock-cells = <1>;
1815 };
1816
1817 imgsys1_dip_nr: clock-controller@15130000 {
1818 compatible = "mediatek,mt8188-imgsys1-dip-nr";
1819 reg = <0 0x15130000 0 0x1000>;
1820 #clock-cells = <1>;
1821 };
1822
1823 imgsys_wpe1: clock-controller@15220000 {
1824 compatible = "mediatek,mt8188-imgsys-wpe1";
1825 reg = <0 0x15220000 0 0x1000>;
1826 #clock-cells = <1>;
1827 };
1828
1829 ipesys: clock-controller@15330000 {
1830 compatible = "mediatek,mt8188-ipesys";
1831 reg = <0 0x15330000 0 0x1000>;
1832 #clock-cells = <1>;
1833 };
1834
1835 imgsys_wpe2: clock-controller@15520000 {
1836 compatible = "mediatek,mt8188-imgsys-wpe2";
1837 reg = <0 0x15520000 0 0x1000>;
1838 #clock-cells = <1>;
1839 };
1840
1841 imgsys_wpe3: clock-controller@15620000 {
1842 compatible = "mediatek,mt8188-imgsys-wpe3";
1843 reg = <0 0x15620000 0 0x1000>;
1844 #clock-cells = <1>;
1845 };
1846
1847 camsys: clock-controller@16000000 {
1848 compatible = "mediatek,mt8188-camsys";
1849 reg = <0 0x16000000 0 0x1000>;
1850 #clock-cells = <1>;
1851 };
1852
1853 camsys_rawa: clock-controller@1604f000 {
1854 compatible = "mediatek,mt8188-camsys-rawa";
1855 reg = <0 0x1604f000 0 0x1000>;
1856 #clock-cells = <1>;
1857 };
1858
1859 camsys_yuva: clock-controller@1606f000 {
1860 compatible = "mediatek,mt8188-camsys-yuva";
1861 reg = <0 0x1606f000 0 0x1000>;
1862 #clock-cells = <1>;
1863 };
1864
1865 camsys_rawb: clock-controller@1608f000 {
1866 compatible = "mediatek,mt8188-camsys-rawb";
1867 reg = <0 0x1608f000 0 0x1000>;
1868 #clock-cells = <1>;
1869 };
1870
1871 camsys_yuvb: clock-controller@160af000 {
1872 compatible = "mediatek,mt8188-camsys-yuvb";
1873 reg = <0 0x160af000 0 0x1000>;
1874 #clock-cells = <1>;
1875 };
1876
1877 ccusys: clock-controller@17200000 {
1878 compatible = "mediatek,mt8188-ccusys";
1879 reg = <0 0x17200000 0 0x1000>;
1880 #clock-cells = <1>;
1881 };
1882
1883 vdecsys_soc: clock-controller@1800f000 {
1884 compatible = "mediatek,mt8188-vdecsys-soc";
1885 reg = <0 0x1800f000 0 0x1000>;
1886 #clock-cells = <1>;
1887 };
1888
1889 vdecsys: clock-controller@1802f000 {
1890 compatible = "mediatek,mt8188-vdecsys";
1891 reg = <0 0x1802f000 0 0x1000>;
1892 #clock-cells = <1>;
1893 };
1894
1895 vencsys: clock-controller@1a000000 {
1896 compatible = "mediatek,mt8188-vencsys";
1897 reg = <0 0x1a000000 0 0x1000>;
1898 #clock-cells = <1>;
1899 };
1900
1901 vdosys0: syscon@1c01d000 {
1902 compatible = "mediatek,mt8188-vdosys0", "syscon";
1903 reg = <0 0x1c01d000 0 0x1000>;
1904 #clock-cells = <1>;
1905 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
1906 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
1907 };
1908
1909 vdosys1: syscon@1c100000 {
1910 compatible = "mediatek,mt8188-vdosys1", "syscon";
1911 reg = <0 0x1c100000 0 0x1000>;
1912 #clock-cells = <1>;
1913 #reset-cells = <1>;
1914 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
1915 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
1916 };
1917 };
1918 };
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