1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 Radxa Limited
4 * Copyright (C) 2024 Collabora Ltd.
5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6 */
7
8 #include "mt8195.dtsi"
9 #include "mt6359.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
13 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
14 #include <dt-bindings/spmi/spmi.h>
15 #include <dt-bindings/usb/pd.h>
16
17 / {
18 model = "Radxa NIO 12L";
19 chassis-type = "embedded";
20 compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195";
21
22 aliases {
23 i2c0 = &i2c2;
24 i2c1 = &i2c3;
25 i2c2 = &i2c4;
26 i2c3 = &i2c0;
27 i2c4 = &i2c1;
28 ethernet0 = ð
29 serial0 = &uart0;
30 serial1 = &uart1;
31 spi0 = &spi1;
32 spi1 = &spi2;
33 };
34
35 chosen {
36 stdout-path = "serial0:921600n8";
37 };
38
39 firmware {
40 optee {
41 compatible = "linaro,optee-tz";
42 method = "smc";
43 };
44 };
45
46 memory@40000000 {
47 device_type = "memory";
48 reg = <0 0x40000000 0x1 0x0>;
49 };
50
51 wifi_vreg: regulator-wifi-3v3-en {
52 compatible = "regulator-fixed";
53 regulator-name = "wifi_3v3_en";
54 regulator-always-on;
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 enable-active-high;
58 gpio = <&pio 67 GPIO_ACTIVE_HIGH>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&wifi_vreg_pins>;
61 vin-supply = <&vsys>;
62 };
63
64 /* system wide switching 5.0V power rail */
65 vsys: regulator-vsys {
66 compatible = "regulator-fixed";
67 regulator-name = "vsys";
68 regulator-always-on;
69 regulator-boot-on;
70 regulator-min-microvolt = <5000000>;
71 regulator-max-microvolt = <5000000>;
72 vin-supply = <&vcc5v0_vsys>;
73 };
74
75 vsys_buck: regulator-vsys-buck {
76 compatible = "regulator-fixed";
77 regulator-name = "vsys_buck";
78 regulator-always-on;
79 regulator-boot-on;
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 vin-supply = <&vcc5v0_vsys>;
83 };
84
85 /* Rail from power-only "TYPE C DC" port */
86 vcc5v0_vsys: regulator-vcc5v0-sys {
87 compatible = "regulator-fixed";
88 regulator-name = "vcc5v0_sys";
89 regulator-always-on;
90 regulator-boot-on;
91 };
92
93 reserved-memory {
94 #address-cells = <2>;
95 #size-cells = <2>;
96 ranges;
97
98 /*
99 * 12 MiB reserved for OP-TEE (BL32)
100 * +-----------------------+ 0x43e0_0000
101 * | SHMEM 2MiB |
102 * +-----------------------+ 0x43c0_0000
103 * | | TA_RAM 8MiB |
104 * + TZDRAM +--------------+ 0x4340_0000
105 * | | TEE_RAM 2MiB |
106 * +-----------------------+ 0x4320_0000
107 */
108 optee_reserved: optee@43200000 {
109 reg = <0 0x43200000 0 0xc00000>;
110 no-map;
111 };
112
113 scp_mem: memory@50000000 {
114 compatible = "shared-dma-pool";
115 reg = <0 0x50000000 0 0x2900000>;
116 no-map;
117 };
118
119 vpu_mem: memory@53000000 {
120 compatible = "shared-dma-pool";
121 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
122 };
123
124 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
125 bl31_secmon_mem: memory@54600000 {
126 reg = <0 0x54600000 0x0 0x200000>;
127 no-map;
128 };
129
130 afe_mem: memory@60000000 {
131 compatible = "shared-dma-pool";
132 reg = <0 0x60000000 0 0x1100000>;
133 no-map;
134 };
135
136 apu_mem: memory@62000000 {
137 compatible = "shared-dma-pool";
138 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
139 };
140 };
141 };
142
143 &cpu0 {
144 cpu-supply = <&mt6359_vcore_buck_reg>;
145 };
146
147 &cpu1 {
148 cpu-supply = <&mt6359_vcore_buck_reg>;
149 };
150
151 &cpu2 {
152 cpu-supply = <&mt6359_vcore_buck_reg>;
153 };
154
155 &cpu3 {
156 cpu-supply = <&mt6359_vcore_buck_reg>;
157 };
158
159 &cpu4 {
160 cpu-supply = <&mt6315_6_vbuck1>;
161 };
162
163 &cpu5 {
164 cpu-supply = <&mt6315_6_vbuck1>;
165 };
166
167 &cpu6 {
168 cpu-supply = <&mt6315_6_vbuck1>;
169 };
170
171 &cpu7 {
172 cpu-supply = <&mt6315_6_vbuck1>;
173 };
174
175 ð {
176 phy-mode = "rgmii-rxid";
177 phy-handle = <&rgmii_phy>;
178 pinctrl-names = "default", "sleep";
179 pinctrl-0 = <ð_default_pins>;
180 pinctrl-1 = <ð_sleep_pins>;
181 mediatek,tx-delay-ps = <2030>;
182 mediatek,mac-wol;
183 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
184 snps,reset-delays-us = <0 20000 100000>;
185 status = "okay";
186
187 mdio {
188 rgmii_phy: ethernet-phy@1 {
189 compatible = "ethernet-phy-id001c.c916";
190 reg = <0x1>;
191 };
192 };
193 };
194
195 &gpu {
196 mali-supply = <&mt6315_7_vbuck1>;
197 status = "okay";
198 };
199
200 &i2c2 {
201 clock-frequency = <400000>;
202 pinctrl-0 = <&i2c2_pins>;
203 pinctrl-names = "default";
204 status = "okay";
205
206 typec-mux@48 {
207 compatible = "ite,it5205";
208 reg = <0x48>;
209
210 mode-switch;
211 orientation-switch;
212
213 vcc-supply = <&mt6359_vibr_ldo_reg>;
214
215 port {
216 it5205_sbu_mux: endpoint {
217 remote-endpoint = <&typec_con_mux>;
218 };
219 };
220 };
221 };
222
223 &i2c4 {
224 clock-frequency = <400000>;
225 pinctrl-0 = <&i2c4_pins>;
226 pinctrl-names = "default";
227 status = "okay";
228
229 /* I2C4 exposed at 39-pins MIPI-LCD connector */
230 };
231
232 &i2c6 {
233 clock-frequency = <400000>;
234 pinctrl-0 = <&i2c6_pins>;
235 pinctrl-names = "default";
236 status = "okay";
237
238 mt6360: pmic@34 {
239 compatible = "mediatek,mt6360";
240 reg = <0x34>;
241 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
242 interrupt-names = "IRQB";
243 interrupt-controller;
244 #interrupt-cells = <1>;
245 pinctrl-0 = <&mt6360_pins>;
246
247 charger {
248 compatible = "mediatek,mt6360-chg";
249 richtek,vinovp-microvolt = <14500000>;
250
251 otg_vbus_regulator: usb-otg-vbus-regulator {
252 regulator-name = "usb-otg-vbus";
253 regulator-min-microvolt = <4425000>;
254 regulator-max-microvolt = <5825000>;
255 };
256 };
257
258 regulator {
259 compatible = "mediatek,mt6360-regulator";
260 LDO_VIN1-supply = <&vsys_buck>;
261 LDO_VIN3-supply = <&mt6360_buck2>;
262
263 mt6360_buck1: buck1 {
264 regulator-name = "emi_vdd2";
265 regulator-min-microvolt = <300000>;
266 regulator-max-microvolt = <1300000>;
267 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
268 MT6360_OPMODE_LP
269 MT6360_OPMODE_ULP>;
270 regulator-always-on;
271 };
272
273 mt6360_buck2: buck2 {
274 regulator-name = "emi_vddq";
275 regulator-min-microvolt = <300000>;
276 regulator-max-microvolt = <1300000>;
277 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
278 MT6360_OPMODE_LP
279 MT6360_OPMODE_ULP>;
280 regulator-always-on;
281 };
282
283 mt6360_ldo1: ldo1 {
284 regulator-name = "ext_lcd_3v3";
285 regulator-min-microvolt = <3300000>;
286 regulator-max-microvolt = <3300000>;
287 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
288 MT6360_OPMODE_LP>;
289 regulator-always-on;
290 };
291
292 mt6360_ldo2: ldo2 {
293 regulator-name = "panel1_p1v8";
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <1800000>;
296 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
297 MT6360_OPMODE_LP>;
298 };
299
300 mt6360_ldo3: ldo3 {
301 regulator-name = "vmc_pmu";
302 regulator-min-microvolt = <1200000>;
303 regulator-max-microvolt = <3600000>;
304 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
305 MT6360_OPMODE_LP>;
306 };
307
308 mt6360_ldo5: ldo5 {
309 regulator-name = "vmch_pmu";
310 regulator-min-microvolt = <3300000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
313 MT6360_OPMODE_LP>;
314 regulator-always-on;
315 };
316
317 mt6360_ldo6: ldo6 {
318 regulator-name = "mt6360_ldo6"; /* Test point */
319 regulator-min-microvolt = <500000>;
320 regulator-max-microvolt = <2100000>;
321 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
322 MT6360_OPMODE_LP>;
323 };
324
325 mt6360_ldo7: ldo7 {
326 regulator-name = "emi_vmddr_en";
327 regulator-min-microvolt = <500000>;
328 regulator-max-microvolt = <2100000>;
329 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
330 MT6360_OPMODE_LP>;
331 regulator-always-on;
332 };
333 };
334
335 typec {
336 compatible = "mediatek,mt6360-tcpc";
337 interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>;
338 interrupt-names = "PD_IRQB";
339
340 connector {
341 compatible = "usb-c-connector";
342 label = "USB-C";
343 data-role = "dual";
344 op-sink-microwatt = <10000000>;
345 power-role = "dual";
346 try-power-role = "sink";
347
348 source-pdos = <PDO_FIXED(5000, 1000,
349 PDO_FIXED_DUAL_ROLE |
350 PDO_FIXED_DATA_SWAP)>;
351 sink-pdos = <PDO_FIXED(5000, 3000,
352 PDO_FIXED_DUAL_ROLE |
353 PDO_FIXED_DATA_SWAP)>;
354
355 ports {
356 #address-cells = <1>;
357 #size-cells = <0>;
358
359 port@0 {
360 reg = <0>;
361 typec_con_hs: endpoint {
362 remote-endpoint = <&mtu3_hs0_role_sw>;
363 };
364 };
365
366 port@2 {
367 reg = <2>;
368 typec_con_mux: endpoint {
369 remote-endpoint = <&it5205_sbu_mux>;
370 };
371 };
372 };
373 };
374 };
375 };
376 };
377
378 &mfg0 {
379 domain-supply = <&mt6315_7_vbuck1>;
380 };
381
382 &mfg1 {
383 domain-supply = <&mt6359_vsram_others_ldo_reg>;
384 };
385
386 /* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */
387 &mmc0 {
388 pinctrl-names = "default", "state_uhs";
389 pinctrl-0 = <&mmc0_default_pins>;
390 pinctrl-1 = <&mmc0_uhs_pins>;
391 bus-width = <8>;
392 max-frequency = <200000000>;
393 hs400-ds-delay = <0x14c11>;
394 cap-mmc-highspeed;
395 cap-mmc-hw-reset;
396 mmc-hs200-1_8v;
397 mmc-hs400-1_8v;
398 no-sdio;
399 no-sd;
400 non-removable;
401 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
402 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
403 status = "okay";
404 };
405
406 /* MMC1 Controller: MicroSD card slot */
407 &mmc1 {
408 pinctrl-names = "default", "state_uhs";
409 pinctrl-0 = <&mmc1_default_pins>, <&mmc1_pins_detect>;
410 pinctrl-1 = <&mmc1_default_pins>;
411 bus-width = <4>;
412 max-frequency = <200000000>;
413 cap-sd-highspeed;
414 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
415 no-mmc;
416 no-sdio;
417 sd-uhs-sdr50;
418 sd-uhs-sdr104;
419 vmmc-supply = <&mt6360_ldo5>;
420 vqmmc-supply = <&mt6360_ldo3>;
421 status = "okay";
422 };
423
424 &mt6359_vaud18_ldo_reg {
425 regulator-always-on;
426 };
427
428 &mt6359_vbbck_ldo_reg {
429 regulator-always-on;
430 };
431
432 /* For USB Hub */
433 &mt6359_vcamio_ldo_reg {
434 regulator-always-on;
435 };
436
437 &mt6359_vcn33_2_bt_ldo_reg {
438 regulator-min-microvolt = <3300000>;
439 regulator-max-microvolt = <3300000>;
440 };
441
442 &mt6359_vcore_buck_reg {
443 regulator-always-on;
444 };
445
446 &mt6359_vgpu11_buck_reg {
447 regulator-always-on;
448 };
449
450 &mt6359_vproc1_buck_reg {
451 regulator-always-on;
452 };
453
454 &mt6359_vproc2_buck_reg {
455 regulator-always-on;
456 };
457
458 &mt6359_vpu_buck_reg {
459 regulator-always-on;
460 };
461
462 &mt6359_vrf12_ldo_reg {
463 regulator-always-on;
464 };
465
466 &mt6359_vsram_md_ldo_reg {
467 regulator-always-on;
468 };
469
470 /* for GPU SRAM */
471 &mt6359_vsram_others_ldo_reg {
472 regulator-min-microvolt = <750000>;
473 regulator-max-microvolt = <750000>;
474 };
475
476 &pio {
477 mediatek,rsel-resistance-in-si-unit;
478
479 eth_default_pins: eth-default-pins {
480 pins-cc {
481 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
482 <PINMUX_GPIO86__FUNC_GBE_RXC>,
483 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
484 <PINMUX_GPIO88__FUNC_GBE_TXEN>;
485 drive-strength = <8>;
486 };
487
488 pins-mdio {
489 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
490 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
491 input-enable;
492 };
493
494 pins-power {
495 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
496 <PINMUX_GPIO92__FUNC_GPIO92>;
497 output-high;
498 };
499
500 pins-rst {
501 pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
502 };
503
504 pins-rxd {
505 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
506 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
507 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
508 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
509 };
510
511 pins-txd {
512 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
513 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
514 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
515 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
516 drive-strength = <8>;
517 };
518 };
519
520 eth_sleep_pins: eth-sleep-pins {
521 pins-cc {
522 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
523 <PINMUX_GPIO86__FUNC_GPIO86>,
524 <PINMUX_GPIO87__FUNC_GPIO87>,
525 <PINMUX_GPIO88__FUNC_GPIO88>;
526 };
527
528 pins-mdio {
529 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
530 <PINMUX_GPIO90__FUNC_GPIO90>;
531 bias-disable;
532 input-disable;
533 };
534
535 pins-rxd {
536 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
537 <PINMUX_GPIO82__FUNC_GPIO82>,
538 <PINMUX_GPIO83__FUNC_GPIO83>,
539 <PINMUX_GPIO84__FUNC_GPIO84>;
540 };
541
542 pins-txd {
543 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
544 <PINMUX_GPIO78__FUNC_GPIO78>,
545 <PINMUX_GPIO79__FUNC_GPIO79>,
546 <PINMUX_GPIO80__FUNC_GPIO80>;
547 };
548 };
549
550 i2c2_pins: i2c2-pins {
551 pins-bus {
552 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
553 <PINMUX_GPIO13__FUNC_SCL2>;
554 bias-pull-up = <1000>;
555 drive-strength = <6>;
556 drive-strength-microamp = <1000>;
557 };
558 };
559
560 i2c4_pins: i2c4-pins {
561 pins-bus {
562 pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
563 <PINMUX_GPIO17__FUNC_SCL4>;
564 bias-pull-up = <1000>;
565 drive-strength-microamp = <1000>;
566 };
567 };
568
569 i2c6_pins: i2c6-pins {
570 pins {
571 pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
572 <PINMUX_GPIO26__FUNC_SCL6>;
573 bias-disable;
574 };
575 };
576
577 mmc0_default_pins: mmc0-default-pins {
578 pins-clk {
579 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
580 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
581 drive-strength = <6>;
582 };
583
584 pins-cmd-dat {
585 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
586 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
587 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
588 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
589 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
590 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
591 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
592 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
593 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
594 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
595 drive-strength = <6>;
596 input-enable;
597 };
598
599 pins-rst {
600 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
601 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
602 drive-strength = <6>;
603 };
604 };
605
606 mmc0_uhs_pins: mmc0-uhs-pins {
607 pins-clk {
608 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
609 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
610 drive-strength = <8>;
611 };
612
613 pins-cmd-dat {
614 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
615 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
616 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
617 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
618 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
619 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
620 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
621 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
622 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
623 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
624 drive-strength = <8>;
625 input-enable;
626 };
627
628 pins-ds {
629 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
630 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
631 drive-strength = <8>;
632 };
633
634 pins-rst {
635 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
636 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
637 drive-strength = <8>;
638 };
639 };
640
641 mmc1_default_pins: mmc1-default-pins {
642 pins-clk {
643 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
644 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
645 drive-strength = <8>;
646 };
647
648 pins-cmd-dat {
649 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
650 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
651 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
652 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
653 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
654 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
655 drive-strength = <8>;
656 input-enable;
657 };
658 };
659
660 mmc1_pins_detect: mmc1-detect-pins {
661 pins-insert {
662 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
663 bias-pull-up;
664 };
665 };
666
667 mt6360_pins: mt6360-pins {
668 pins-irq {
669 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>,
670 <PINMUX_GPIO101__FUNC_GPIO101>;
671 input-enable;
672 bias-pull-up;
673 };
674 };
675
676 pcie0_default_pins: pcie0-default-pins {
677 pins-bus {
678 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
679 <PINMUX_GPIO20__FUNC_PERSTN>,
680 <PINMUX_GPIO21__FUNC_CLKREQN>;
681 bias-pull-up;
682 };
683 };
684
685 pcie1_default_pins: pcie1-default-pins {
686 pins-bus {
687 pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>,
688 <PINMUX_GPIO1__FUNC_CLKREQN_1>,
689 <PINMUX_GPIO2__FUNC_WAKEN_1>;
690 bias-disable;
691 };
692 };
693
694 spi1_pins: spi1-default-pins {
695 pins-bus {
696 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
697 <PINMUX_GPIO137__FUNC_SPIM1_CLK>,
698 <PINMUX_GPIO138__FUNC_SPIM1_MO>,
699 <PINMUX_GPIO139__FUNC_SPIM1_MI>;
700 bias-disable;
701 };
702 };
703
704 spi2_pins: spi2-default-pins {
705 pins-bus {
706 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
707 <PINMUX_GPIO141__FUNC_SPIM2_CLK>,
708 <PINMUX_GPIO142__FUNC_SPIM2_MO>,
709 <PINMUX_GPIO143__FUNC_SPIM2_MI>;
710 bias-disable;
711 };
712 };
713
714 uart0_pins: uart0-pins {
715 pins-bus {
716 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
717 <PINMUX_GPIO99__FUNC_URXD0>;
718 };
719 };
720
721 uart1_pins: uart1-pins {
722 pins-bus {
723 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
724 <PINMUX_GPIO103__FUNC_URXD1>;
725 };
726 };
727
728 usb3_port0_pins: usb3p0-default-pins {
729 pins-vbus {
730 pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
731 input-enable;
732 };
733 };
734
735 usb2_port0_pins: usb2p0-default-pins {
736 pins-iddig {
737 pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>;
738 input-enable;
739 bias-pull-up;
740 };
741
742 pins-vbus {
743 pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>;
744 output-low;
745 };
746 };
747
748 wifi_vreg_pins: wifi-vreg-pins {
749 pins-wifi-pmu-en {
750 pinmux = <PINMUX_GPIO65__FUNC_GPIO65>;
751 output-high;
752 };
753
754 pins-wifi-vreg-en {
755 pinmux = <PINMUX_GPIO67__FUNC_GPIO67>;
756 };
757 };
758 };
759
760 &pcie0 {
761 pinctrl-names = "default";
762 pinctrl-0 = <&pcie0_default_pins>;
763 status = "okay";
764 };
765
766 &pcie1 {
767 pinctrl-names = "default";
768 pinctrl-0 = <&pcie1_default_pins>;
769 status = "okay";
770 };
771
772 &pciephy {
773 status = "okay";
774 };
775
776 &pmic {
777 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
778 };
779
780 &scp {
781 memory-region = <&scp_mem>;
782 status = "okay";
783 };
784
785 &spi1 {
786 /* Exposed at 40 pin connector */
787 pinctrl-0 = <&spi1_pins>;
788 pinctrl-names = "default";
789 mediatek,pad-select = <0>;
790 #address-cells = <1>;
791 #size-cells = <0>;
792 status = "okay";
793 };
794
795 &spi2 {
796 /* Exposed at 40 pin connector */
797 pinctrl-0 = <&spi2_pins>;
798 pinctrl-names = "default";
799 mediatek,pad-select = <0>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 status = "okay";
803 };
804
805 &spmi {
806 #address-cells = <2>;
807 #size-cells = <0>;
808
809 mt6315_6: pmic@6 {
810 compatible = "mediatek,mt6315-regulator";
811 reg = <0x6 SPMI_USID>;
812
813 regulators {
814 mt6315_6_vbuck1: vbuck1 {
815 regulator-compatible = "vbuck1";
816 regulator-name = "Vbcpu";
817 regulator-min-microvolt = <300000>;
818 regulator-max-microvolt = <1193750>;
819 regulator-enable-ramp-delay = <256>;
820 regulator-allowed-modes = <0 1 2>;
821 regulator-always-on;
822 };
823 };
824 };
825
826 mt6315_7: pmic@7 {
827 compatible = "mediatek,mt6315-regulator";
828 reg = <0x7 SPMI_USID>;
829
830 regulators {
831 mt6315_7_vbuck1: vbuck1 {
832 regulator-compatible = "vbuck1";
833 regulator-name = "Vgpu";
834 regulator-min-microvolt = <300000>;
835 regulator-max-microvolt = <1193750>;
836 regulator-enable-ramp-delay = <256>;
837 regulator-allowed-modes = <0 1 2>;
838 };
839 };
840 };
841 };
842
843 &u3phy0 {
844 status = "okay";
845 };
846
847 &u3phy1 {
848 status = "okay";
849 };
850
851 &u3phy2 {
852 status = "okay";
853 };
854
855 &uart0 {
856 /* Exposed at 40 pin connector */
857 pinctrl-0 = <&uart0_pins>;
858 pinctrl-names = "default";
859 status = "okay";
860 };
861
862 &uart1 {
863 /* Exposed at 40 pin connector */
864 pinctrl-0 = <&uart1_pins>;
865 pinctrl-names = "default";
866 status = "okay";
867 };
868
869 &ssusb0 {
870 pinctrl-names = "default";
871 pinctrl-0 = <&usb3_port0_pins>;
872 role-switch-default-mode = "host";
873 usb-role-switch;
874 vusb33-supply = <&mt6359_vusb_ldo_reg>;
875 status = "okay";
876
877 port {
878 mtu3_hs0_role_sw: endpoint {
879 remote-endpoint = <&typec_con_hs>;
880 };
881 };
882 };
883
884 &ssusb2 {
885 pinctrl-names = "default";
886 pinctrl-0 = <&usb2_port0_pins>;
887 vusb33-supply = <&mt6359_vusb_ldo_reg>;
888 status = "okay";
889 };
890
891 &xhci0 {
892 vbus-supply = <&otg_vbus_regulator>;
893 status = "okay";
894 };
895
896 &xhci1 {
897 phys = <&u2port1 PHY_TYPE_USB2>;
898 /* MT7921's USB Bluetooth has issues with USB2 LPM */
899 usb2-lpm-disable;
900 vusb33-supply = <&mt6359_vusb_ldo_reg>;
901 vbus-supply = <&vsys>;
902 mediatek,u3p-dis-msk = <1>;
903 status = "okay";
904 };
905
906 &xhci2 {
907 vbus-supply = <&vsys>;
908 status = "okay";
909 };
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