1 // SPDX-License-Identifier: GPL-2.0
2
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
12
13 / {
14 compatible = "nvidia,tegra234";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 bus@0 {
20 compatible = "simple-bus";
21
22 #address-cells = <2>;
23 #size-cells = <2>;
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
25
26 misc@100000 {
27 compatible = "nvidia,tegra234-misc";
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
30 status = "okay";
31 };
32
33 timer@2080000 {
34 compatible = "nvidia,tegra234-timer";
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
52 status = "okay";
53 };
54
55 gpio: gpio@2200000 {
56 compatible = "nvidia,tegra234-gpio";
57 reg-names = "security", "gpio";
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
60 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 #gpio-cells = <2>;
111 gpio-controller;
112 gpio-ranges = <&pinmux 0 0 164>;
113 };
114
115 pinmux: pinmux@2430000 {
116 compatible = "nvidia,tegra234-pinmux";
117 reg = <0x0 0x2430000 0x0 0x19100>;
118 };
119
120 gpcdma: dma-controller@2600000 {
121 compatible = "nvidia,tegra234-gpcdma",
122 "nvidia,tegra186-gpcdma";
123 reg = <0x0 0x2600000 0x0 0x210000>;
124 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
125 reset-names = "gpcdma";
126 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
158 #dma-cells = <1>;
159 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
160 dma-channel-mask = <0xfffffffe>;
161 dma-coherent;
162 };
163
164 aconnect@2900000 {
165 compatible = "nvidia,tegra234-aconnect",
166 "nvidia,tegra210-aconnect";
167 clocks = <&bpmp TEGRA234_CLK_APE>,
168 <&bpmp TEGRA234_CLK_APB2APE>;
169 clock-names = "ape", "apb2ape";
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
171 status = "disabled";
172
173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
176
177 tegra_ahub: ahub@2900800 {
178 compatible = "nvidia,tegra234-ahub";
179 reg = <0x0 0x02900800 0x0 0x800>;
180 clocks = <&bpmp TEGRA234_CLK_AHUB>;
181 clock-names = "ahub";
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
184 assigned-clock-rates = <81600000>;
185 status = "disabled";
186
187 #address-cells = <2>;
188 #size-cells = <2>;
189 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
190
191 tegra_i2s1: i2s@2901000 {
192 compatible = "nvidia,tegra234-i2s",
193 "nvidia,tegra210-i2s";
194 reg = <0x0 0x2901000 0x0 0x100>;
195 clocks = <&bpmp TEGRA234_CLK_I2S1>,
196 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
197 clock-names = "i2s", "sync_input";
198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
200 assigned-clock-rates = <1536000>;
201 sound-name-prefix = "I2S1";
202 status = "disabled";
203
204 ports {
205 #address-cells = <1>;
206 #size-cells = <0>;
207
208 port@0 {
209 reg = <0>;
210
211 i2s1_cif: endpoint {
212 remote-endpoint = <&xbar_i2s1>;
213 };
214 };
215
216 i2s1_port: port@1 {
217 reg = <1>;
218
219 i2s1_dap: endpoint {
220 dai-format = "i2s";
221 /* placeholder for external codec */
222 };
223 };
224 };
225 };
226
227 tegra_i2s2: i2s@2901100 {
228 compatible = "nvidia,tegra234-i2s",
229 "nvidia,tegra210-i2s";
230 reg = <0x0 0x2901100 0x0 0x100>;
231 clocks = <&bpmp TEGRA234_CLK_I2S2>,
232 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
233 clock-names = "i2s", "sync_input";
234 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
235 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
236 assigned-clock-rates = <1536000>;
237 sound-name-prefix = "I2S2";
238 status = "disabled";
239
240 ports {
241 #address-cells = <1>;
242 #size-cells = <0>;
243
244 port@0 {
245 reg = <0>;
246
247 i2s2_cif: endpoint {
248 remote-endpoint = <&xbar_i2s2>;
249 };
250 };
251
252 i2s2_port: port@1 {
253 reg = <1>;
254
255 i2s2_dap: endpoint {
256 dai-format = "i2s";
257 /* placeholder for external codec */
258 };
259 };
260 };
261 };
262
263 tegra_i2s3: i2s@2901200 {
264 compatible = "nvidia,tegra234-i2s",
265 "nvidia,tegra210-i2s";
266 reg = <0x0 0x2901200 0x0 0x100>;
267 clocks = <&bpmp TEGRA234_CLK_I2S3>,
268 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
269 clock-names = "i2s", "sync_input";
270 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
271 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
272 assigned-clock-rates = <1536000>;
273 sound-name-prefix = "I2S3";
274 status = "disabled";
275
276 ports {
277 #address-cells = <1>;
278 #size-cells = <0>;
279
280 port@0 {
281 reg = <0>;
282
283 i2s3_cif: endpoint {
284 remote-endpoint = <&xbar_i2s3>;
285 };
286 };
287
288 i2s3_port: port@1 {
289 reg = <1>;
290
291 i2s3_dap: endpoint {
292 dai-format = "i2s";
293 /* placeholder for external codec */
294 };
295 };
296 };
297 };
298
299 tegra_i2s4: i2s@2901300 {
300 compatible = "nvidia,tegra234-i2s",
301 "nvidia,tegra210-i2s";
302 reg = <0x0 0x2901300 0x0 0x100>;
303 clocks = <&bpmp TEGRA234_CLK_I2S4>,
304 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
305 clock-names = "i2s", "sync_input";
306 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
307 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
308 assigned-clock-rates = <1536000>;
309 sound-name-prefix = "I2S4";
310 status = "disabled";
311
312 ports {
313 #address-cells = <1>;
314 #size-cells = <0>;
315
316 port@0 {
317 reg = <0>;
318
319 i2s4_cif: endpoint {
320 remote-endpoint = <&xbar_i2s4>;
321 };
322 };
323
324 i2s4_port: port@1 {
325 reg = <1>;
326
327 i2s4_dap: endpoint {
328 dai-format = "i2s";
329 /* placeholder for external codec */
330 };
331 };
332 };
333 };
334
335 tegra_i2s5: i2s@2901400 {
336 compatible = "nvidia,tegra234-i2s",
337 "nvidia,tegra210-i2s";
338 reg = <0x0 0x2901400 0x0 0x100>;
339 clocks = <&bpmp TEGRA234_CLK_I2S5>,
340 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
341 clock-names = "i2s", "sync_input";
342 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
343 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
344 assigned-clock-rates = <1536000>;
345 sound-name-prefix = "I2S5";
346 status = "disabled";
347
348 ports {
349 #address-cells = <1>;
350 #size-cells = <0>;
351
352 port@0 {
353 reg = <0>;
354
355 i2s5_cif: endpoint {
356 remote-endpoint = <&xbar_i2s5>;
357 };
358 };
359
360 i2s5_port: port@1 {
361 reg = <1>;
362
363 i2s5_dap: endpoint {
364 dai-format = "i2s";
365 /* placeholder for external codec */
366 };
367 };
368 };
369 };
370
371 tegra_i2s6: i2s@2901500 {
372 compatible = "nvidia,tegra234-i2s",
373 "nvidia,tegra210-i2s";
374 reg = <0x0 0x2901500 0x0 0x100>;
375 clocks = <&bpmp TEGRA234_CLK_I2S6>,
376 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
377 clock-names = "i2s", "sync_input";
378 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
380 assigned-clock-rates = <1536000>;
381 sound-name-prefix = "I2S6";
382 status = "disabled";
383
384 ports {
385 #address-cells = <1>;
386 #size-cells = <0>;
387
388 port@0 {
389 reg = <0>;
390
391 i2s6_cif: endpoint {
392 remote-endpoint = <&xbar_i2s6>;
393 };
394 };
395
396 i2s6_port: port@1 {
397 reg = <1>;
398
399 i2s6_dap: endpoint {
400 dai-format = "i2s";
401 /* placeholder for external codec */
402 };
403 };
404 };
405 };
406
407 tegra_sfc1: sfc@2902000 {
408 compatible = "nvidia,tegra234-sfc",
409 "nvidia,tegra210-sfc";
410 reg = <0x0 0x2902000 0x0 0x200>;
411 sound-name-prefix = "SFC1";
412
413 ports {
414 #address-cells = <1>;
415 #size-cells = <0>;
416
417 port@0 {
418 reg = <0>;
419
420 sfc1_cif_in: endpoint {
421 remote-endpoint = <&xbar_sfc1_in>;
422 };
423 };
424
425 sfc1_out_port: port@1 {
426 reg = <1>;
427
428 sfc1_cif_out: endpoint {
429 remote-endpoint = <&xbar_sfc1_out>;
430 };
431 };
432 };
433 };
434
435 tegra_sfc2: sfc@2902200 {
436 compatible = "nvidia,tegra234-sfc",
437 "nvidia,tegra210-sfc";
438 reg = <0x0 0x2902200 0x0 0x200>;
439 sound-name-prefix = "SFC2";
440
441 ports {
442 #address-cells = <1>;
443 #size-cells = <0>;
444
445 port@0 {
446 reg = <0>;
447
448 sfc2_cif_in: endpoint {
449 remote-endpoint = <&xbar_sfc2_in>;
450 };
451 };
452
453 sfc2_out_port: port@1 {
454 reg = <1>;
455
456 sfc2_cif_out: endpoint {
457 remote-endpoint = <&xbar_sfc2_out>;
458 };
459 };
460 };
461 };
462
463 tegra_sfc3: sfc@2902400 {
464 compatible = "nvidia,tegra234-sfc",
465 "nvidia,tegra210-sfc";
466 reg = <0x0 0x2902400 0x0 0x200>;
467 sound-name-prefix = "SFC3";
468
469 ports {
470 #address-cells = <1>;
471 #size-cells = <0>;
472
473 port@0 {
474 reg = <0>;
475
476 sfc3_cif_in: endpoint {
477 remote-endpoint = <&xbar_sfc3_in>;
478 };
479 };
480
481 sfc3_out_port: port@1 {
482 reg = <1>;
483
484 sfc3_cif_out: endpoint {
485 remote-endpoint = <&xbar_sfc3_out>;
486 };
487 };
488 };
489 };
490
491 tegra_sfc4: sfc@2902600 {
492 compatible = "nvidia,tegra234-sfc",
493 "nvidia,tegra210-sfc";
494 reg = <0x0 0x2902600 0x0 0x200>;
495 sound-name-prefix = "SFC4";
496
497 ports {
498 #address-cells = <1>;
499 #size-cells = <0>;
500
501 port@0 {
502 reg = <0>;
503
504 sfc4_cif_in: endpoint {
505 remote-endpoint = <&xbar_sfc4_in>;
506 };
507 };
508
509 sfc4_out_port: port@1 {
510 reg = <1>;
511
512 sfc4_cif_out: endpoint {
513 remote-endpoint = <&xbar_sfc4_out>;
514 };
515 };
516 };
517 };
518
519 tegra_amx1: amx@2903000 {
520 compatible = "nvidia,tegra234-amx",
521 "nvidia,tegra194-amx";
522 reg = <0x0 0x2903000 0x0 0x100>;
523 sound-name-prefix = "AMX1";
524
525 ports {
526 #address-cells = <1>;
527 #size-cells = <0>;
528
529 port@0 {
530 reg = <0>;
531
532 amx1_in1: endpoint {
533 remote-endpoint = <&xbar_amx1_in1>;
534 };
535 };
536
537 port@1 {
538 reg = <1>;
539
540 amx1_in2: endpoint {
541 remote-endpoint = <&xbar_amx1_in2>;
542 };
543 };
544
545 port@2 {
546 reg = <2>;
547
548 amx1_in3: endpoint {
549 remote-endpoint = <&xbar_amx1_in3>;
550 };
551 };
552
553 port@3 {
554 reg = <3>;
555
556 amx1_in4: endpoint {
557 remote-endpoint = <&xbar_amx1_in4>;
558 };
559 };
560
561 amx1_out_port: port@4 {
562 reg = <4>;
563
564 amx1_out: endpoint {
565 remote-endpoint = <&xbar_amx1_out>;
566 };
567 };
568 };
569 };
570
571 tegra_amx2: amx@2903100 {
572 compatible = "nvidia,tegra234-amx",
573 "nvidia,tegra194-amx";
574 reg = <0x0 0x2903100 0x0 0x100>;
575 sound-name-prefix = "AMX2";
576
577 ports {
578 #address-cells = <1>;
579 #size-cells = <0>;
580
581 port@0 {
582 reg = <0>;
583
584 amx2_in1: endpoint {
585 remote-endpoint = <&xbar_amx2_in1>;
586 };
587 };
588
589 port@1 {
590 reg = <1>;
591
592 amx2_in2: endpoint {
593 remote-endpoint = <&xbar_amx2_in2>;
594 };
595 };
596
597 port@2 {
598 reg = <2>;
599
600 amx2_in3: endpoint {
601 remote-endpoint = <&xbar_amx2_in3>;
602 };
603 };
604
605 port@3 {
606 reg = <3>;
607
608 amx2_in4: endpoint {
609 remote-endpoint = <&xbar_amx2_in4>;
610 };
611 };
612
613 amx2_out_port: port@4 {
614 reg = <4>;
615
616 amx2_out: endpoint {
617 remote-endpoint = <&xbar_amx2_out>;
618 };
619 };
620 };
621 };
622
623 tegra_amx3: amx@2903200 {
624 compatible = "nvidia,tegra234-amx",
625 "nvidia,tegra194-amx";
626 reg = <0x0 0x2903200 0x0 0x100>;
627 sound-name-prefix = "AMX3";
628
629 ports {
630 #address-cells = <1>;
631 #size-cells = <0>;
632
633 port@0 {
634 reg = <0>;
635
636 amx3_in1: endpoint {
637 remote-endpoint = <&xbar_amx3_in1>;
638 };
639 };
640
641 port@1 {
642 reg = <1>;
643
644 amx3_in2: endpoint {
645 remote-endpoint = <&xbar_amx3_in2>;
646 };
647 };
648
649 port@2 {
650 reg = <2>;
651
652 amx3_in3: endpoint {
653 remote-endpoint = <&xbar_amx3_in3>;
654 };
655 };
656
657 port@3 {
658 reg = <3>;
659
660 amx3_in4: endpoint {
661 remote-endpoint = <&xbar_amx3_in4>;
662 };
663 };
664
665 amx3_out_port: port@4 {
666 reg = <4>;
667
668 amx3_out: endpoint {
669 remote-endpoint = <&xbar_amx3_out>;
670 };
671 };
672 };
673 };
674
675 tegra_amx4: amx@2903300 {
676 compatible = "nvidia,tegra234-amx",
677 "nvidia,tegra194-amx";
678 reg = <0x0 0x2903300 0x0 0x100>;
679 sound-name-prefix = "AMX4";
680
681 ports {
682 #address-cells = <1>;
683 #size-cells = <0>;
684
685 port@0 {
686 reg = <0>;
687
688 amx4_in1: endpoint {
689 remote-endpoint = <&xbar_amx4_in1>;
690 };
691 };
692
693 port@1 {
694 reg = <1>;
695
696 amx4_in2: endpoint {
697 remote-endpoint = <&xbar_amx4_in2>;
698 };
699 };
700
701 port@2 {
702 reg = <2>;
703
704 amx4_in3: endpoint {
705 remote-endpoint = <&xbar_amx4_in3>;
706 };
707 };
708
709 port@3 {
710 reg = <3>;
711
712 amx4_in4: endpoint {
713 remote-endpoint = <&xbar_amx4_in4>;
714 };
715 };
716
717 amx4_out_port: port@4 {
718 reg = <4>;
719
720 amx4_out: endpoint {
721 remote-endpoint = <&xbar_amx4_out>;
722 };
723 };
724 };
725 };
726
727 tegra_adx1: adx@2903800 {
728 compatible = "nvidia,tegra234-adx",
729 "nvidia,tegra210-adx";
730 reg = <0x0 0x2903800 0x0 0x100>;
731 sound-name-prefix = "ADX1";
732
733 ports {
734 #address-cells = <1>;
735 #size-cells = <0>;
736
737 port@0 {
738 reg = <0>;
739
740 adx1_in: endpoint {
741 remote-endpoint = <&xbar_adx1_in>;
742 };
743 };
744
745 adx1_out1_port: port@1 {
746 reg = <1>;
747
748 adx1_out1: endpoint {
749 remote-endpoint = <&xbar_adx1_out1>;
750 };
751 };
752
753 adx1_out2_port: port@2 {
754 reg = <2>;
755
756 adx1_out2: endpoint {
757 remote-endpoint = <&xbar_adx1_out2>;
758 };
759 };
760
761 adx1_out3_port: port@3 {
762 reg = <3>;
763
764 adx1_out3: endpoint {
765 remote-endpoint = <&xbar_adx1_out3>;
766 };
767 };
768
769 adx1_out4_port: port@4 {
770 reg = <4>;
771
772 adx1_out4: endpoint {
773 remote-endpoint = <&xbar_adx1_out4>;
774 };
775 };
776 };
777 };
778
779 tegra_adx2: adx@2903900 {
780 compatible = "nvidia,tegra234-adx",
781 "nvidia,tegra210-adx";
782 reg = <0x0 0x2903900 0x0 0x100>;
783 sound-name-prefix = "ADX2";
784
785 ports {
786 #address-cells = <1>;
787 #size-cells = <0>;
788
789 port@0 {
790 reg = <0>;
791
792 adx2_in: endpoint {
793 remote-endpoint = <&xbar_adx2_in>;
794 };
795 };
796
797 adx2_out1_port: port@1 {
798 reg = <1>;
799
800 adx2_out1: endpoint {
801 remote-endpoint = <&xbar_adx2_out1>;
802 };
803 };
804
805 adx2_out2_port: port@2 {
806 reg = <2>;
807
808 adx2_out2: endpoint {
809 remote-endpoint = <&xbar_adx2_out2>;
810 };
811 };
812
813 adx2_out3_port: port@3 {
814 reg = <3>;
815
816 adx2_out3: endpoint {
817 remote-endpoint = <&xbar_adx2_out3>;
818 };
819 };
820
821 adx2_out4_port: port@4 {
822 reg = <4>;
823
824 adx2_out4: endpoint {
825 remote-endpoint = <&xbar_adx2_out4>;
826 };
827 };
828 };
829 };
830
831 tegra_adx3: adx@2903a00 {
832 compatible = "nvidia,tegra234-adx",
833 "nvidia,tegra210-adx";
834 reg = <0x0 0x2903a00 0x0 0x100>;
835 sound-name-prefix = "ADX3";
836
837 ports {
838 #address-cells = <1>;
839 #size-cells = <0>;
840
841 port@0 {
842 reg = <0>;
843
844 adx3_in: endpoint {
845 remote-endpoint = <&xbar_adx3_in>;
846 };
847 };
848
849 adx3_out1_port: port@1 {
850 reg = <1>;
851
852 adx3_out1: endpoint {
853 remote-endpoint = <&xbar_adx3_out1>;
854 };
855 };
856
857 adx3_out2_port: port@2 {
858 reg = <2>;
859
860 adx3_out2: endpoint {
861 remote-endpoint = <&xbar_adx3_out2>;
862 };
863 };
864
865 adx3_out3_port: port@3 {
866 reg = <3>;
867
868 adx3_out3: endpoint {
869 remote-endpoint = <&xbar_adx3_out3>;
870 };
871 };
872
873 adx3_out4_port: port@4 {
874 reg = <4>;
875
876 adx3_out4: endpoint {
877 remote-endpoint = <&xbar_adx3_out4>;
878 };
879 };
880 };
881 };
882
883 tegra_adx4: adx@2903b00 {
884 compatible = "nvidia,tegra234-adx",
885 "nvidia,tegra210-adx";
886 reg = <0x0 0x2903b00 0x0 0x100>;
887 sound-name-prefix = "ADX4";
888
889 ports {
890 #address-cells = <1>;
891 #size-cells = <0>;
892
893 port@0 {
894 reg = <0>;
895
896 adx4_in: endpoint {
897 remote-endpoint = <&xbar_adx4_in>;
898 };
899 };
900
901 adx4_out1_port: port@1 {
902 reg = <1>;
903
904 adx4_out1: endpoint {
905 remote-endpoint = <&xbar_adx4_out1>;
906 };
907 };
908
909 adx4_out2_port: port@2 {
910 reg = <2>;
911
912 adx4_out2: endpoint {
913 remote-endpoint = <&xbar_adx4_out2>;
914 };
915 };
916
917 adx4_out3_port: port@3 {
918 reg = <3>;
919
920 adx4_out3: endpoint {
921 remote-endpoint = <&xbar_adx4_out3>;
922 };
923 };
924
925 adx4_out4_port: port@4 {
926 reg = <4>;
927
928 adx4_out4: endpoint {
929 remote-endpoint = <&xbar_adx4_out4>;
930 };
931 };
932 };
933 };
934
935
936 tegra_dmic1: dmic@2904000 {
937 compatible = "nvidia,tegra234-dmic",
938 "nvidia,tegra210-dmic";
939 reg = <0x0 0x2904000 0x0 0x100>;
940 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
941 clock-names = "dmic";
942 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
943 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
944 assigned-clock-rates = <3072000>;
945 sound-name-prefix = "DMIC1";
946 status = "disabled";
947
948 ports {
949 #address-cells = <1>;
950 #size-cells = <0>;
951
952 port@0 {
953 reg = <0>;
954
955 dmic1_cif: endpoint {
956 remote-endpoint = <&xbar_dmic1>;
957 };
958 };
959
960 dmic1_port: port@1 {
961 reg = <1>;
962
963 dmic1_dap: endpoint {
964 /* placeholder for external codec */
965 };
966 };
967 };
968 };
969
970 tegra_dmic2: dmic@2904100 {
971 compatible = "nvidia,tegra234-dmic",
972 "nvidia,tegra210-dmic";
973 reg = <0x0 0x2904100 0x0 0x100>;
974 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
975 clock-names = "dmic";
976 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
977 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
978 assigned-clock-rates = <3072000>;
979 sound-name-prefix = "DMIC2";
980 status = "disabled";
981
982 ports {
983 #address-cells = <1>;
984 #size-cells = <0>;
985
986 port@0 {
987 reg = <0>;
988
989 dmic2_cif: endpoint {
990 remote-endpoint = <&xbar_dmic2>;
991 };
992 };
993
994 dmic2_port: port@1 {
995 reg = <1>;
996
997 dmic2_dap: endpoint {
998 /* placeholder for external codec */
999 };
1000 };
1001 };
1002 };
1003
1004 tegra_dmic3: dmic@2904200 {
1005 compatible = "nvidia,tegra234-dmic",
1006 "nvidia,tegra210-dmic";
1007 reg = <0x0 0x2904200 0x0 0x100>;
1008 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
1009 clock-names = "dmic";
1010 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
1011 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1012 assigned-clock-rates = <3072000>;
1013 sound-name-prefix = "DMIC3";
1014 status = "disabled";
1015
1016 ports {
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019
1020 port@0 {
1021 reg = <0>;
1022
1023 dmic3_cif: endpoint {
1024 remote-endpoint = <&xbar_dmic3>;
1025 };
1026 };
1027
1028 dmic3_port: port@1 {
1029 reg = <1>;
1030
1031 dmic3_dap: endpoint {
1032 /* placeholder for external codec */
1033 };
1034 };
1035 };
1036 };
1037
1038 tegra_dmic4: dmic@2904300 {
1039 compatible = "nvidia,tegra234-dmic",
1040 "nvidia,tegra210-dmic";
1041 reg = <0x0 0x2904300 0x0 0x100>;
1042 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
1043 clock-names = "dmic";
1044 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
1045 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1046 assigned-clock-rates = <3072000>;
1047 sound-name-prefix = "DMIC4";
1048 status = "disabled";
1049
1050 ports {
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1053
1054 port@0 {
1055 reg = <0>;
1056
1057 dmic4_cif: endpoint {
1058 remote-endpoint = <&xbar_dmic4>;
1059 };
1060 };
1061
1062 dmic4_port: port@1 {
1063 reg = <1>;
1064
1065 dmic4_dap: endpoint {
1066 /* placeholder for external codec */
1067 };
1068 };
1069 };
1070 };
1071
1072 tegra_dspk1: dspk@2905000 {
1073 compatible = "nvidia,tegra234-dspk",
1074 "nvidia,tegra186-dspk";
1075 reg = <0x0 0x2905000 0x0 0x100>;
1076 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
1077 clock-names = "dspk";
1078 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
1079 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1080 assigned-clock-rates = <12288000>;
1081 sound-name-prefix = "DSPK1";
1082 status = "disabled";
1083
1084 ports {
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1087
1088 port@0 {
1089 reg = <0>;
1090
1091 dspk1_cif: endpoint {
1092 remote-endpoint = <&xbar_dspk1>;
1093 };
1094 };
1095
1096 dspk1_port: port@1 {
1097 reg = <1>;
1098
1099 dspk1_dap: endpoint {
1100 /* placeholder for external codec */
1101 };
1102 };
1103 };
1104 };
1105
1106 tegra_dspk2: dspk@2905100 {
1107 compatible = "nvidia,tegra234-dspk",
1108 "nvidia,tegra186-dspk";
1109 reg = <0x0 0x2905100 0x0 0x100>;
1110 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
1111 clock-names = "dspk";
1112 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
1113 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1114 assigned-clock-rates = <12288000>;
1115 sound-name-prefix = "DSPK2";
1116 status = "disabled";
1117
1118 ports {
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121
1122 port@0 {
1123 reg = <0>;
1124
1125 dspk2_cif: endpoint {
1126 remote-endpoint = <&xbar_dspk2>;
1127 };
1128 };
1129
1130 dspk2_port: port@1 {
1131 reg = <1>;
1132
1133 dspk2_dap: endpoint {
1134 /* placeholder for external codec */
1135 };
1136 };
1137 };
1138 };
1139
1140 tegra_ope1: processing-engine@2908000 {
1141 compatible = "nvidia,tegra234-ope",
1142 "nvidia,tegra210-ope";
1143 reg = <0x0 0x2908000 0x0 0x100>;
1144 sound-name-prefix = "OPE1";
1145
1146 #address-cells = <2>;
1147 #size-cells = <2>;
1148 ranges;
1149
1150 equalizer@2908100 {
1151 compatible = "nvidia,tegra234-peq",
1152 "nvidia,tegra210-peq";
1153 reg = <0x0 0x2908100 0x0 0x100>;
1154 };
1155
1156 dynamic-range-compressor@2908200 {
1157 compatible = "nvidia,tegra234-mbdrc",
1158 "nvidia,tegra210-mbdrc";
1159 reg = <0x0 0x2908200 0x0 0x200>;
1160 };
1161
1162 ports {
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165
1166 port@0 {
1167 reg = <0x0>;
1168
1169 ope1_cif_in_ep: endpoint {
1170 remote-endpoint =
1171 <&xbar_ope1_in_ep>;
1172 };
1173 };
1174
1175 ope1_out_port: port@1 {
1176 reg = <0x1>;
1177
1178 ope1_cif_out_ep: endpoint {
1179 remote-endpoint =
1180 <&xbar_ope1_out_ep>;
1181 };
1182 };
1183 };
1184 };
1185
1186 tegra_mvc1: mvc@290a000 {
1187 compatible = "nvidia,tegra234-mvc",
1188 "nvidia,tegra210-mvc";
1189 reg = <0x0 0x290a000 0x0 0x200>;
1190 sound-name-prefix = "MVC1";
1191
1192 ports {
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195
1196 port@0 {
1197 reg = <0>;
1198
1199 mvc1_cif_in: endpoint {
1200 remote-endpoint = <&xbar_mvc1_in>;
1201 };
1202 };
1203
1204 mvc1_out_port: port@1 {
1205 reg = <1>;
1206
1207 mvc1_cif_out: endpoint {
1208 remote-endpoint = <&xbar_mvc1_out>;
1209 };
1210 };
1211 };
1212 };
1213
1214 tegra_mvc2: mvc@290a200 {
1215 compatible = "nvidia,tegra234-mvc",
1216 "nvidia,tegra210-mvc";
1217 reg = <0x0 0x290a200 0x0 0x200>;
1218 sound-name-prefix = "MVC2";
1219
1220 ports {
1221 #address-cells = <1>;
1222 #size-cells = <0>;
1223
1224 port@0 {
1225 reg = <0>;
1226
1227 mvc2_cif_in: endpoint {
1228 remote-endpoint = <&xbar_mvc2_in>;
1229 };
1230 };
1231
1232 mvc2_out_port: port@1 {
1233 reg = <1>;
1234
1235 mvc2_cif_out: endpoint {
1236 remote-endpoint = <&xbar_mvc2_out>;
1237 };
1238 };
1239 };
1240 };
1241
1242 tegra_amixer: amixer@290bb00 {
1243 compatible = "nvidia,tegra234-amixer",
1244 "nvidia,tegra210-amixer";
1245 reg = <0x0 0x290bb00 0x0 0x800>;
1246 sound-name-prefix = "MIXER1";
1247
1248 ports {
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251
1252 port@0 {
1253 reg = <0x0>;
1254
1255 mix_in1: endpoint {
1256 remote-endpoint = <&xbar_mix_in1>;
1257 };
1258 };
1259
1260 port@1 {
1261 reg = <0x1>;
1262
1263 mix_in2: endpoint {
1264 remote-endpoint = <&xbar_mix_in2>;
1265 };
1266 };
1267
1268 port@2 {
1269 reg = <0x2>;
1270
1271 mix_in3: endpoint {
1272 remote-endpoint = <&xbar_mix_in3>;
1273 };
1274 };
1275
1276 port@3 {
1277 reg = <0x3>;
1278
1279 mix_in4: endpoint {
1280 remote-endpoint = <&xbar_mix_in4>;
1281 };
1282 };
1283
1284 port@4 {
1285 reg = <0x4>;
1286
1287 mix_in5: endpoint {
1288 remote-endpoint = <&xbar_mix_in5>;
1289 };
1290 };
1291
1292 port@5 {
1293 reg = <0x5>;
1294
1295 mix_in6: endpoint {
1296 remote-endpoint = <&xbar_mix_in6>;
1297 };
1298 };
1299
1300 port@6 {
1301 reg = <0x6>;
1302
1303 mix_in7: endpoint {
1304 remote-endpoint = <&xbar_mix_in7>;
1305 };
1306 };
1307
1308 port@7 {
1309 reg = <0x7>;
1310
1311 mix_in8: endpoint {
1312 remote-endpoint = <&xbar_mix_in8>;
1313 };
1314 };
1315
1316 port@8 {
1317 reg = <0x8>;
1318
1319 mix_in9: endpoint {
1320 remote-endpoint = <&xbar_mix_in9>;
1321 };
1322 };
1323
1324 port@9 {
1325 reg = <0x9>;
1326
1327 mix_in10: endpoint {
1328 remote-endpoint = <&xbar_mix_in10>;
1329 };
1330 };
1331
1332 mix_out1_port: port@a {
1333 reg = <0xa>;
1334
1335 mix_out1: endpoint {
1336 remote-endpoint = <&xbar_mix_out1>;
1337 };
1338 };
1339
1340 mix_out2_port: port@b {
1341 reg = <0xb>;
1342
1343 mix_out2: endpoint {
1344 remote-endpoint = <&xbar_mix_out2>;
1345 };
1346 };
1347
1348 mix_out3_port: port@c {
1349 reg = <0xc>;
1350
1351 mix_out3: endpoint {
1352 remote-endpoint = <&xbar_mix_out3>;
1353 };
1354 };
1355
1356 mix_out4_port: port@d {
1357 reg = <0xd>;
1358
1359 mix_out4: endpoint {
1360 remote-endpoint = <&xbar_mix_out4>;
1361 };
1362 };
1363
1364 mix_out5_port: port@e {
1365 reg = <0xe>;
1366
1367 mix_out5: endpoint {
1368 remote-endpoint = <&xbar_mix_out5>;
1369 };
1370 };
1371 };
1372 };
1373
1374 tegra_admaif: admaif@290f000 {
1375 compatible = "nvidia,tegra234-admaif",
1376 "nvidia,tegra186-admaif";
1377 reg = <0x0 0x0290f000 0x0 0x1000>;
1378 dmas = <&adma 1>, <&adma 1>,
1379 <&adma 2>, <&adma 2>,
1380 <&adma 3>, <&adma 3>,
1381 <&adma 4>, <&adma 4>,
1382 <&adma 5>, <&adma 5>,
1383 <&adma 6>, <&adma 6>,
1384 <&adma 7>, <&adma 7>,
1385 <&adma 8>, <&adma 8>,
1386 <&adma 9>, <&adma 9>,
1387 <&adma 10>, <&adma 10>,
1388 <&adma 11>, <&adma 11>,
1389 <&adma 12>, <&adma 12>,
1390 <&adma 13>, <&adma 13>,
1391 <&adma 14>, <&adma 14>,
1392 <&adma 15>, <&adma 15>,
1393 <&adma 16>, <&adma 16>,
1394 <&adma 17>, <&adma 17>,
1395 <&adma 18>, <&adma 18>,
1396 <&adma 19>, <&adma 19>,
1397 <&adma 20>, <&adma 20>;
1398 dma-names = "rx1", "tx1",
1399 "rx2", "tx2",
1400 "rx3", "tx3",
1401 "rx4", "tx4",
1402 "rx5", "tx5",
1403 "rx6", "tx6",
1404 "rx7", "tx7",
1405 "rx8", "tx8",
1406 "rx9", "tx9",
1407 "rx10", "tx10",
1408 "rx11", "tx11",
1409 "rx12", "tx12",
1410 "rx13", "tx13",
1411 "rx14", "tx14",
1412 "rx15", "tx15",
1413 "rx16", "tx16",
1414 "rx17", "tx17",
1415 "rx18", "tx18",
1416 "rx19", "tx19",
1417 "rx20", "tx20";
1418 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
1419 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
1420 interconnect-names = "dma-mem", "write";
1421 iommus = <&smmu_niso0 TEGRA234_SID_APE>;
1422
1423 ports {
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1426
1427 admaif0_port: port@0 {
1428 reg = <0x0>;
1429
1430 admaif0: endpoint {
1431 remote-endpoint = <&xbar_admaif0>;
1432 };
1433 };
1434
1435 admaif1_port: port@1 {
1436 reg = <0x1>;
1437
1438 admaif1: endpoint {
1439 remote-endpoint = <&xbar_admaif1>;
1440 };
1441 };
1442
1443 admaif2_port: port@2 {
1444 reg = <0x2>;
1445
1446 admaif2: endpoint {
1447 remote-endpoint = <&xbar_admaif2>;
1448 };
1449 };
1450
1451 admaif3_port: port@3 {
1452 reg = <0x3>;
1453
1454 admaif3: endpoint {
1455 remote-endpoint = <&xbar_admaif3>;
1456 };
1457 };
1458
1459 admaif4_port: port@4 {
1460 reg = <0x4>;
1461
1462 admaif4: endpoint {
1463 remote-endpoint = <&xbar_admaif4>;
1464 };
1465 };
1466
1467 admaif5_port: port@5 {
1468 reg = <0x5>;
1469
1470 admaif5: endpoint {
1471 remote-endpoint = <&xbar_admaif5>;
1472 };
1473 };
1474
1475 admaif6_port: port@6 {
1476 reg = <0x6>;
1477
1478 admaif6: endpoint {
1479 remote-endpoint = <&xbar_admaif6>;
1480 };
1481 };
1482
1483 admaif7_port: port@7 {
1484 reg = <0x7>;
1485
1486 admaif7: endpoint {
1487 remote-endpoint = <&xbar_admaif7>;
1488 };
1489 };
1490
1491 admaif8_port: port@8 {
1492 reg = <0x8>;
1493
1494 admaif8: endpoint {
1495 remote-endpoint = <&xbar_admaif8>;
1496 };
1497 };
1498
1499 admaif9_port: port@9 {
1500 reg = <0x9>;
1501
1502 admaif9: endpoint {
1503 remote-endpoint = <&xbar_admaif9>;
1504 };
1505 };
1506
1507 admaif10_port: port@a {
1508 reg = <0xa>;
1509
1510 admaif10: endpoint {
1511 remote-endpoint = <&xbar_admaif10>;
1512 };
1513 };
1514
1515 admaif11_port: port@b {
1516 reg = <0xb>;
1517
1518 admaif11: endpoint {
1519 remote-endpoint = <&xbar_admaif11>;
1520 };
1521 };
1522
1523 admaif12_port: port@c {
1524 reg = <0xc>;
1525
1526 admaif12: endpoint {
1527 remote-endpoint = <&xbar_admaif12>;
1528 };
1529 };
1530
1531 admaif13_port: port@d {
1532 reg = <0xd>;
1533
1534 admaif13: endpoint {
1535 remote-endpoint = <&xbar_admaif13>;
1536 };
1537 };
1538
1539 admaif14_port: port@e {
1540 reg = <0xe>;
1541
1542 admaif14: endpoint {
1543 remote-endpoint = <&xbar_admaif14>;
1544 };
1545 };
1546
1547 admaif15_port: port@f {
1548 reg = <0xf>;
1549
1550 admaif15: endpoint {
1551 remote-endpoint = <&xbar_admaif15>;
1552 };
1553 };
1554
1555 admaif16_port: port@10 {
1556 reg = <0x10>;
1557
1558 admaif16: endpoint {
1559 remote-endpoint = <&xbar_admaif16>;
1560 };
1561 };
1562
1563 admaif17_port: port@11 {
1564 reg = <0x11>;
1565
1566 admaif17: endpoint {
1567 remote-endpoint = <&xbar_admaif17>;
1568 };
1569 };
1570
1571 admaif18_port: port@12 {
1572 reg = <0x12>;
1573
1574 admaif18: endpoint {
1575 remote-endpoint = <&xbar_admaif18>;
1576 };
1577 };
1578
1579 admaif19_port: port@13 {
1580 reg = <0x13>;
1581
1582 admaif19: endpoint {
1583 remote-endpoint = <&xbar_admaif19>;
1584 };
1585 };
1586 };
1587 };
1588
1589 tegra_asrc: asrc@2910000 {
1590 compatible = "nvidia,tegra234-asrc",
1591 "nvidia,tegra186-asrc";
1592 reg = <0x0 0x2910000 0x0 0x2000>;
1593 sound-name-prefix = "ASRC1";
1594
1595 ports {
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1598
1599 port@0 {
1600 reg = <0x0>;
1601
1602 asrc_in1_ep: endpoint {
1603 remote-endpoint =
1604 <&xbar_asrc_in1_ep>;
1605 };
1606 };
1607
1608 port@1 {
1609 reg = <0x1>;
1610
1611 asrc_in2_ep: endpoint {
1612 remote-endpoint =
1613 <&xbar_asrc_in2_ep>;
1614 };
1615 };
1616
1617 port@2 {
1618 reg = <0x2>;
1619
1620 asrc_in3_ep: endpoint {
1621 remote-endpoint =
1622 <&xbar_asrc_in3_ep>;
1623 };
1624 };
1625
1626 port@3 {
1627 reg = <0x3>;
1628
1629 asrc_in4_ep: endpoint {
1630 remote-endpoint =
1631 <&xbar_asrc_in4_ep>;
1632 };
1633 };
1634
1635 port@4 {
1636 reg = <0x4>;
1637
1638 asrc_in5_ep: endpoint {
1639 remote-endpoint =
1640 <&xbar_asrc_in5_ep>;
1641 };
1642 };
1643
1644 port@5 {
1645 reg = <0x5>;
1646
1647 asrc_in6_ep: endpoint {
1648 remote-endpoint =
1649 <&xbar_asrc_in6_ep>;
1650 };
1651 };
1652
1653 port@6 {
1654 reg = <0x6>;
1655
1656 asrc_in7_ep: endpoint {
1657 remote-endpoint =
1658 <&xbar_asrc_in7_ep>;
1659 };
1660 };
1661
1662 asrc_out1_port: port@7 {
1663 reg = <0x7>;
1664
1665 asrc_out1_ep: endpoint {
1666 remote-endpoint =
1667 <&xbar_asrc_out1_ep>;
1668 };
1669 };
1670
1671 asrc_out2_port: port@8 {
1672 reg = <0x8>;
1673
1674 asrc_out2_ep: endpoint {
1675 remote-endpoint =
1676 <&xbar_asrc_out2_ep>;
1677 };
1678 };
1679
1680 asrc_out3_port: port@9 {
1681 reg = <0x9>;
1682
1683 asrc_out3_ep: endpoint {
1684 remote-endpoint =
1685 <&xbar_asrc_out3_ep>;
1686 };
1687 };
1688
1689 asrc_out4_port: port@a {
1690 reg = <0xa>;
1691
1692 asrc_out4_ep: endpoint {
1693 remote-endpoint =
1694 <&xbar_asrc_out4_ep>;
1695 };
1696 };
1697
1698 asrc_out5_port: port@b {
1699 reg = <0xb>;
1700
1701 asrc_out5_ep: endpoint {
1702 remote-endpoint =
1703 <&xbar_asrc_out5_ep>;
1704 };
1705 };
1706
1707 asrc_out6_port: port@c {
1708 reg = <0xc>;
1709
1710 asrc_out6_ep: endpoint {
1711 remote-endpoint =
1712 <&xbar_asrc_out6_ep>;
1713 };
1714 };
1715 };
1716 };
1717
1718 ports {
1719 #address-cells = <1>;
1720 #size-cells = <0>;
1721
1722 port@0 {
1723 reg = <0x0>;
1724
1725 xbar_admaif0: endpoint {
1726 remote-endpoint = <&admaif0>;
1727 };
1728 };
1729
1730 port@1 {
1731 reg = <0x1>;
1732
1733 xbar_admaif1: endpoint {
1734 remote-endpoint = <&admaif1>;
1735 };
1736 };
1737
1738 port@2 {
1739 reg = <0x2>;
1740
1741 xbar_admaif2: endpoint {
1742 remote-endpoint = <&admaif2>;
1743 };
1744 };
1745
1746 port@3 {
1747 reg = <0x3>;
1748
1749 xbar_admaif3: endpoint {
1750 remote-endpoint = <&admaif3>;
1751 };
1752 };
1753
1754 port@4 {
1755 reg = <0x4>;
1756
1757 xbar_admaif4: endpoint {
1758 remote-endpoint = <&admaif4>;
1759 };
1760 };
1761
1762 port@5 {
1763 reg = <0x5>;
1764
1765 xbar_admaif5: endpoint {
1766 remote-endpoint = <&admaif5>;
1767 };
1768 };
1769
1770 port@6 {
1771 reg = <0x6>;
1772
1773 xbar_admaif6: endpoint {
1774 remote-endpoint = <&admaif6>;
1775 };
1776 };
1777
1778 port@7 {
1779 reg = <0x7>;
1780
1781 xbar_admaif7: endpoint {
1782 remote-endpoint = <&admaif7>;
1783 };
1784 };
1785
1786 port@8 {
1787 reg = <0x8>;
1788
1789 xbar_admaif8: endpoint {
1790 remote-endpoint = <&admaif8>;
1791 };
1792 };
1793
1794 port@9 {
1795 reg = <0x9>;
1796
1797 xbar_admaif9: endpoint {
1798 remote-endpoint = <&admaif9>;
1799 };
1800 };
1801
1802 port@a {
1803 reg = <0xa>;
1804
1805 xbar_admaif10: endpoint {
1806 remote-endpoint = <&admaif10>;
1807 };
1808 };
1809
1810 port@b {
1811 reg = <0xb>;
1812
1813 xbar_admaif11: endpoint {
1814 remote-endpoint = <&admaif11>;
1815 };
1816 };
1817
1818 port@c {
1819 reg = <0xc>;
1820
1821 xbar_admaif12: endpoint {
1822 remote-endpoint = <&admaif12>;
1823 };
1824 };
1825
1826 port@d {
1827 reg = <0xd>;
1828
1829 xbar_admaif13: endpoint {
1830 remote-endpoint = <&admaif13>;
1831 };
1832 };
1833
1834 port@e {
1835 reg = <0xe>;
1836
1837 xbar_admaif14: endpoint {
1838 remote-endpoint = <&admaif14>;
1839 };
1840 };
1841
1842 port@f {
1843 reg = <0xf>;
1844
1845 xbar_admaif15: endpoint {
1846 remote-endpoint = <&admaif15>;
1847 };
1848 };
1849
1850 port@10 {
1851 reg = <0x10>;
1852
1853 xbar_admaif16: endpoint {
1854 remote-endpoint = <&admaif16>;
1855 };
1856 };
1857
1858 port@11 {
1859 reg = <0x11>;
1860
1861 xbar_admaif17: endpoint {
1862 remote-endpoint = <&admaif17>;
1863 };
1864 };
1865
1866 port@12 {
1867 reg = <0x12>;
1868
1869 xbar_admaif18: endpoint {
1870 remote-endpoint = <&admaif18>;
1871 };
1872 };
1873
1874 port@13 {
1875 reg = <0x13>;
1876
1877 xbar_admaif19: endpoint {
1878 remote-endpoint = <&admaif19>;
1879 };
1880 };
1881
1882 xbar_i2s1_port: port@14 {
1883 reg = <0x14>;
1884
1885 xbar_i2s1: endpoint {
1886 remote-endpoint = <&i2s1_cif>;
1887 };
1888 };
1889
1890 xbar_i2s2_port: port@15 {
1891 reg = <0x15>;
1892
1893 xbar_i2s2: endpoint {
1894 remote-endpoint = <&i2s2_cif>;
1895 };
1896 };
1897
1898 xbar_i2s3_port: port@16 {
1899 reg = <0x16>;
1900
1901 xbar_i2s3: endpoint {
1902 remote-endpoint = <&i2s3_cif>;
1903 };
1904 };
1905
1906 xbar_i2s4_port: port@17 {
1907 reg = <0x17>;
1908
1909 xbar_i2s4: endpoint {
1910 remote-endpoint = <&i2s4_cif>;
1911 };
1912 };
1913
1914 xbar_i2s5_port: port@18 {
1915 reg = <0x18>;
1916
1917 xbar_i2s5: endpoint {
1918 remote-endpoint = <&i2s5_cif>;
1919 };
1920 };
1921
1922 xbar_i2s6_port: port@19 {
1923 reg = <0x19>;
1924
1925 xbar_i2s6: endpoint {
1926 remote-endpoint = <&i2s6_cif>;
1927 };
1928 };
1929
1930 xbar_dmic1_port: port@1a {
1931 reg = <0x1a>;
1932
1933 xbar_dmic1: endpoint {
1934 remote-endpoint = <&dmic1_cif>;
1935 };
1936 };
1937
1938 xbar_dmic2_port: port@1b {
1939 reg = <0x1b>;
1940
1941 xbar_dmic2: endpoint {
1942 remote-endpoint = <&dmic2_cif>;
1943 };
1944 };
1945
1946 xbar_dmic3_port: port@1c {
1947 reg = <0x1c>;
1948
1949 xbar_dmic3: endpoint {
1950 remote-endpoint = <&dmic3_cif>;
1951 };
1952 };
1953
1954 xbar_dmic4_port: port@1d {
1955 reg = <0x1d>;
1956
1957 xbar_dmic4: endpoint {
1958 remote-endpoint = <&dmic4_cif>;
1959 };
1960 };
1961
1962 xbar_dspk1_port: port@1e {
1963 reg = <0x1e>;
1964
1965 xbar_dspk1: endpoint {
1966 remote-endpoint = <&dspk1_cif>;
1967 };
1968 };
1969
1970 xbar_dspk2_port: port@1f {
1971 reg = <0x1f>;
1972
1973 xbar_dspk2: endpoint {
1974 remote-endpoint = <&dspk2_cif>;
1975 };
1976 };
1977
1978 xbar_sfc1_in_port: port@20 {
1979 reg = <0x20>;
1980
1981 xbar_sfc1_in: endpoint {
1982 remote-endpoint = <&sfc1_cif_in>;
1983 };
1984 };
1985
1986 port@21 {
1987 reg = <0x21>;
1988
1989 xbar_sfc1_out: endpoint {
1990 remote-endpoint = <&sfc1_cif_out>;
1991 };
1992 };
1993
1994 xbar_sfc2_in_port: port@22 {
1995 reg = <0x22>;
1996
1997 xbar_sfc2_in: endpoint {
1998 remote-endpoint = <&sfc2_cif_in>;
1999 };
2000 };
2001
2002 port@23 {
2003 reg = <0x23>;
2004
2005 xbar_sfc2_out: endpoint {
2006 remote-endpoint = <&sfc2_cif_out>;
2007 };
2008 };
2009
2010 xbar_sfc3_in_port: port@24 {
2011 reg = <0x24>;
2012
2013 xbar_sfc3_in: endpoint {
2014 remote-endpoint = <&sfc3_cif_in>;
2015 };
2016 };
2017
2018 port@25 {
2019 reg = <0x25>;
2020
2021 xbar_sfc3_out: endpoint {
2022 remote-endpoint = <&sfc3_cif_out>;
2023 };
2024 };
2025
2026 xbar_sfc4_in_port: port@26 {
2027 reg = <0x26>;
2028
2029 xbar_sfc4_in: endpoint {
2030 remote-endpoint = <&sfc4_cif_in>;
2031 };
2032 };
2033
2034 port@27 {
2035 reg = <0x27>;
2036
2037 xbar_sfc4_out: endpoint {
2038 remote-endpoint = <&sfc4_cif_out>;
2039 };
2040 };
2041
2042 xbar_mvc1_in_port: port@28 {
2043 reg = <0x28>;
2044
2045 xbar_mvc1_in: endpoint {
2046 remote-endpoint = <&mvc1_cif_in>;
2047 };
2048 };
2049
2050 port@29 {
2051 reg = <0x29>;
2052
2053 xbar_mvc1_out: endpoint {
2054 remote-endpoint = <&mvc1_cif_out>;
2055 };
2056 };
2057
2058 xbar_mvc2_in_port: port@2a {
2059 reg = <0x2a>;
2060
2061 xbar_mvc2_in: endpoint {
2062 remote-endpoint = <&mvc2_cif_in>;
2063 };
2064 };
2065
2066 port@2b {
2067 reg = <0x2b>;
2068
2069 xbar_mvc2_out: endpoint {
2070 remote-endpoint = <&mvc2_cif_out>;
2071 };
2072 };
2073
2074 xbar_amx1_in1_port: port@2c {
2075 reg = <0x2c>;
2076
2077 xbar_amx1_in1: endpoint {
2078 remote-endpoint = <&amx1_in1>;
2079 };
2080 };
2081
2082 xbar_amx1_in2_port: port@2d {
2083 reg = <0x2d>;
2084
2085 xbar_amx1_in2: endpoint {
2086 remote-endpoint = <&amx1_in2>;
2087 };
2088 };
2089
2090 xbar_amx1_in3_port: port@2e {
2091 reg = <0x2e>;
2092
2093 xbar_amx1_in3: endpoint {
2094 remote-endpoint = <&amx1_in3>;
2095 };
2096 };
2097
2098 xbar_amx1_in4_port: port@2f {
2099 reg = <0x2f>;
2100
2101 xbar_amx1_in4: endpoint {
2102 remote-endpoint = <&amx1_in4>;
2103 };
2104 };
2105
2106 port@30 {
2107 reg = <0x30>;
2108
2109 xbar_amx1_out: endpoint {
2110 remote-endpoint = <&amx1_out>;
2111 };
2112 };
2113
2114 xbar_amx2_in1_port: port@31 {
2115 reg = <0x31>;
2116
2117 xbar_amx2_in1: endpoint {
2118 remote-endpoint = <&amx2_in1>;
2119 };
2120 };
2121
2122 xbar_amx2_in2_port: port@32 {
2123 reg = <0x32>;
2124
2125 xbar_amx2_in2: endpoint {
2126 remote-endpoint = <&amx2_in2>;
2127 };
2128 };
2129
2130 xbar_amx2_in3_port: port@33 {
2131 reg = <0x33>;
2132
2133 xbar_amx2_in3: endpoint {
2134 remote-endpoint = <&amx2_in3>;
2135 };
2136 };
2137
2138 xbar_amx2_in4_port: port@34 {
2139 reg = <0x34>;
2140
2141 xbar_amx2_in4: endpoint {
2142 remote-endpoint = <&amx2_in4>;
2143 };
2144 };
2145
2146 port@35 {
2147 reg = <0x35>;
2148
2149 xbar_amx2_out: endpoint {
2150 remote-endpoint = <&amx2_out>;
2151 };
2152 };
2153
2154 xbar_amx3_in1_port: port@36 {
2155 reg = <0x36>;
2156
2157 xbar_amx3_in1: endpoint {
2158 remote-endpoint = <&amx3_in1>;
2159 };
2160 };
2161
2162 xbar_amx3_in2_port: port@37 {
2163 reg = <0x37>;
2164
2165 xbar_amx3_in2: endpoint {
2166 remote-endpoint = <&amx3_in2>;
2167 };
2168 };
2169
2170 xbar_amx3_in3_port: port@38 {
2171 reg = <0x38>;
2172
2173 xbar_amx3_in3: endpoint {
2174 remote-endpoint = <&amx3_in3>;
2175 };
2176 };
2177
2178 xbar_amx3_in4_port: port@39 {
2179 reg = <0x39>;
2180
2181 xbar_amx3_in4: endpoint {
2182 remote-endpoint = <&amx3_in4>;
2183 };
2184 };
2185
2186 port@3a {
2187 reg = <0x3a>;
2188
2189 xbar_amx3_out: endpoint {
2190 remote-endpoint = <&amx3_out>;
2191 };
2192 };
2193
2194 xbar_amx4_in1_port: port@3b {
2195 reg = <0x3b>;
2196
2197 xbar_amx4_in1: endpoint {
2198 remote-endpoint = <&amx4_in1>;
2199 };
2200 };
2201
2202 xbar_amx4_in2_port: port@3c {
2203 reg = <0x3c>;
2204
2205 xbar_amx4_in2: endpoint {
2206 remote-endpoint = <&amx4_in2>;
2207 };
2208 };
2209
2210 xbar_amx4_in3_port: port@3d {
2211 reg = <0x3d>;
2212
2213 xbar_amx4_in3: endpoint {
2214 remote-endpoint = <&amx4_in3>;
2215 };
2216 };
2217
2218 xbar_amx4_in4_port: port@3e {
2219 reg = <0x3e>;
2220
2221 xbar_amx4_in4: endpoint {
2222 remote-endpoint = <&amx4_in4>;
2223 };
2224 };
2225
2226 port@3f {
2227 reg = <0x3f>;
2228
2229 xbar_amx4_out: endpoint {
2230 remote-endpoint = <&amx4_out>;
2231 };
2232 };
2233
2234 xbar_adx1_in_port: port@40 {
2235 reg = <0x40>;
2236
2237 xbar_adx1_in: endpoint {
2238 remote-endpoint = <&adx1_in>;
2239 };
2240 };
2241
2242 port@41 {
2243 reg = <0x41>;
2244
2245 xbar_adx1_out1: endpoint {
2246 remote-endpoint = <&adx1_out1>;
2247 };
2248 };
2249
2250 port@42 {
2251 reg = <0x42>;
2252
2253 xbar_adx1_out2: endpoint {
2254 remote-endpoint = <&adx1_out2>;
2255 };
2256 };
2257
2258 port@43 {
2259 reg = <0x43>;
2260
2261 xbar_adx1_out3: endpoint {
2262 remote-endpoint = <&adx1_out3>;
2263 };
2264 };
2265
2266 port@44 {
2267 reg = <0x44>;
2268
2269 xbar_adx1_out4: endpoint {
2270 remote-endpoint = <&adx1_out4>;
2271 };
2272 };
2273
2274 xbar_adx2_in_port: port@45 {
2275 reg = <0x45>;
2276
2277 xbar_adx2_in: endpoint {
2278 remote-endpoint = <&adx2_in>;
2279 };
2280 };
2281
2282 port@46 {
2283 reg = <0x46>;
2284
2285 xbar_adx2_out1: endpoint {
2286 remote-endpoint = <&adx2_out1>;
2287 };
2288 };
2289
2290 port@47 {
2291 reg = <0x47>;
2292
2293 xbar_adx2_out2: endpoint {
2294 remote-endpoint = <&adx2_out2>;
2295 };
2296 };
2297
2298 port@48 {
2299 reg = <0x48>;
2300
2301 xbar_adx2_out3: endpoint {
2302 remote-endpoint = <&adx2_out3>;
2303 };
2304 };
2305
2306 port@49 {
2307 reg = <0x49>;
2308
2309 xbar_adx2_out4: endpoint {
2310 remote-endpoint = <&adx2_out4>;
2311 };
2312 };
2313
2314 xbar_adx3_in_port: port@4a {
2315 reg = <0x4a>;
2316
2317 xbar_adx3_in: endpoint {
2318 remote-endpoint = <&adx3_in>;
2319 };
2320 };
2321
2322 port@4b {
2323 reg = <0x4b>;
2324
2325 xbar_adx3_out1: endpoint {
2326 remote-endpoint = <&adx3_out1>;
2327 };
2328 };
2329
2330 port@4c {
2331 reg = <0x4c>;
2332
2333 xbar_adx3_out2: endpoint {
2334 remote-endpoint = <&adx3_out2>;
2335 };
2336 };
2337
2338 port@4d {
2339 reg = <0x4d>;
2340
2341 xbar_adx3_out3: endpoint {
2342 remote-endpoint = <&adx3_out3>;
2343 };
2344 };
2345
2346 port@4e {
2347 reg = <0x4e>;
2348
2349 xbar_adx3_out4: endpoint {
2350 remote-endpoint = <&adx3_out4>;
2351 };
2352 };
2353
2354 xbar_adx4_in_port: port@4f {
2355 reg = <0x4f>;
2356
2357 xbar_adx4_in: endpoint {
2358 remote-endpoint = <&adx4_in>;
2359 };
2360 };
2361
2362 port@50 {
2363 reg = <0x50>;
2364
2365 xbar_adx4_out1: endpoint {
2366 remote-endpoint = <&adx4_out1>;
2367 };
2368 };
2369
2370 port@51 {
2371 reg = <0x51>;
2372
2373 xbar_adx4_out2: endpoint {
2374 remote-endpoint = <&adx4_out2>;
2375 };
2376 };
2377
2378 port@52 {
2379 reg = <0x52>;
2380
2381 xbar_adx4_out3: endpoint {
2382 remote-endpoint = <&adx4_out3>;
2383 };
2384 };
2385
2386 port@53 {
2387 reg = <0x53>;
2388
2389 xbar_adx4_out4: endpoint {
2390 remote-endpoint = <&adx4_out4>;
2391 };
2392 };
2393
2394 xbar_mix_in1_port: port@54 {
2395 reg = <0x54>;
2396
2397 xbar_mix_in1: endpoint {
2398 remote-endpoint = <&mix_in1>;
2399 };
2400 };
2401
2402 xbar_mix_in2_port: port@55 {
2403 reg = <0x55>;
2404
2405 xbar_mix_in2: endpoint {
2406 remote-endpoint = <&mix_in2>;
2407 };
2408 };
2409
2410 xbar_mix_in3_port: port@56 {
2411 reg = <0x56>;
2412
2413 xbar_mix_in3: endpoint {
2414 remote-endpoint = <&mix_in3>;
2415 };
2416 };
2417
2418 xbar_mix_in4_port: port@57 {
2419 reg = <0x57>;
2420
2421 xbar_mix_in4: endpoint {
2422 remote-endpoint = <&mix_in4>;
2423 };
2424 };
2425
2426 xbar_mix_in5_port: port@58 {
2427 reg = <0x58>;
2428
2429 xbar_mix_in5: endpoint {
2430 remote-endpoint = <&mix_in5>;
2431 };
2432 };
2433
2434 xbar_mix_in6_port: port@59 {
2435 reg = <0x59>;
2436
2437 xbar_mix_in6: endpoint {
2438 remote-endpoint = <&mix_in6>;
2439 };
2440 };
2441
2442 xbar_mix_in7_port: port@5a {
2443 reg = <0x5a>;
2444
2445 xbar_mix_in7: endpoint {
2446 remote-endpoint = <&mix_in7>;
2447 };
2448 };
2449
2450 xbar_mix_in8_port: port@5b {
2451 reg = <0x5b>;
2452
2453 xbar_mix_in8: endpoint {
2454 remote-endpoint = <&mix_in8>;
2455 };
2456 };
2457
2458 xbar_mix_in9_port: port@5c {
2459 reg = <0x5c>;
2460
2461 xbar_mix_in9: endpoint {
2462 remote-endpoint = <&mix_in9>;
2463 };
2464 };
2465
2466 xbar_mix_in10_port: port@5d {
2467 reg = <0x5d>;
2468
2469 xbar_mix_in10: endpoint {
2470 remote-endpoint = <&mix_in10>;
2471 };
2472 };
2473
2474 port@5e {
2475 reg = <0x5e>;
2476
2477 xbar_mix_out1: endpoint {
2478 remote-endpoint = <&mix_out1>;
2479 };
2480 };
2481
2482 port@5f {
2483 reg = <0x5f>;
2484
2485 xbar_mix_out2: endpoint {
2486 remote-endpoint = <&mix_out2>;
2487 };
2488 };
2489
2490 port@60 {
2491 reg = <0x60>;
2492
2493 xbar_mix_out3: endpoint {
2494 remote-endpoint = <&mix_out3>;
2495 };
2496 };
2497
2498 port@61 {
2499 reg = <0x61>;
2500
2501 xbar_mix_out4: endpoint {
2502 remote-endpoint = <&mix_out4>;
2503 };
2504 };
2505
2506 port@62 {
2507 reg = <0x62>;
2508
2509 xbar_mix_out5: endpoint {
2510 remote-endpoint = <&mix_out5>;
2511 };
2512 };
2513
2514 xbar_asrc_in1_port: port@63 {
2515 reg = <0x63>;
2516
2517 xbar_asrc_in1_ep: endpoint {
2518 remote-endpoint = <&asrc_in1_ep>;
2519 };
2520 };
2521
2522 port@64 {
2523 reg = <0x64>;
2524
2525 xbar_asrc_out1_ep: endpoint {
2526 remote-endpoint = <&asrc_out1_ep>;
2527 };
2528 };
2529
2530 xbar_asrc_in2_port: port@65 {
2531 reg = <0x65>;
2532
2533 xbar_asrc_in2_ep: endpoint {
2534 remote-endpoint = <&asrc_in2_ep>;
2535 };
2536 };
2537
2538 port@66 {
2539 reg = <0x66>;
2540
2541 xbar_asrc_out2_ep: endpoint {
2542 remote-endpoint = <&asrc_out2_ep>;
2543 };
2544 };
2545
2546 xbar_asrc_in3_port: port@67 {
2547 reg = <0x67>;
2548
2549 xbar_asrc_in3_ep: endpoint {
2550 remote-endpoint = <&asrc_in3_ep>;
2551 };
2552 };
2553
2554 port@68 {
2555 reg = <0x68>;
2556
2557 xbar_asrc_out3_ep: endpoint {
2558 remote-endpoint = <&asrc_out3_ep>;
2559 };
2560 };
2561
2562 xbar_asrc_in4_port: port@69 {
2563 reg = <0x69>;
2564
2565 xbar_asrc_in4_ep: endpoint {
2566 remote-endpoint = <&asrc_in4_ep>;
2567 };
2568 };
2569
2570 port@6a {
2571 reg = <0x6a>;
2572
2573 xbar_asrc_out4_ep: endpoint {
2574 remote-endpoint = <&asrc_out4_ep>;
2575 };
2576 };
2577
2578 xbar_asrc_in5_port: port@6b {
2579 reg = <0x6b>;
2580
2581 xbar_asrc_in5_ep: endpoint {
2582 remote-endpoint = <&asrc_in5_ep>;
2583 };
2584 };
2585
2586 port@6c {
2587 reg = <0x6c>;
2588
2589 xbar_asrc_out5_ep: endpoint {
2590 remote-endpoint = <&asrc_out5_ep>;
2591 };
2592 };
2593
2594 xbar_asrc_in6_port: port@6d {
2595 reg = <0x6d>;
2596
2597 xbar_asrc_in6_ep: endpoint {
2598 remote-endpoint = <&asrc_in6_ep>;
2599 };
2600 };
2601
2602 port@6e {
2603 reg = <0x6e>;
2604
2605 xbar_asrc_out6_ep: endpoint {
2606 remote-endpoint = <&asrc_out6_ep>;
2607 };
2608 };
2609
2610 xbar_asrc_in7_port: port@6f {
2611 reg = <0x6f>;
2612
2613 xbar_asrc_in7_ep: endpoint {
2614 remote-endpoint = <&asrc_in7_ep>;
2615 };
2616 };
2617
2618 xbar_ope1_in_port: port@70 {
2619 reg = <0x70>;
2620
2621 xbar_ope1_in_ep: endpoint {
2622 remote-endpoint = <&ope1_cif_in_ep>;
2623 };
2624 };
2625
2626 port@71 {
2627 reg = <0x71>;
2628
2629 xbar_ope1_out_ep: endpoint {
2630 remote-endpoint = <&ope1_cif_out_ep>;
2631 };
2632 };
2633 };
2634 };
2635
2636 adma: dma-controller@2930000 {
2637 compatible = "nvidia,tegra234-adma",
2638 "nvidia,tegra186-adma";
2639 reg = <0x0 0x02930000 0x0 0x20000>;
2640 interrupt-parent = <&agic>;
2641 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
2642 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
2643 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
2644 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2645 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2646 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
2647 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
2649 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2650 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
2651 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
2652 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
2653 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
2654 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
2655 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
2656 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
2657 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
2658 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
2659 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
2660 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
2661 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
2662 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
2663 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
2664 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
2665 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
2666 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
2667 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
2668 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
2669 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
2670 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
2671 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
2672 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2673 #dma-cells = <1>;
2674 clocks = <&bpmp TEGRA234_CLK_AHUB>;
2675 clock-names = "d_audio";
2676 status = "disabled";
2677 };
2678
2679 agic: interrupt-controller@2a40000 {
2680 compatible = "nvidia,tegra234-agic",
2681 "nvidia,tegra210-agic";
2682 #interrupt-cells = <3>;
2683 interrupt-controller;
2684 reg = <0x0 0x02a41000 0x0 0x1000>,
2685 <0x0 0x02a42000 0x0 0x2000>;
2686 interrupts = <GIC_SPI 145
2687 (GIC_CPU_MASK_SIMPLE(4) |
2688 IRQ_TYPE_LEVEL_HIGH)>;
2689 clocks = <&bpmp TEGRA234_CLK_APE>;
2690 clock-names = "clk";
2691 status = "disabled";
2692 };
2693 };
2694
2695 mc: memory-controller@2c00000 {
2696 compatible = "nvidia,tegra234-mc";
2697 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
2698 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
2699 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
2700 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
2701 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
2702 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
2703 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
2704 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
2705 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
2706 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
2707 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
2708 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
2709 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
2710 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
2711 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
2712 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
2713 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
2714 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
2715 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
2716 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
2717 "ch11", "ch12", "ch13", "ch14", "ch15";
2718 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2719 #interconnect-cells = <1>;
2720 status = "okay";
2721
2722 #address-cells = <2>;
2723 #size-cells = <2>;
2724 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
2725 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
2726 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
2727
2728 /*
2729 * Bit 39 of addresses passing through the memory
2730 * controller selects the XBAR format used when memory
2731 * is accessed. This is used to transparently access
2732 * memory in the XBAR format used by the discrete GPU
2733 * (bit 39 set) or Tegra (bit 39 clear).
2734 *
2735 * As a consequence, the operating system must ensure
2736 * that bit 39 is never used implicitly, for example
2737 * via an I/O virtual address mapping of an IOMMU. If
2738 * devices require access to the XBAR switch, their
2739 * drivers must set this bit explicitly.
2740 *
2741 * Limit the DMA range for memory clients to [38:0].
2742 */
2743 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
2744
2745 emc: external-memory-controller@2c60000 {
2746 compatible = "nvidia,tegra234-emc";
2747 reg = <0x0 0x02c60000 0x0 0x90000>,
2748 <0x0 0x01780000 0x0 0x80000>;
2749 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
2750 clocks = <&bpmp TEGRA234_CLK_EMC>;
2751 clock-names = "emc";
2752 status = "okay";
2753
2754 #interconnect-cells = <0>;
2755
2756 nvidia,bpmp = <&bpmp>;
2757 };
2758 };
2759
2760 uarta: serial@3100000 {
2761 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2762 reg = <0x0 0x03100000 0x0 0x10000>;
2763 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2764 clocks = <&bpmp TEGRA234_CLK_UARTA>;
2765 resets = <&bpmp TEGRA234_RESET_UARTA>;
2766 dmas = <&gpcdma 8>, <&gpcdma 8>;
2767 dma-names = "rx", "tx";
2768 status = "disabled";
2769 };
2770
2771 uarte: serial@3140000 {
2772 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2773 reg = <0x0 0x03140000 0x0 0x10000>;
2774 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2775 clocks = <&bpmp TEGRA234_CLK_UARTE>;
2776 resets = <&bpmp TEGRA234_RESET_UARTE>;
2777 dmas = <&gpcdma 20>, <&gpcdma 20>;
2778 dma-names = "rx", "tx";
2779 status = "disabled";
2780 };
2781
2782 gen1_i2c: i2c@3160000 {
2783 compatible = "nvidia,tegra194-i2c";
2784 reg = <0x0 0x3160000 0x0 0x100>;
2785 status = "disabled";
2786 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
2787 #address-cells = <1>;
2788 #size-cells = <0>;
2789 clock-frequency = <400000>;
2790 clocks = <&bpmp TEGRA234_CLK_I2C1>,
2791 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2792 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
2793 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2794 clock-names = "div-clk", "parent";
2795 resets = <&bpmp TEGRA234_RESET_I2C1>;
2796 reset-names = "i2c";
2797 dmas = <&gpcdma 21>, <&gpcdma 21>;
2798 dma-names = "rx", "tx";
2799 };
2800
2801 cam_i2c: i2c@3180000 {
2802 compatible = "nvidia,tegra194-i2c";
2803 reg = <0x0 0x3180000 0x0 0x100>;
2804 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
2805 #address-cells = <1>;
2806 #size-cells = <0>;
2807 status = "disabled";
2808 clock-frequency = <400000>;
2809 clocks = <&bpmp TEGRA234_CLK_I2C3>,
2810 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2811 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
2812 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2813 clock-names = "div-clk", "parent";
2814 resets = <&bpmp TEGRA234_RESET_I2C3>;
2815 reset-names = "i2c";
2816 dmas = <&gpcdma 23>, <&gpcdma 23>;
2817 dma-names = "rx", "tx";
2818 };
2819
2820 dp_aux_ch1_i2c: i2c@3190000 {
2821 compatible = "nvidia,tegra194-i2c";
2822 reg = <0x0 0x3190000 0x0 0x100>;
2823 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
2824 #address-cells = <1>;
2825 #size-cells = <0>;
2826 status = "disabled";
2827 clock-frequency = <100000>;
2828 clocks = <&bpmp TEGRA234_CLK_I2C4>,
2829 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2830 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
2831 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2832 clock-names = "div-clk", "parent";
2833 resets = <&bpmp TEGRA234_RESET_I2C4>;
2834 reset-names = "i2c";
2835 dmas = <&gpcdma 26>, <&gpcdma 26>;
2836 dma-names = "rx", "tx";
2837 };
2838
2839 dp_aux_ch0_i2c: i2c@31b0000 {
2840 compatible = "nvidia,tegra194-i2c";
2841 reg = <0x0 0x31b0000 0x0 0x100>;
2842 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2843 #address-cells = <1>;
2844 #size-cells = <0>;
2845 status = "disabled";
2846 clock-frequency = <100000>;
2847 clocks = <&bpmp TEGRA234_CLK_I2C6>,
2848 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2849 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
2850 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2851 clock-names = "div-clk", "parent";
2852 resets = <&bpmp TEGRA234_RESET_I2C6>;
2853 reset-names = "i2c";
2854 dmas = <&gpcdma 30>, <&gpcdma 30>;
2855 dma-names = "rx", "tx";
2856 };
2857
2858 dp_aux_ch2_i2c: i2c@31c0000 {
2859 compatible = "nvidia,tegra194-i2c";
2860 reg = <0x0 0x31c0000 0x0 0x100>;
2861 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2862 #address-cells = <1>;
2863 #size-cells = <0>;
2864 status = "disabled";
2865 clock-frequency = <100000>;
2866 clocks = <&bpmp TEGRA234_CLK_I2C7>,
2867 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2868 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
2869 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2870 clock-names = "div-clk", "parent";
2871 resets = <&bpmp TEGRA234_RESET_I2C7>;
2872 reset-names = "i2c";
2873 dmas = <&gpcdma 27>, <&gpcdma 27>;
2874 dma-names = "rx", "tx";
2875 };
2876
2877 uarti: serial@31d0000 {
2878 compatible = "arm,sbsa-uart";
2879 reg = <0x0 0x31d0000 0x0 0x10000>;
2880 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
2881 status = "disabled";
2882 };
2883
2884 dp_aux_ch3_i2c: i2c@31e0000 {
2885 compatible = "nvidia,tegra194-i2c";
2886 reg = <0x0 0x31e0000 0x0 0x100>;
2887 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2888 #address-cells = <1>;
2889 #size-cells = <0>;
2890 status = "disabled";
2891 clock-frequency = <100000>;
2892 clocks = <&bpmp TEGRA234_CLK_I2C9>,
2893 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2894 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
2895 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2896 clock-names = "div-clk", "parent";
2897 resets = <&bpmp TEGRA234_RESET_I2C9>;
2898 reset-names = "i2c";
2899 dmas = <&gpcdma 31>, <&gpcdma 31>;
2900 dma-names = "rx", "tx";
2901 };
2902
2903 spi@3210000 {
2904 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
2905 reg = <0x0 0x03210000 0x0 0x1000>;
2906 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2907 #address-cells = <1>;
2908 #size-cells = <0>;
2909 clocks = <&bpmp TEGRA234_CLK_SPI1>;
2910 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
2911 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2912 clock-names = "spi";
2913 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
2914 resets = <&bpmp TEGRA234_RESET_SPI1>;
2915 reset-names = "spi";
2916 dmas = <&gpcdma 15>, <&gpcdma 15>;
2917 dma-names = "rx", "tx";
2918 dma-coherent;
2919 status = "disabled";
2920 };
2921
2922 spi@3230000 {
2923 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
2924 reg = <0x0 0x03230000 0x0 0x1000>;
2925 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2926 #address-cells = <1>;
2927 #size-cells = <0>;
2928 clocks = <&bpmp TEGRA234_CLK_SPI3>;
2929 clock-names = "spi";
2930 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
2931 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
2932 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2933 resets = <&bpmp TEGRA234_RESET_SPI3>;
2934 reset-names = "spi";
2935 dmas = <&gpcdma 17>, <&gpcdma 17>;
2936 dma-names = "rx", "tx";
2937 dma-coherent;
2938 status = "disabled";
2939 };
2940
2941 spi@3270000 {
2942 compatible = "nvidia,tegra234-qspi";
2943 reg = <0x0 0x3270000 0x0 0x1000>;
2944 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
2945 #address-cells = <1>;
2946 #size-cells = <0>;
2947 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
2948 <&bpmp TEGRA234_CLK_QSPI0_PM>;
2949 clock-names = "qspi", "qspi_out";
2950 resets = <&bpmp TEGRA234_RESET_QSPI0>;
2951 status = "disabled";
2952 };
2953
2954 pwm1: pwm@3280000 {
2955 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2956 reg = <0x0 0x3280000 0x0 0x10000>;
2957 clocks = <&bpmp TEGRA234_CLK_PWM1>;
2958 resets = <&bpmp TEGRA234_RESET_PWM1>;
2959 reset-names = "pwm";
2960 status = "disabled";
2961 #pwm-cells = <2>;
2962 };
2963
2964 pwm2: pwm@3290000 {
2965 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2966 reg = <0x0 0x3290000 0x0 0x10000>;
2967 clocks = <&bpmp TEGRA234_CLK_PWM2>;
2968 resets = <&bpmp TEGRA234_RESET_PWM2>;
2969 reset-names = "pwm";
2970 status = "disabled";
2971 #pwm-cells = <2>;
2972 };
2973
2974 pwm3: pwm@32a0000 {
2975 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2976 reg = <0x0 0x32a0000 0x0 0x10000>;
2977 clocks = <&bpmp TEGRA234_CLK_PWM3>;
2978 resets = <&bpmp TEGRA234_RESET_PWM3>;
2979 reset-names = "pwm";
2980 status = "disabled";
2981 #pwm-cells = <2>;
2982 };
2983
2984 pwm5: pwm@32c0000 {
2985 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2986 reg = <0x0 0x32c0000 0x0 0x10000>;
2987 clocks = <&bpmp TEGRA234_CLK_PWM5>;
2988 resets = <&bpmp TEGRA234_RESET_PWM5>;
2989 reset-names = "pwm";
2990 status = "disabled";
2991 #pwm-cells = <2>;
2992 };
2993
2994 pwm6: pwm@32d0000 {
2995 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2996 reg = <0x0 0x32d0000 0x0 0x10000>;
2997 clocks = <&bpmp TEGRA234_CLK_PWM6>;
2998 resets = <&bpmp TEGRA234_RESET_PWM6>;
2999 reset-names = "pwm";
3000 status = "disabled";
3001 #pwm-cells = <2>;
3002 };
3003
3004 pwm7: pwm@32e0000 {
3005 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3006 reg = <0x0 0x32e0000 0x0 0x10000>;
3007 clocks = <&bpmp TEGRA234_CLK_PWM7>;
3008 resets = <&bpmp TEGRA234_RESET_PWM7>;
3009 reset-names = "pwm";
3010 status = "disabled";
3011 #pwm-cells = <2>;
3012 };
3013
3014 pwm8: pwm@32f0000 {
3015 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3016 reg = <0x0 0x32f0000 0x0 0x10000>;
3017 clocks = <&bpmp TEGRA234_CLK_PWM8>;
3018 resets = <&bpmp TEGRA234_RESET_PWM8>;
3019 reset-names = "pwm";
3020 status = "disabled";
3021 #pwm-cells = <2>;
3022 };
3023
3024 spi@3300000 {
3025 compatible = "nvidia,tegra234-qspi";
3026 reg = <0x0 0x3300000 0x0 0x1000>;
3027 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3028 #address-cells = <1>;
3029 #size-cells = <0>;
3030 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
3031 <&bpmp TEGRA234_CLK_QSPI1_PM>;
3032 clock-names = "qspi", "qspi_out";
3033 resets = <&bpmp TEGRA234_RESET_QSPI1>;
3034 status = "disabled";
3035 };
3036
3037 mmc@3400000 {
3038 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
3039 reg = <0x0 0x03400000 0x0 0x20000>;
3040 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
3041 clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
3042 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
3043 clock-names = "sdhci", "tmclk";
3044 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
3045 <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
3046 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
3047 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
3048 resets = <&bpmp TEGRA234_RESET_SDMMC1>;
3049 reset-names = "sdhci";
3050 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
3051 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
3052 interconnect-names = "dma-mem", "write";
3053 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
3054 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
3055 pinctrl-0 = <&sdmmc1_3v3>;
3056 pinctrl-1 = <&sdmmc1_1v8>;
3057 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
3058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
3059 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
3060 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
3061 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
3062 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
3063 nvidia,default-tap = <14>;
3064 nvidia,default-trim = <0x8>;
3065 sd-uhs-sdr25;
3066 sd-uhs-sdr50;
3067 sd-uhs-ddr50;
3068 sd-uhs-sdr104;
3069 status = "disabled";
3070 };
3071
3072 mmc@3460000 {
3073 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
3074 reg = <0x0 0x03460000 0x0 0x20000>;
3075 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
3076 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
3077 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
3078 clock-names = "sdhci", "tmclk";
3079 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
3080 <&bpmp TEGRA234_CLK_PLLC4>;
3081 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
3082 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
3083 reset-names = "sdhci";
3084 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
3085 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
3086 interconnect-names = "dma-mem", "write";
3087 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
3088 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
3089 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
3090 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
3091 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
3092 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
3093 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
3094 nvidia,default-tap = <0x8>;
3095 nvidia,default-trim = <0x14>;
3096 nvidia,dqs-trim = <40>;
3097 supports-cqe;
3098 status = "disabled";
3099 };
3100
3101 hda@3510000 {
3102 compatible = "nvidia,tegra234-hda";
3103 reg = <0x0 0x3510000 0x0 0x10000>;
3104 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
3105 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
3106 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
3107 clock-names = "hda", "hda2codec_2x";
3108 resets = <&bpmp TEGRA234_RESET_HDA>,
3109 <&bpmp TEGRA234_RESET_HDACODEC>;
3110 reset-names = "hda", "hda2codec_2x";
3111 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
3112 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
3113 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
3114 interconnect-names = "dma-mem", "write";
3115 iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
3116 status = "disabled";
3117 };
3118
3119 xusb_padctl: padctl@3520000 {
3120 compatible = "nvidia,tegra234-xusb-padctl";
3121 reg = <0x0 0x03520000 0x0 0x20000>,
3122 <0x0 0x03540000 0x0 0x10000>;
3123 reg-names = "padctl", "ao";
3124 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
3125
3126 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
3127 reset-names = "padctl";
3128
3129 status = "disabled";
3130
3131 pads {
3132 usb2 {
3133 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
3134 clock-names = "trk";
3135
3136 lanes {
3137 usb2-0 {
3138 nvidia,function = "xusb";
3139 status = "disabled";
3140 #phy-cells = <0>;
3141 };
3142
3143 usb2-1 {
3144 nvidia,function = "xusb";
3145 status = "disabled";
3146 #phy-cells = <0>;
3147 };
3148
3149 usb2-2 {
3150 nvidia,function = "xusb";
3151 status = "disabled";
3152 #phy-cells = <0>;
3153 };
3154
3155 usb2-3 {
3156 nvidia,function = "xusb";
3157 status = "disabled";
3158 #phy-cells = <0>;
3159 };
3160 };
3161 };
3162
3163 usb3 {
3164 lanes {
3165 usb3-0 {
3166 nvidia,function = "xusb";
3167 status = "disabled";
3168 #phy-cells = <0>;
3169 };
3170
3171 usb3-1 {
3172 nvidia,function = "xusb";
3173 status = "disabled";
3174 #phy-cells = <0>;
3175 };
3176
3177 usb3-2 {
3178 nvidia,function = "xusb";
3179 status = "disabled";
3180 #phy-cells = <0>;
3181 };
3182
3183 usb3-3 {
3184 nvidia,function = "xusb";
3185 status = "disabled";
3186 #phy-cells = <0>;
3187 };
3188 };
3189 };
3190 };
3191
3192 ports {
3193 usb2-0 {
3194 status = "disabled";
3195 };
3196
3197 usb2-1 {
3198 status = "disabled";
3199 };
3200
3201 usb2-2 {
3202 status = "disabled";
3203 };
3204
3205 usb2-3 {
3206 status = "disabled";
3207 };
3208
3209 usb3-0 {
3210 status = "disabled";
3211 };
3212
3213 usb3-1 {
3214 status = "disabled";
3215 };
3216
3217 usb3-2 {
3218 status = "disabled";
3219 };
3220
3221 usb3-3 {
3222 status = "disabled";
3223 };
3224 };
3225 };
3226
3227 usb@3550000 {
3228 compatible = "nvidia,tegra234-xudc";
3229 reg = <0x0 0x03550000 0x0 0x8000>,
3230 <0x0 0x03558000 0x0 0x8000>;
3231 reg-names = "base", "fpci";
3232 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
3233 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
3234 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
3235 <&bpmp TEGRA234_CLK_XUSB_SS>,
3236 <&bpmp TEGRA234_CLK_XUSB_FS>;
3237 clock-names = "dev", "ss", "ss_src", "fs_src";
3238 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>,
3239 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>;
3240 interconnect-names = "dma-mem", "write";
3241 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>;
3242 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
3243 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
3244 power-domain-names = "dev", "ss";
3245 nvidia,xusb-padctl = <&xusb_padctl>;
3246 dma-coherent;
3247 status = "disabled";
3248 };
3249
3250 usb@3610000 {
3251 compatible = "nvidia,tegra234-xusb";
3252 reg = <0x0 0x03610000 0x0 0x40000>,
3253 <0x0 0x03600000 0x0 0x10000>,
3254 <0x0 0x03650000 0x0 0x10000>;
3255 reg-names = "hcd", "fpci", "bar2";
3256
3257 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
3258 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3259
3260 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
3261 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
3262 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
3263 <&bpmp TEGRA234_CLK_XUSB_SS>,
3264 <&bpmp TEGRA234_CLK_CLK_M>,
3265 <&bpmp TEGRA234_CLK_XUSB_FS>,
3266 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
3267 <&bpmp TEGRA234_CLK_CLK_M>,
3268 <&bpmp TEGRA234_CLK_PLLE>;
3269 clock-names = "xusb_host", "xusb_falcon_src",
3270 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
3271 "xusb_fs_src", "pll_u_480m", "clk_m",
3272 "pll_e";
3273 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
3274 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
3275 interconnect-names = "dma-mem", "write";
3276 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;
3277
3278 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
3279 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
3280 power-domain-names = "xusb_host", "xusb_ss";
3281
3282 nvidia,xusb-padctl = <&xusb_padctl>;
3283 dma-coherent;
3284 status = "disabled";
3285 };
3286
3287 fuse@3810000 {
3288 compatible = "nvidia,tegra234-efuse";
3289 reg = <0x0 0x03810000 0x0 0x10000>;
3290 clocks = <&bpmp TEGRA234_CLK_FUSE>;
3291 clock-names = "fuse";
3292 };
3293
3294 hte_lic: hardware-timestamp@3aa0000 {
3295 compatible = "nvidia,tegra234-gte-lic";
3296 reg = <0x0 0x3aa0000 0x0 0x10000>;
3297 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3298 nvidia,int-threshold = <1>;
3299 #timestamp-cells = <1>;
3300 };
3301
3302 hsp_top0: hsp@3c00000 {
3303 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
3304 reg = <0x0 0x03c00000 0x0 0xa0000>;
3305 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
3306 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
3307 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
3308 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
3309 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
3310 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
3311 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3312 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
3313 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
3314 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
3315 "shared3", "shared4", "shared5", "shared6",
3316 "shared7";
3317 #mbox-cells = <2>;
3318 };
3319
3320 p2u_hsio_0: phy@3e00000 {
3321 compatible = "nvidia,tegra234-p2u";
3322 reg = <0x0 0x03e00000 0x0 0x10000>;
3323 reg-names = "ctl";
3324
3325 #phy-cells = <0>;
3326 };
3327
3328 p2u_hsio_1: phy@3e10000 {
3329 compatible = "nvidia,tegra234-p2u";
3330 reg = <0x0 0x03e10000 0x0 0x10000>;
3331 reg-names = "ctl";
3332
3333 #phy-cells = <0>;
3334 };
3335
3336 p2u_hsio_2: phy@3e20000 {
3337 compatible = "nvidia,tegra234-p2u";
3338 reg = <0x0 0x03e20000 0x0 0x10000>;
3339 reg-names = "ctl";
3340
3341 #phy-cells = <0>;
3342 };
3343
3344 p2u_hsio_3: phy@3e30000 {
3345 compatible = "nvidia,tegra234-p2u";
3346 reg = <0x0 0x03e30000 0x0 0x10000>;
3347 reg-names = "ctl";
3348
3349 #phy-cells = <0>;
3350 };
3351
3352 p2u_hsio_4: phy@3e40000 {
3353 compatible = "nvidia,tegra234-p2u";
3354 reg = <0x0 0x03e40000 0x0 0x10000>;
3355 reg-names = "ctl";
3356
3357 #phy-cells = <0>;
3358 };
3359
3360 p2u_hsio_5: phy@3e50000 {
3361 compatible = "nvidia,tegra234-p2u";
3362 reg = <0x0 0x03e50000 0x0 0x10000>;
3363 reg-names = "ctl";
3364
3365 #phy-cells = <0>;
3366 };
3367
3368 p2u_hsio_6: phy@3e60000 {
3369 compatible = "nvidia,tegra234-p2u";
3370 reg = <0x0 0x03e60000 0x0 0x10000>;
3371 reg-names = "ctl";
3372
3373 #phy-cells = <0>;
3374 };
3375
3376 p2u_hsio_7: phy@3e70000 {
3377 compatible = "nvidia,tegra234-p2u";
3378 reg = <0x0 0x03e70000 0x0 0x10000>;
3379 reg-names = "ctl";
3380
3381 #phy-cells = <0>;
3382 };
3383
3384 p2u_nvhs_0: phy@3e90000 {
3385 compatible = "nvidia,tegra234-p2u";
3386 reg = <0x0 0x03e90000 0x0 0x10000>;
3387 reg-names = "ctl";
3388
3389 #phy-cells = <0>;
3390 };
3391
3392 p2u_nvhs_1: phy@3ea0000 {
3393 compatible = "nvidia,tegra234-p2u";
3394 reg = <0x0 0x03ea0000 0x0 0x10000>;
3395 reg-names = "ctl";
3396
3397 #phy-cells = <0>;
3398 };
3399
3400 p2u_nvhs_2: phy@3eb0000 {
3401 compatible = "nvidia,tegra234-p2u";
3402 reg = <0x0 0x03eb0000 0x0 0x10000>;
3403 reg-names = "ctl";
3404
3405 #phy-cells = <0>;
3406 };
3407
3408 p2u_nvhs_3: phy@3ec0000 {
3409 compatible = "nvidia,tegra234-p2u";
3410 reg = <0x0 0x03ec0000 0x0 0x10000>;
3411 reg-names = "ctl";
3412
3413 #phy-cells = <0>;
3414 };
3415
3416 p2u_nvhs_4: phy@3ed0000 {
3417 compatible = "nvidia,tegra234-p2u";
3418 reg = <0x0 0x03ed0000 0x0 0x10000>;
3419 reg-names = "ctl";
3420
3421 #phy-cells = <0>;
3422 };
3423
3424 p2u_nvhs_5: phy@3ee0000 {
3425 compatible = "nvidia,tegra234-p2u";
3426 reg = <0x0 0x03ee0000 0x0 0x10000>;
3427 reg-names = "ctl";
3428
3429 #phy-cells = <0>;
3430 };
3431
3432 p2u_nvhs_6: phy@3ef0000 {
3433 compatible = "nvidia,tegra234-p2u";
3434 reg = <0x0 0x03ef0000 0x0 0x10000>;
3435 reg-names = "ctl";
3436
3437 #phy-cells = <0>;
3438 };
3439
3440 p2u_nvhs_7: phy@3f00000 {
3441 compatible = "nvidia,tegra234-p2u";
3442 reg = <0x0 0x03f00000 0x0 0x10000>;
3443 reg-names = "ctl";
3444
3445 #phy-cells = <0>;
3446 };
3447
3448 p2u_gbe_0: phy@3f20000 {
3449 compatible = "nvidia,tegra234-p2u";
3450 reg = <0x0 0x03f20000 0x0 0x10000>;
3451 reg-names = "ctl";
3452
3453 #phy-cells = <0>;
3454 };
3455
3456 p2u_gbe_1: phy@3f30000 {
3457 compatible = "nvidia,tegra234-p2u";
3458 reg = <0x0 0x03f30000 0x0 0x10000>;
3459 reg-names = "ctl";
3460
3461 #phy-cells = <0>;
3462 };
3463
3464 p2u_gbe_2: phy@3f40000 {
3465 compatible = "nvidia,tegra234-p2u";
3466 reg = <0x0 0x03f40000 0x0 0x10000>;
3467 reg-names = "ctl";
3468
3469 #phy-cells = <0>;
3470 };
3471
3472 p2u_gbe_3: phy@3f50000 {
3473 compatible = "nvidia,tegra234-p2u";
3474 reg = <0x0 0x03f50000 0x0 0x10000>;
3475 reg-names = "ctl";
3476
3477 #phy-cells = <0>;
3478 };
3479
3480 p2u_gbe_4: phy@3f60000 {
3481 compatible = "nvidia,tegra234-p2u";
3482 reg = <0x0 0x03f60000 0x0 0x10000>;
3483 reg-names = "ctl";
3484
3485 #phy-cells = <0>;
3486 };
3487
3488 p2u_gbe_5: phy@3f70000 {
3489 compatible = "nvidia,tegra234-p2u";
3490 reg = <0x0 0x03f70000 0x0 0x10000>;
3491 reg-names = "ctl";
3492
3493 #phy-cells = <0>;
3494 };
3495
3496 p2u_gbe_6: phy@3f80000 {
3497 compatible = "nvidia,tegra234-p2u";
3498 reg = <0x0 0x03f80000 0x0 0x10000>;
3499 reg-names = "ctl";
3500
3501 #phy-cells = <0>;
3502 };
3503
3504 p2u_gbe_7: phy@3f90000 {
3505 compatible = "nvidia,tegra234-p2u";
3506 reg = <0x0 0x03f90000 0x0 0x10000>;
3507 reg-names = "ctl";
3508
3509 #phy-cells = <0>;
3510 };
3511
3512 ethernet@6800000 {
3513 compatible = "nvidia,tegra234-mgbe";
3514 reg = <0x0 0x06800000 0x0 0x10000>,
3515 <0x0 0x06810000 0x0 0x10000>,
3516 <0x0 0x068a0000 0x0 0x10000>;
3517 reg-names = "hypervisor", "mac", "xpcs";
3518 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
3519 interrupt-names = "common";
3520 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
3521 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
3522 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
3523 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
3524 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
3525 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
3526 <&bpmp TEGRA234_CLK_MGBE0_TX>,
3527 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
3528 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
3529 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
3530 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
3531 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
3532 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3533 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3534 "rx-pcs", "tx-pcs";
3535 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
3536 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
3537 reset-names = "mac", "pcs";
3538 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
3539 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
3540 interconnect-names = "dma-mem", "write";
3541 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
3542 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
3543 status = "disabled";
3544
3545 snps,axi-config = <&mgbe0_axi_setup>;
3546
3547 mgbe0_axi_setup: stmmac-axi-config {
3548 snps,blen = <256 128 64 32>;
3549 snps,rd_osr_lmt = <63>;
3550 snps,wr_osr_lmt = <63>;
3551 };
3552 };
3553
3554 ethernet@6900000 {
3555 compatible = "nvidia,tegra234-mgbe";
3556 reg = <0x0 0x06900000 0x0 0x10000>,
3557 <0x0 0x06910000 0x0 0x10000>,
3558 <0x0 0x069a0000 0x0 0x10000>;
3559 reg-names = "hypervisor", "mac", "xpcs";
3560 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
3561 interrupt-names = "common";
3562 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
3563 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
3564 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
3565 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
3566 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
3567 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
3568 <&bpmp TEGRA234_CLK_MGBE1_TX>,
3569 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
3570 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
3571 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
3572 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
3573 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
3574 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3575 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3576 "rx-pcs", "tx-pcs";
3577 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
3578 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
3579 reset-names = "mac", "pcs";
3580 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
3581 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
3582 interconnect-names = "dma-mem", "write";
3583 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
3584 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
3585 status = "disabled";
3586
3587 snps,axi-config = <&mgbe1_axi_setup>;
3588
3589 mgbe1_axi_setup: stmmac-axi-config {
3590 snps,blen = <256 128 64 32>;
3591 snps,rd_osr_lmt = <63>;
3592 snps,wr_osr_lmt = <63>;
3593 };
3594 };
3595
3596 ethernet@6a00000 {
3597 compatible = "nvidia,tegra234-mgbe";
3598 reg = <0x0 0x06a00000 0x0 0x10000>,
3599 <0x0 0x06a10000 0x0 0x10000>,
3600 <0x0 0x06aa0000 0x0 0x10000>;
3601 reg-names = "hypervisor", "mac", "xpcs";
3602 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
3603 interrupt-names = "common";
3604 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
3605 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
3606 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
3607 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
3608 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
3609 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
3610 <&bpmp TEGRA234_CLK_MGBE2_TX>,
3611 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
3612 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
3613 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
3614 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
3615 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
3616 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3617 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3618 "rx-pcs", "tx-pcs";
3619 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
3620 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
3621 reset-names = "mac", "pcs";
3622 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
3623 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
3624 interconnect-names = "dma-mem", "write";
3625 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
3626 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3627 status = "disabled";
3628
3629 snps,axi-config = <&mgbe2_axi_setup>;
3630
3631 mgbe2_axi_setup: stmmac-axi-config {
3632 snps,blen = <256 128 64 32>;
3633 snps,rd_osr_lmt = <63>;
3634 snps,wr_osr_lmt = <63>;
3635 };
3636 };
3637
3638 ethernet@6b00000 {
3639 compatible = "nvidia,tegra234-mgbe";
3640 reg = <0x0 0x06b00000 0x0 0x10000>,
3641 <0x0 0x06b10000 0x0 0x10000>,
3642 <0x0 0x06ba0000 0x0 0x10000>;
3643 reg-names = "hypervisor", "mac", "xpcs";
3644 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
3645 interrupt-names = "common";
3646 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
3647 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
3648 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
3649 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
3650 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
3651 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
3652 <&bpmp TEGRA234_CLK_MGBE3_TX>,
3653 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
3654 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
3655 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
3656 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
3657 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
3658 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3659 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3660 "rx-pcs", "tx-pcs";
3661 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
3662 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
3663 reset-names = "mac", "pcs";
3664 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
3665 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
3666 interconnect-names = "dma-mem", "write";
3667 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
3668 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3669 status = "disabled";
3670 };
3671
3672 smmu_niso1: iommu@8000000 {
3673 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
3674 reg = <0x0 0x8000000 0x0 0x1000000>,
3675 <0x0 0x7000000 0x0 0x1000000>;
3676 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3677 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3678 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3679 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3680 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3681 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3682 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3683 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3684 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3685 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3686 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3687 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3688 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3689 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3690 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3691 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3692 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3693 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3694 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3695 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3696 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3697 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3698 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3699 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3700 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3701 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3702 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3703 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3704 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3705 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3706 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3707 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3708 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3709 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3710 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3711 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3712 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3713 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3714 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3715 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3716 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3717 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3718 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3719 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3720 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3721 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3722 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3723 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3724 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3725 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3726 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3727 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3728 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3731 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3732 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3733 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3734 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3735 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3736 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3737 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3738 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3739 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3740 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3741 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3742 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3743 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3744 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3745 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3746 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3747 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3748 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3749 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3750 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3751 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3752 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3753 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3754 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3755 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3756 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3757 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3758 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3759 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3760 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3761 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3762 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3763 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3764 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3765 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3766 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3767 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3768 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3769 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3770 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3771 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3772 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3773 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3774 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3775 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3776 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3777 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3778 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3779 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3780 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3781 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3782 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3783 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3784 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3785 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3786 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3787 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3788 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3789 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3790 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3791 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3792 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3793 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3794 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3795 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3796 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3797 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3798 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3799 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3800 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3801 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3802 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3803 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3804 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3805 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3806 stream-match-mask = <0x7f80>;
3807 #global-interrupts = <2>;
3808 #iommu-cells = <1>;
3809
3810 nvidia,memory-controller = <&mc>;
3811 status = "okay";
3812 };
3813
3814 sce-fabric@b600000 {
3815 compatible = "nvidia,tegra234-sce-fabric";
3816 reg = <0x0 0xb600000 0x0 0x40000>;
3817 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
3818 status = "okay";
3819 };
3820
3821 rce-fabric@be00000 {
3822 compatible = "nvidia,tegra234-rce-fabric";
3823 reg = <0x0 0xbe00000 0x0 0x40000>;
3824 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
3825 status = "okay";
3826 };
3827
3828 hsp_aon: hsp@c150000 {
3829 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
3830 reg = <0x0 0x0c150000 0x0 0x90000>;
3831 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
3832 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
3833 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3834 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
3835 /*
3836 * Shared interrupt 0 is routed only to AON/SPE, so
3837 * we only have 4 shared interrupts for the CCPLEX.
3838 */
3839 interrupt-names = "shared1", "shared2", "shared3", "shared4";
3840 #mbox-cells = <2>;
3841 };
3842
3843 hte_aon: hardware-timestamp@c1e0000 {
3844 compatible = "nvidia,tegra234-gte-aon";
3845 reg = <0x0 0xc1e0000 0x0 0x10000>;
3846 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3847 nvidia,int-threshold = <1>;
3848 nvidia,gpio-controller = <&gpio_aon>;
3849 #timestamp-cells = <1>;
3850 };
3851
3852 gen2_i2c: i2c@c240000 {
3853 compatible = "nvidia,tegra194-i2c";
3854 reg = <0x0 0xc240000 0x0 0x100>;
3855 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
3856 #address-cells = <1>;
3857 #size-cells = <0>;
3858 status = "disabled";
3859 clock-frequency = <100000>;
3860 clocks = <&bpmp TEGRA234_CLK_I2C2>,
3861 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3862 clock-names = "div-clk", "parent";
3863 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
3864 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3865 resets = <&bpmp TEGRA234_RESET_I2C2>;
3866 reset-names = "i2c";
3867 dmas = <&gpcdma 22>, <&gpcdma 22>;
3868 dma-names = "rx", "tx";
3869 };
3870
3871 gen8_i2c: i2c@c250000 {
3872 compatible = "nvidia,tegra194-i2c";
3873 reg = <0x0 0xc250000 0x0 0x100>;
3874 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3875 #address-cells = <1>;
3876 #size-cells = <0>;
3877 status = "disabled";
3878 clock-frequency = <400000>;
3879 clocks = <&bpmp TEGRA234_CLK_I2C8>,
3880 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3881 clock-names = "div-clk", "parent";
3882 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
3883 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3884 resets = <&bpmp TEGRA234_RESET_I2C8>;
3885 reset-names = "i2c";
3886 dmas = <&gpcdma 0>, <&gpcdma 0>;
3887 dma-names = "rx", "tx";
3888 };
3889
3890 spi@c260000 {
3891 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
3892 reg = <0x0 0x0c260000 0x0 0x1000>;
3893 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3894 #address-cells = <1>;
3895 #size-cells = <0>;
3896 clocks = <&bpmp TEGRA234_CLK_SPI2>;
3897 clock-names = "spi";
3898 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
3899 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
3900 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3901 resets = <&bpmp TEGRA234_RESET_SPI2>;
3902 reset-names = "spi";
3903 dmas = <&gpcdma 19>, <&gpcdma 19>;
3904 dma-names = "rx", "tx";
3905 dma-coherent;
3906 status = "disabled";
3907 };
3908
3909 rtc@c2a0000 {
3910 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
3911 reg = <0x0 0x0c2a0000 0x0 0x10000>;
3912 interrupt-parent = <&pmc>;
3913 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
3914 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
3915 clock-names = "rtc";
3916 status = "disabled";
3917 };
3918
3919 gpio_aon: gpio@c2f0000 {
3920 compatible = "nvidia,tegra234-gpio-aon";
3921 reg-names = "security", "gpio";
3922 reg = <0x0 0x0c2f0000 0x0 0x1000>,
3923 <0x0 0x0c2f1000 0x0 0x1000>;
3924 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
3925 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
3926 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
3927 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
3928 #interrupt-cells = <2>;
3929 interrupt-controller;
3930 #gpio-cells = <2>;
3931 gpio-controller;
3932 gpio-ranges = <&pinmux_aon 0 0 32>;
3933 };
3934
3935 pinmux_aon: pinmux@c300000 {
3936 compatible = "nvidia,tegra234-pinmux-aon";
3937 reg = <0x0 0xc300000 0x0 0x4000>;
3938 };
3939
3940 pwm4: pwm@c340000 {
3941 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3942 reg = <0x0 0xc340000 0x0 0x10000>;
3943 clocks = <&bpmp TEGRA234_CLK_PWM4>;
3944 resets = <&bpmp TEGRA234_RESET_PWM4>;
3945 reset-names = "pwm";
3946 status = "disabled";
3947 #pwm-cells = <2>;
3948 };
3949
3950 pmc: pmc@c360000 {
3951 compatible = "nvidia,tegra234-pmc";
3952 reg = <0x0 0x0c360000 0x0 0x10000>,
3953 <0x0 0x0c370000 0x0 0x10000>,
3954 <0x0 0x0c380000 0x0 0x10000>,
3955 <0x0 0x0c390000 0x0 0x10000>,
3956 <0x0 0x0c3a0000 0x0 0x10000>;
3957 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
3958
3959 #interrupt-cells = <2>;
3960 interrupt-controller;
3961
3962 sdmmc1_1v8: sdmmc1-1v8 {
3963 pins = "sdmmc1-hv";
3964 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
3965 };
3966
3967 sdmmc1_3v3: sdmmc1-3v3 {
3968 pins = "sdmmc1-hv";
3969 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
3970 };
3971
3972 sdmmc3_1v8: sdmmc3-1v8 {
3973 pins = "sdmmc3-hv";
3974 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
3975 };
3976
3977 sdmmc3_3v3: sdmmc3-3v3 {
3978 pins = "sdmmc3-hv";
3979 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
3980 };
3981 };
3982
3983 aon-fabric@c600000 {
3984 compatible = "nvidia,tegra234-aon-fabric";
3985 reg = <0x0 0xc600000 0x0 0x40000>;
3986 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
3987 status = "okay";
3988 };
3989
3990 bpmp-fabric@d600000 {
3991 compatible = "nvidia,tegra234-bpmp-fabric";
3992 reg = <0x0 0xd600000 0x0 0x40000>;
3993 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3994 status = "okay";
3995 };
3996
3997 dce-fabric@de00000 {
3998 compatible = "nvidia,tegra234-sce-fabric";
3999 reg = <0x0 0xde00000 0x0 0x40000>;
4000 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
4001 status = "okay";
4002 };
4003
4004 ccplex@e000000 {
4005 compatible = "nvidia,tegra234-ccplex-cluster";
4006 reg = <0x0 0x0e000000 0x0 0x5ffff>;
4007 nvidia,bpmp = <&bpmp>;
4008 status = "okay";
4009 };
4010
4011 gic: interrupt-controller@f400000 {
4012 compatible = "arm,gic-v3";
4013 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
4014 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
4015 interrupt-parent = <&gic>;
4016 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
4017
4018 #redistributor-regions = <1>;
4019 #interrupt-cells = <3>;
4020 interrupt-controller;
4021 };
4022
4023 smmu_iso: iommu@10000000 {
4024 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
4025 reg = <0x0 0x10000000 0x0 0x1000000>;
4026 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4027 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4028 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4029 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4030 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4031 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4032 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4033 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4034 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4035 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4036 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4037 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4038 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4039 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4040 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4041 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4042 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4043 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4044 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4045 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4046 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4047 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4048 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4049 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4050 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4051 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4052 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4053 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4054 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4055 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4056 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4057 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4058 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4059 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4060 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4061 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4062 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4063 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4064 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4065 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4066 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4067 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4068 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4069 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4070 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4071 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4072 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4073 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4074 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4075 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4076 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4077 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4078 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4079 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4080 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4081 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4082 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4083 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4084 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4085 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4086 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4087 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4088 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4089 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4090 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4091 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4092 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4093 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4094 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4095 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4096 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4097 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4098 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4099 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4100 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4101 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4102 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4103 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4104 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4105 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4106 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4107 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4108 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4109 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4110 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4111 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4112 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4113 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4114 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4115 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4116 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4117 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4118 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4119 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4120 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4121 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4122 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4123 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4124 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4125 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4126 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4127 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4128 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4129 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4130 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4131 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4132 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4133 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4134 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4135 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4136 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4137 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4138 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4139 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4140 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4141 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4142 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4143 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4144 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4145 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4146 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4147 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4148 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4149 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4150 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4151 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4152 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4153 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4154 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
4155 stream-match-mask = <0x7f80>;
4156 #global-interrupts = <1>;
4157 #iommu-cells = <1>;
4158
4159 nvidia,memory-controller = <&mc>;
4160 status = "okay";
4161 };
4162
4163 smmu_niso0: iommu@12000000 {
4164 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
4165 reg = <0x0 0x12000000 0x0 0x1000000>,
4166 <0x0 0x11000000 0x0 0x1000000>;
4167 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
4297 stream-match-mask = <0x7f80>;
4298 #global-interrupts = <2>;
4299 #iommu-cells = <1>;
4300
4301 nvidia,memory-controller = <&mc>;
4302 status = "okay";
4303 };
4304
4305 cbb-fabric@13a00000 {
4306 compatible = "nvidia,tegra234-cbb-fabric";
4307 reg = <0x0 0x13a00000 0x0 0x400000>;
4308 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
4309 status = "okay";
4310 };
4311
4312 host1x@13e00000 {
4313 compatible = "nvidia,tegra234-host1x";
4314 reg = <0x0 0x13e00000 0x0 0x10000>,
4315 <0x0 0x13e10000 0x0 0x10000>,
4316 <0x0 0x13e40000 0x0 0x10000>;
4317 reg-names = "common", "hypervisor", "vm";
4318 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4319 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
4320 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
4321 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
4322 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
4323 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
4324 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
4325 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
4326 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
4327 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
4328 "syncpt5", "syncpt6", "syncpt7", "host1x";
4329 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
4330 clock-names = "host1x";
4331
4332 #address-cells = <2>;
4333 #size-cells = <2>;
4334 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
4335
4336 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
4337 interconnect-names = "dma-mem";
4338 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
4339 dma-coherent;
4340
4341 /* Context isolation domains */
4342 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
4343 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
4344 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
4345 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
4346 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
4347 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
4348 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
4349 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
4350 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
4351 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
4352 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
4353 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
4354 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
4355 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
4356 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
4357 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
4358
4359 vic@15340000 {
4360 compatible = "nvidia,tegra234-vic";
4361 reg = <0x0 0x15340000 0x0 0x00040000>;
4362 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
4363 clocks = <&bpmp TEGRA234_CLK_VIC>;
4364 clock-names = "vic";
4365 resets = <&bpmp TEGRA234_RESET_VIC>;
4366 reset-names = "vic";
4367
4368 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
4369 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
4370 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
4371 interconnect-names = "dma-mem", "write";
4372 iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
4373 dma-coherent;
4374 };
4375
4376 nvdec@15480000 {
4377 compatible = "nvidia,tegra234-nvdec";
4378 reg = <0x0 0x15480000 0x0 0x00040000>;
4379 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
4380 <&bpmp TEGRA234_CLK_FUSE>,
4381 <&bpmp TEGRA234_CLK_TSEC_PKA>;
4382 clock-names = "nvdec", "fuse", "tsec_pka";
4383 resets = <&bpmp TEGRA234_RESET_NVDEC>;
4384 reset-names = "nvdec";
4385 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
4386 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
4387 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
4388 interconnect-names = "dma-mem", "write";
4389 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
4390 dma-coherent;
4391
4392 nvidia,memory-controller = <&mc>;
4393
4394 /*
4395 * Placeholder values that firmware needs to update with the real
4396 * offsets parsed from the microcode headers.
4397 */
4398 nvidia,bl-manifest-offset = <0>;
4399 nvidia,bl-data-offset = <0>;
4400 nvidia,bl-code-offset = <0>;
4401 nvidia,os-manifest-offset = <0>;
4402 nvidia,os-data-offset = <0>;
4403 nvidia,os-code-offset = <0>;
4404
4405 /*
4406 * Firmware needs to set this to "okay" once the above values have
4407 * been updated.
4408 */
4409 status = "disabled";
4410 };
4411
4412 crypto@15820000 {
4413 compatible = "nvidia,tegra234-se-aes";
4414 reg = <0x00 0x15820000 0x00 0x10000>;
4415 clocks = <&bpmp TEGRA234_CLK_SE>;
4416 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>;
4417 dma-coherent;
4418 };
4419
4420 crypto@15840000 {
4421 compatible = "nvidia,tegra234-se-hash";
4422 reg = <0x00 0x15840000 0x00 0x10000>;
4423 clocks = <&bpmp TEGRA234_CLK_SE>;
4424 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>;
4425 dma-coherent;
4426 };
4427 };
4428
4429 pcie@140a0000 {
4430 compatible = "nvidia,tegra234-pcie";
4431 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
4432 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
4433 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
4434 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4435 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4436 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4437 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4438
4439 #address-cells = <3>;
4440 #size-cells = <2>;
4441 device_type = "pci";
4442 num-lanes = <4>;
4443 num-viewport = <8>;
4444 linux,pci-domain = <8>;
4445
4446 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
4447 clock-names = "core";
4448
4449 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
4450 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
4451 reset-names = "apb", "core";
4452
4453 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4454 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4455 interrupt-names = "intr", "msi";
4456
4457 #interrupt-cells = <1>;
4458 interrupt-map-mask = <0 0 0 0>;
4459 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
4460
4461 nvidia,bpmp = <&bpmp 8>;
4462
4463 nvidia,aspm-cmrt-us = <60>;
4464 nvidia,aspm-pwr-on-t-us = <20>;
4465 nvidia,aspm-l0s-entrance-latency-us = <3>;
4466
4467 bus-range = <0x0 0xff>;
4468
4469 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4470 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4471 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4472
4473 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
4474 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
4475 interconnect-names = "dma-mem", "write";
4476 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
4477 iommu-map-mask = <0x0>;
4478 dma-coherent;
4479
4480 status = "disabled";
4481 };
4482
4483 pcie@140c0000 {
4484 compatible = "nvidia,tegra234-pcie";
4485 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
4486 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
4487 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
4488 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4489 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
4490 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4491 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4492
4493 #address-cells = <3>;
4494 #size-cells = <2>;
4495 device_type = "pci";
4496 num-lanes = <4>;
4497 num-viewport = <8>;
4498 linux,pci-domain = <9>;
4499
4500 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
4501 clock-names = "core";
4502
4503 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
4504 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
4505 reset-names = "apb", "core";
4506
4507 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4508 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4509 interrupt-names = "intr", "msi";
4510
4511 #interrupt-cells = <1>;
4512 interrupt-map-mask = <0 0 0 0>;
4513 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
4514
4515 nvidia,bpmp = <&bpmp 9>;
4516
4517 nvidia,aspm-cmrt-us = <60>;
4518 nvidia,aspm-pwr-on-t-us = <20>;
4519 nvidia,aspm-l0s-entrance-latency-us = <3>;
4520
4521 bus-range = <0x0 0xff>;
4522
4523 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
4524 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4525 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4526
4527 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
4528 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
4529 interconnect-names = "dma-mem", "write";
4530 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
4531 iommu-map-mask = <0x0>;
4532 dma-coherent;
4533
4534 status = "disabled";
4535 };
4536
4537 pcie@140e0000 {
4538 compatible = "nvidia,tegra234-pcie";
4539 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4540 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
4541 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
4542 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4543 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
4544 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4545 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4546
4547 #address-cells = <3>;
4548 #size-cells = <2>;
4549 device_type = "pci";
4550 num-lanes = <4>;
4551 num-viewport = <8>;
4552 linux,pci-domain = <10>;
4553
4554 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
4555 clock-names = "core";
4556
4557 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
4558 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
4559 reset-names = "apb", "core";
4560
4561 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4562 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4563 interrupt-names = "intr", "msi";
4564
4565 #interrupt-cells = <1>;
4566 interrupt-map-mask = <0 0 0 0>;
4567 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4568
4569 nvidia,bpmp = <&bpmp 10>;
4570
4571 nvidia,aspm-cmrt-us = <60>;
4572 nvidia,aspm-pwr-on-t-us = <20>;
4573 nvidia,aspm-l0s-entrance-latency-us = <3>;
4574
4575 bus-range = <0x0 0xff>;
4576
4577 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4578 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4579 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4580
4581 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
4582 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
4583 interconnect-names = "dma-mem", "write";
4584 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4585 iommu-map-mask = <0x0>;
4586 dma-coherent;
4587
4588 status = "disabled";
4589 };
4590
4591 pcie-ep@140e0000 {
4592 compatible = "nvidia,tegra234-pcie-ep";
4593 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4594 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
4595 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4596 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
4597 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
4598 reg-names = "appl", "atu_dma", "dbi", "addr_space";
4599
4600 num-lanes = <4>;
4601
4602 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
4603 clock-names = "core";
4604
4605 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
4606 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
4607 reset-names = "apb", "core";
4608
4609 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
4610 interrupt-names = "intr";
4611
4612 nvidia,bpmp = <&bpmp 10>;
4613
4614 nvidia,enable-ext-refclk;
4615 nvidia,aspm-cmrt-us = <60>;
4616 nvidia,aspm-pwr-on-t-us = <20>;
4617 nvidia,aspm-l0s-entrance-latency-us = <3>;
4618
4619 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
4620 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
4621 interconnect-names = "dma-mem", "write";
4622 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4623 iommu-map-mask = <0x0>;
4624 dma-coherent;
4625
4626 status = "disabled";
4627 };
4628
4629 pcie@14100000 {
4630 compatible = "nvidia,tegra234-pcie";
4631 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4632 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
4633 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
4634 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4635 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
4636 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
4637 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4638
4639 #address-cells = <3>;
4640 #size-cells = <2>;
4641 device_type = "pci";
4642 num-lanes = <1>;
4643 num-viewport = <8>;
4644 linux,pci-domain = <1>;
4645
4646 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
4647 clock-names = "core";
4648
4649 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
4650 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
4651 reset-names = "apb", "core";
4652
4653 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4654 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4655 interrupt-names = "intr", "msi";
4656
4657 #interrupt-cells = <1>;
4658 interrupt-map-mask = <0 0 0 0>;
4659 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
4660
4661 nvidia,bpmp = <&bpmp 1>;
4662
4663 nvidia,aspm-cmrt-us = <60>;
4664 nvidia,aspm-pwr-on-t-us = <20>;
4665 nvidia,aspm-l0s-entrance-latency-us = <3>;
4666
4667 bus-range = <0x0 0xff>;
4668
4669 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
4670 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4671 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4672
4673 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
4674 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
4675 interconnect-names = "dma-mem", "write";
4676 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
4677 iommu-map-mask = <0x0>;
4678 dma-coherent;
4679
4680 status = "disabled";
4681 };
4682
4683 pcie@14120000 {
4684 compatible = "nvidia,tegra234-pcie";
4685 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4686 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
4687 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
4688 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4689 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
4690 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
4691 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4692
4693 #address-cells = <3>;
4694 #size-cells = <2>;
4695 device_type = "pci";
4696 num-lanes = <1>;
4697 num-viewport = <8>;
4698 linux,pci-domain = <2>;
4699
4700 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
4701 clock-names = "core";
4702
4703 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
4704 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
4705 reset-names = "apb", "core";
4706
4707 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4708 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4709 interrupt-names = "intr", "msi";
4710
4711 #interrupt-cells = <1>;
4712 interrupt-map-mask = <0 0 0 0>;
4713 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
4714
4715 nvidia,bpmp = <&bpmp 2>;
4716
4717 nvidia,aspm-cmrt-us = <60>;
4718 nvidia,aspm-pwr-on-t-us = <20>;
4719 nvidia,aspm-l0s-entrance-latency-us = <3>;
4720
4721 bus-range = <0x0 0xff>;
4722
4723 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
4724 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4725 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4726
4727 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
4728 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
4729 interconnect-names = "dma-mem", "write";
4730 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
4731 iommu-map-mask = <0x0>;
4732 dma-coherent;
4733
4734 status = "disabled";
4735 };
4736
4737 pcie@14140000 {
4738 compatible = "nvidia,tegra234-pcie";
4739 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4740 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
4741 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
4742 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4743 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
4744 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4745 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4746
4747 #address-cells = <3>;
4748 #size-cells = <2>;
4749 device_type = "pci";
4750 num-lanes = <1>;
4751 num-viewport = <8>;
4752 linux,pci-domain = <3>;
4753
4754 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
4755 clock-names = "core";
4756
4757 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
4758 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
4759 reset-names = "apb", "core";
4760
4761 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4762 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4763 interrupt-names = "intr", "msi";
4764
4765 #interrupt-cells = <1>;
4766 interrupt-map-mask = <0 0 0 0>;
4767 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4768
4769 nvidia,bpmp = <&bpmp 3>;
4770
4771 nvidia,aspm-cmrt-us = <60>;
4772 nvidia,aspm-pwr-on-t-us = <20>;
4773 nvidia,aspm-l0s-entrance-latency-us = <3>;
4774
4775 bus-range = <0x0 0xff>;
4776
4777 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
4778 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4779 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4780
4781 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
4782 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
4783 interconnect-names = "dma-mem", "write";
4784 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
4785 iommu-map-mask = <0x0>;
4786 dma-coherent;
4787
4788 status = "disabled";
4789 };
4790
4791 pcie@14160000 {
4792 compatible = "nvidia,tegra234-pcie";
4793 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
4794 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
4795 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
4796 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4797 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
4798 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4799 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4800
4801 #address-cells = <3>;
4802 #size-cells = <2>;
4803 device_type = "pci";
4804 num-lanes = <4>;
4805 num-viewport = <8>;
4806 linux,pci-domain = <4>;
4807
4808 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
4809 clock-names = "core";
4810
4811 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
4812 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
4813 reset-names = "apb", "core";
4814
4815 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4816 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4817 interrupt-names = "intr", "msi";
4818
4819 #interrupt-cells = <1>;
4820 interrupt-map-mask = <0 0 0 0>;
4821 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4822
4823 nvidia,bpmp = <&bpmp 4>;
4824
4825 nvidia,aspm-cmrt-us = <60>;
4826 nvidia,aspm-pwr-on-t-us = <20>;
4827 nvidia,aspm-l0s-entrance-latency-us = <3>;
4828
4829 bus-range = <0x0 0xff>;
4830
4831 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4832 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4833 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4834
4835 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
4836 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
4837 interconnect-names = "dma-mem", "write";
4838 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
4839 iommu-map-mask = <0x0>;
4840 dma-coherent;
4841
4842 status = "disabled";
4843 };
4844
4845 pcie-ep@14160000 {
4846 compatible = "nvidia,tegra234-pcie-ep";
4847 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
4848 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
4849 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
4850 0x00 0x36080000 0x0 0x00040000 /* DBI space (256K) */
4851 0x21 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
4852 reg-names = "appl", "atu_dma", "dbi", "addr_space";
4853 num-lanes = <4>;
4854 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
4855 clock-names = "core";
4856 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
4857 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
4858 reset-names = "apb", "core";
4859
4860 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
4861 interrupt-names = "intr";
4862 nvidia,bpmp = <&bpmp 4>;
4863 nvidia,enable-ext-refclk;
4864 nvidia,aspm-cmrt-us = <60>;
4865 nvidia,aspm-pwr-on-t-us = <20>;
4866 nvidia,aspm-l0s-entrance-latency-us = <3>;
4867
4868 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
4869 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
4870 interconnect-names = "dma-mem", "write";
4871 iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
4872 dma-coherent;
4873 status = "disabled";
4874 };
4875
4876 pcie@14180000 {
4877 compatible = "nvidia,tegra234-pcie";
4878 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
4879 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
4880 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
4881 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4882 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
4883 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4884 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4885
4886 #address-cells = <3>;
4887 #size-cells = <2>;
4888 device_type = "pci";
4889 num-lanes = <4>;
4890 num-viewport = <8>;
4891 linux,pci-domain = <0>;
4892
4893 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
4894 clock-names = "core";
4895
4896 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
4897 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
4898 reset-names = "apb", "core";
4899
4900 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4901 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4902 interrupt-names = "intr", "msi";
4903
4904 #interrupt-cells = <1>;
4905 interrupt-map-mask = <0 0 0 0>;
4906 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4907
4908 nvidia,bpmp = <&bpmp 0>;
4909
4910 nvidia,aspm-cmrt-us = <60>;
4911 nvidia,aspm-pwr-on-t-us = <20>;
4912 nvidia,aspm-l0s-entrance-latency-us = <3>;
4913
4914 bus-range = <0x0 0xff>;
4915
4916 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4917 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4918 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4919
4920 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
4921 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
4922 interconnect-names = "dma-mem", "write";
4923 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
4924 iommu-map-mask = <0x0>;
4925 dma-coherent;
4926
4927 status = "disabled";
4928 };
4929
4930 pcie@141a0000 {
4931 compatible = "nvidia,tegra234-pcie";
4932 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
4933 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
4934 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
4935 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4936 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4937 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4938 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4939
4940 #address-cells = <3>;
4941 #size-cells = <2>;
4942 device_type = "pci";
4943 num-lanes = <8>;
4944 num-viewport = <8>;
4945 linux,pci-domain = <5>;
4946
4947 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
4948 clock-names = "core";
4949
4950 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
4951 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
4952 reset-names = "apb", "core";
4953
4954 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4955 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4956 interrupt-names = "intr", "msi";
4957
4958 #interrupt-cells = <1>;
4959 interrupt-map-mask = <0 0 0 0>;
4960 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4961
4962 nvidia,bpmp = <&bpmp 5>;
4963
4964 nvidia,aspm-cmrt-us = <60>;
4965 nvidia,aspm-pwr-on-t-us = <20>;
4966 nvidia,aspm-l0s-entrance-latency-us = <3>;
4967
4968 bus-range = <0x0 0xff>;
4969
4970 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
4971 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4972 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4973
4974 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
4975 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
4976 interconnect-names = "dma-mem", "write";
4977 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
4978 iommu-map-mask = <0x0>;
4979 dma-coherent;
4980
4981 status = "disabled";
4982 };
4983
4984 pcie-ep@141a0000 {
4985 compatible = "nvidia,tegra234-pcie-ep";
4986 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
4987 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
4988 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4989 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4990 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
4991 reg-names = "appl", "atu_dma", "dbi", "addr_space";
4992
4993 num-lanes = <8>;
4994
4995 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
4996 clock-names = "core";
4997
4998 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
4999 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
5000 reset-names = "apb", "core";
5001
5002 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
5003 interrupt-names = "intr";
5004
5005 nvidia,bpmp = <&bpmp 5>;
5006
5007 nvidia,enable-ext-refclk;
5008 nvidia,aspm-cmrt-us = <60>;
5009 nvidia,aspm-pwr-on-t-us = <20>;
5010 nvidia,aspm-l0s-entrance-latency-us = <3>;
5011
5012 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
5013 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
5014 interconnect-names = "dma-mem", "write";
5015 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
5016 iommu-map-mask = <0x0>;
5017 dma-coherent;
5018
5019 status = "disabled";
5020 };
5021
5022 pcie@141c0000 {
5023 compatible = "nvidia,tegra234-pcie";
5024 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
5025 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
5026 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
5027 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5028 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
5029 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
5030 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
5031
5032 #address-cells = <3>;
5033 #size-cells = <2>;
5034 device_type = "pci";
5035 num-lanes = <4>;
5036 num-viewport = <8>;
5037 linux,pci-domain = <6>;
5038
5039 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
5040 clock-names = "core";
5041
5042 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
5043 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
5044 reset-names = "apb", "core";
5045
5046 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
5047 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
5048 interrupt-names = "intr", "msi";
5049
5050 #interrupt-cells = <1>;
5051 interrupt-map-mask = <0 0 0 0>;
5052 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
5053
5054 nvidia,bpmp = <&bpmp 6>;
5055
5056 nvidia,aspm-cmrt-us = <60>;
5057 nvidia,aspm-pwr-on-t-us = <20>;
5058 nvidia,aspm-l0s-entrance-latency-us = <3>;
5059
5060 bus-range = <0x0 0xff>;
5061
5062 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
5063 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5064 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5065
5066 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
5067 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
5068 interconnect-names = "dma-mem", "write";
5069 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5070 iommu-map-mask = <0x0>;
5071 dma-coherent;
5072
5073 status = "disabled";
5074 };
5075
5076 pcie-ep@141c0000 {
5077 compatible = "nvidia,tegra234-pcie-ep";
5078 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
5079 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
5080 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5081 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
5082 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
5083 reg-names = "appl", "atu_dma", "dbi", "addr_space";
5084
5085 num-lanes = <4>;
5086
5087 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
5088 clock-names = "core";
5089
5090 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
5091 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
5092 reset-names = "apb", "core";
5093
5094 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
5095 interrupt-names = "intr";
5096
5097 nvidia,bpmp = <&bpmp 6>;
5098
5099 nvidia,enable-ext-refclk;
5100 nvidia,aspm-cmrt-us = <60>;
5101 nvidia,aspm-pwr-on-t-us = <20>;
5102 nvidia,aspm-l0s-entrance-latency-us = <3>;
5103
5104 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
5105 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
5106 interconnect-names = "dma-mem", "write";
5107 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5108 iommu-map-mask = <0x0>;
5109 dma-coherent;
5110
5111 status = "disabled";
5112 };
5113
5114 pcie@141e0000 {
5115 compatible = "nvidia,tegra234-pcie";
5116 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5117 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
5118 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
5119 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5120 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
5121 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
5122 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
5123
5124 #address-cells = <3>;
5125 #size-cells = <2>;
5126 device_type = "pci";
5127 num-lanes = <8>;
5128 num-viewport = <8>;
5129 linux,pci-domain = <7>;
5130
5131 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
5132 clock-names = "core";
5133
5134 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
5135 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
5136 reset-names = "apb", "core";
5137
5138 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
5139 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
5140 interrupt-names = "intr", "msi";
5141
5142 #interrupt-cells = <1>;
5143 interrupt-map-mask = <0 0 0 0>;
5144 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
5145
5146 nvidia,bpmp = <&bpmp 7>;
5147
5148 nvidia,aspm-cmrt-us = <60>;
5149 nvidia,aspm-pwr-on-t-us = <20>;
5150 nvidia,aspm-l0s-entrance-latency-us = <3>;
5151
5152 bus-range = <0x0 0xff>;
5153
5154 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
5155 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5156 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5157
5158 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
5159 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
5160 interconnect-names = "dma-mem", "write";
5161 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5162 iommu-map-mask = <0x0>;
5163 dma-coherent;
5164
5165 status = "disabled";
5166 };
5167
5168 pcie-ep@141e0000 {
5169 compatible = "nvidia,tegra234-pcie-ep";
5170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5171 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
5172 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5173 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
5174 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
5175 reg-names = "appl", "atu_dma", "dbi", "addr_space";
5176
5177 num-lanes = <8>;
5178
5179 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
5180 clock-names = "core";
5181
5182 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
5183 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
5184 reset-names = "apb", "core";
5185
5186 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
5187 interrupt-names = "intr";
5188
5189 nvidia,bpmp = <&bpmp 7>;
5190
5191 nvidia,enable-ext-refclk;
5192 nvidia,aspm-cmrt-us = <60>;
5193 nvidia,aspm-pwr-on-t-us = <20>;
5194 nvidia,aspm-l0s-entrance-latency-us = <3>;
5195
5196 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
5197 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
5198 interconnect-names = "dma-mem", "write";
5199 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5200 iommu-map-mask = <0x0>;
5201 dma-coherent;
5202
5203 status = "disabled";
5204 };
5205 };
5206
5207 sram@40000000 {
5208 compatible = "nvidia,tegra234-sysram", "mmio-sram";
5209 reg = <0x0 0x40000000 0x0 0x80000>;
5210
5211 #address-cells = <1>;
5212 #size-cells = <1>;
5213 ranges = <0x0 0x0 0x40000000 0x80000>;
5214
5215 no-memory-wc;
5216
5217 cpu_bpmp_tx: sram@70000 {
5218 reg = <0x70000 0x1000>;
5219 label = "cpu-bpmp-tx";
5220 pool;
5221 };
5222
5223 cpu_bpmp_rx: sram@71000 {
5224 reg = <0x71000 0x1000>;
5225 label = "cpu-bpmp-rx";
5226 pool;
5227 };
5228 };
5229
5230 bpmp: bpmp {
5231 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
5232 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
5233 TEGRA_HSP_DB_MASTER_BPMP>;
5234 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
5235 #clock-cells = <1>;
5236 #reset-cells = <1>;
5237 #power-domain-cells = <1>;
5238 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
5239 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
5240 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
5241 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
5242 interconnect-names = "read", "write", "dma-mem", "dma-write";
5243 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
5244
5245 bpmp_i2c: i2c {
5246 compatible = "nvidia,tegra186-bpmp-i2c";
5247 nvidia,bpmp-bus-id = <5>;
5248 #address-cells = <1>;
5249 #size-cells = <0>;
5250 };
5251
5252 bpmp_thermal: thermal {
5253 compatible = "nvidia,tegra186-bpmp-thermal";
5254 #thermal-sensor-cells = <1>;
5255 };
5256 };
5257
5258 cpus {
5259 #address-cells = <1>;
5260 #size-cells = <0>;
5261
5262 cpu0_0: cpu@0 {
5263 compatible = "arm,cortex-a78";
5264 device_type = "cpu";
5265 reg = <0x00000>;
5266
5267 enable-method = "psci";
5268
5269 operating-points-v2 = <&cl0_opp_tbl>;
5270 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5271
5272 i-cache-size = <65536>;
5273 i-cache-line-size = <64>;
5274 i-cache-sets = <256>;
5275 d-cache-size = <65536>;
5276 d-cache-line-size = <64>;
5277 d-cache-sets = <256>;
5278 next-level-cache = <&l2c0_0>;
5279 };
5280
5281 cpu0_1: cpu@100 {
5282 compatible = "arm,cortex-a78";
5283 device_type = "cpu";
5284 reg = <0x00100>;
5285
5286 enable-method = "psci";
5287
5288 operating-points-v2 = <&cl0_opp_tbl>;
5289 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5290
5291 i-cache-size = <65536>;
5292 i-cache-line-size = <64>;
5293 i-cache-sets = <256>;
5294 d-cache-size = <65536>;
5295 d-cache-line-size = <64>;
5296 d-cache-sets = <256>;
5297 next-level-cache = <&l2c0_1>;
5298 };
5299
5300 cpu0_2: cpu@200 {
5301 compatible = "arm,cortex-a78";
5302 device_type = "cpu";
5303 reg = <0x00200>;
5304
5305 enable-method = "psci";
5306
5307 operating-points-v2 = <&cl0_opp_tbl>;
5308 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5309
5310 i-cache-size = <65536>;
5311 i-cache-line-size = <64>;
5312 i-cache-sets = <256>;
5313 d-cache-size = <65536>;
5314 d-cache-line-size = <64>;
5315 d-cache-sets = <256>;
5316 next-level-cache = <&l2c0_2>;
5317 };
5318
5319 cpu0_3: cpu@300 {
5320 compatible = "arm,cortex-a78";
5321 device_type = "cpu";
5322 reg = <0x00300>;
5323
5324 enable-method = "psci";
5325
5326 operating-points-v2 = <&cl0_opp_tbl>;
5327 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5328
5329 i-cache-size = <65536>;
5330 i-cache-line-size = <64>;
5331 i-cache-sets = <256>;
5332 d-cache-size = <65536>;
5333 d-cache-line-size = <64>;
5334 d-cache-sets = <256>;
5335 next-level-cache = <&l2c0_3>;
5336 };
5337
5338 cpu1_0: cpu@10000 {
5339 compatible = "arm,cortex-a78";
5340 device_type = "cpu";
5341 reg = <0x10000>;
5342
5343 enable-method = "psci";
5344
5345 operating-points-v2 = <&cl1_opp_tbl>;
5346 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5347
5348 i-cache-size = <65536>;
5349 i-cache-line-size = <64>;
5350 i-cache-sets = <256>;
5351 d-cache-size = <65536>;
5352 d-cache-line-size = <64>;
5353 d-cache-sets = <256>;
5354 next-level-cache = <&l2c1_0>;
5355 };
5356
5357 cpu1_1: cpu@10100 {
5358 compatible = "arm,cortex-a78";
5359 device_type = "cpu";
5360 reg = <0x10100>;
5361
5362 enable-method = "psci";
5363
5364 operating-points-v2 = <&cl1_opp_tbl>;
5365 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5366
5367 i-cache-size = <65536>;
5368 i-cache-line-size = <64>;
5369 i-cache-sets = <256>;
5370 d-cache-size = <65536>;
5371 d-cache-line-size = <64>;
5372 d-cache-sets = <256>;
5373 next-level-cache = <&l2c1_1>;
5374 };
5375
5376 cpu1_2: cpu@10200 {
5377 compatible = "arm,cortex-a78";
5378 device_type = "cpu";
5379 reg = <0x10200>;
5380
5381 enable-method = "psci";
5382
5383 operating-points-v2 = <&cl1_opp_tbl>;
5384 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5385
5386 i-cache-size = <65536>;
5387 i-cache-line-size = <64>;
5388 i-cache-sets = <256>;
5389 d-cache-size = <65536>;
5390 d-cache-line-size = <64>;
5391 d-cache-sets = <256>;
5392 next-level-cache = <&l2c1_2>;
5393 };
5394
5395 cpu1_3: cpu@10300 {
5396 compatible = "arm,cortex-a78";
5397 device_type = "cpu";
5398 reg = <0x10300>;
5399
5400 enable-method = "psci";
5401
5402 operating-points-v2 = <&cl1_opp_tbl>;
5403 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5404
5405 i-cache-size = <65536>;
5406 i-cache-line-size = <64>;
5407 i-cache-sets = <256>;
5408 d-cache-size = <65536>;
5409 d-cache-line-size = <64>;
5410 d-cache-sets = <256>;
5411 next-level-cache = <&l2c1_3>;
5412 };
5413
5414 cpu2_0: cpu@20000 {
5415 compatible = "arm,cortex-a78";
5416 device_type = "cpu";
5417 reg = <0x20000>;
5418
5419 enable-method = "psci";
5420
5421 operating-points-v2 = <&cl2_opp_tbl>;
5422 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5423
5424 i-cache-size = <65536>;
5425 i-cache-line-size = <64>;
5426 i-cache-sets = <256>;
5427 d-cache-size = <65536>;
5428 d-cache-line-size = <64>;
5429 d-cache-sets = <256>;
5430 next-level-cache = <&l2c2_0>;
5431 };
5432
5433 cpu2_1: cpu@20100 {
5434 compatible = "arm,cortex-a78";
5435 device_type = "cpu";
5436 reg = <0x20100>;
5437
5438 enable-method = "psci";
5439
5440 operating-points-v2 = <&cl2_opp_tbl>;
5441 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5442
5443 i-cache-size = <65536>;
5444 i-cache-line-size = <64>;
5445 i-cache-sets = <256>;
5446 d-cache-size = <65536>;
5447 d-cache-line-size = <64>;
5448 d-cache-sets = <256>;
5449 next-level-cache = <&l2c2_1>;
5450 };
5451
5452 cpu2_2: cpu@20200 {
5453 compatible = "arm,cortex-a78";
5454 device_type = "cpu";
5455 reg = <0x20200>;
5456
5457 enable-method = "psci";
5458
5459 operating-points-v2 = <&cl2_opp_tbl>;
5460 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5461
5462 i-cache-size = <65536>;
5463 i-cache-line-size = <64>;
5464 i-cache-sets = <256>;
5465 d-cache-size = <65536>;
5466 d-cache-line-size = <64>;
5467 d-cache-sets = <256>;
5468 next-level-cache = <&l2c2_2>;
5469 };
5470
5471 cpu2_3: cpu@20300 {
5472 compatible = "arm,cortex-a78";
5473 device_type = "cpu";
5474 reg = <0x20300>;
5475
5476 enable-method = "psci";
5477
5478 operating-points-v2 = <&cl2_opp_tbl>;
5479 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5480
5481 i-cache-size = <65536>;
5482 i-cache-line-size = <64>;
5483 i-cache-sets = <256>;
5484 d-cache-size = <65536>;
5485 d-cache-line-size = <64>;
5486 d-cache-sets = <256>;
5487 next-level-cache = <&l2c2_3>;
5488 };
5489
5490 cpu-map {
5491 cluster0 {
5492 core0 {
5493 cpu = <&cpu0_0>;
5494 };
5495
5496 core1 {
5497 cpu = <&cpu0_1>;
5498 };
5499
5500 core2 {
5501 cpu = <&cpu0_2>;
5502 };
5503
5504 core3 {
5505 cpu = <&cpu0_3>;
5506 };
5507 };
5508
5509 cluster1 {
5510 core0 {
5511 cpu = <&cpu1_0>;
5512 };
5513
5514 core1 {
5515 cpu = <&cpu1_1>;
5516 };
5517
5518 core2 {
5519 cpu = <&cpu1_2>;
5520 };
5521
5522 core3 {
5523 cpu = <&cpu1_3>;
5524 };
5525 };
5526
5527 cluster2 {
5528 core0 {
5529 cpu = <&cpu2_0>;
5530 };
5531
5532 core1 {
5533 cpu = <&cpu2_1>;
5534 };
5535
5536 core2 {
5537 cpu = <&cpu2_2>;
5538 };
5539
5540 core3 {
5541 cpu = <&cpu2_3>;
5542 };
5543 };
5544 };
5545
5546 l2c0_0: l2-cache00 {
5547 compatible = "cache";
5548 cache-size = <262144>;
5549 cache-line-size = <64>;
5550 cache-sets = <512>;
5551 cache-unified;
5552 cache-level = <2>;
5553 next-level-cache = <&l3c0>;
5554 };
5555
5556 l2c0_1: l2-cache01 {
5557 compatible = "cache";
5558 cache-size = <262144>;
5559 cache-line-size = <64>;
5560 cache-sets = <512>;
5561 cache-unified;
5562 cache-level = <2>;
5563 next-level-cache = <&l3c0>;
5564 };
5565
5566 l2c0_2: l2-cache02 {
5567 compatible = "cache";
5568 cache-size = <262144>;
5569 cache-line-size = <64>;
5570 cache-sets = <512>;
5571 cache-unified;
5572 cache-level = <2>;
5573 next-level-cache = <&l3c0>;
5574 };
5575
5576 l2c0_3: l2-cache03 {
5577 compatible = "cache";
5578 cache-size = <262144>;
5579 cache-line-size = <64>;
5580 cache-sets = <512>;
5581 cache-unified;
5582 cache-level = <2>;
5583 next-level-cache = <&l3c0>;
5584 };
5585
5586 l2c1_0: l2-cache10 {
5587 compatible = "cache";
5588 cache-size = <262144>;
5589 cache-line-size = <64>;
5590 cache-sets = <512>;
5591 cache-unified;
5592 cache-level = <2>;
5593 next-level-cache = <&l3c1>;
5594 };
5595
5596 l2c1_1: l2-cache11 {
5597 compatible = "cache";
5598 cache-size = <262144>;
5599 cache-line-size = <64>;
5600 cache-sets = <512>;
5601 cache-unified;
5602 cache-level = <2>;
5603 next-level-cache = <&l3c1>;
5604 };
5605
5606 l2c1_2: l2-cache12 {
5607 compatible = "cache";
5608 cache-size = <262144>;
5609 cache-line-size = <64>;
5610 cache-sets = <512>;
5611 cache-unified;
5612 cache-level = <2>;
5613 next-level-cache = <&l3c1>;
5614 };
5615
5616 l2c1_3: l2-cache13 {
5617 compatible = "cache";
5618 cache-size = <262144>;
5619 cache-line-size = <64>;
5620 cache-sets = <512>;
5621 cache-unified;
5622 cache-level = <2>;
5623 next-level-cache = <&l3c1>;
5624 };
5625
5626 l2c2_0: l2-cache20 {
5627 compatible = "cache";
5628 cache-size = <262144>;
5629 cache-line-size = <64>;
5630 cache-sets = <512>;
5631 cache-unified;
5632 cache-level = <2>;
5633 next-level-cache = <&l3c2>;
5634 };
5635
5636 l2c2_1: l2-cache21 {
5637 compatible = "cache";
5638 cache-size = <262144>;
5639 cache-line-size = <64>;
5640 cache-sets = <512>;
5641 cache-unified;
5642 cache-level = <2>;
5643 next-level-cache = <&l3c2>;
5644 };
5645
5646 l2c2_2: l2-cache22 {
5647 compatible = "cache";
5648 cache-size = <262144>;
5649 cache-line-size = <64>;
5650 cache-sets = <512>;
5651 cache-unified;
5652 cache-level = <2>;
5653 next-level-cache = <&l3c2>;
5654 };
5655
5656 l2c2_3: l2-cache23 {
5657 compatible = "cache";
5658 cache-size = <262144>;
5659 cache-line-size = <64>;
5660 cache-sets = <512>;
5661 cache-unified;
5662 cache-level = <2>;
5663 next-level-cache = <&l3c2>;
5664 };
5665
5666 l3c0: l3-cache0 {
5667 compatible = "cache";
5668 cache-unified;
5669 cache-size = <2097152>;
5670 cache-line-size = <64>;
5671 cache-sets = <2048>;
5672 cache-level = <3>;
5673 };
5674
5675 l3c1: l3-cache1 {
5676 compatible = "cache";
5677 cache-unified;
5678 cache-size = <2097152>;
5679 cache-line-size = <64>;
5680 cache-sets = <2048>;
5681 cache-level = <3>;
5682 };
5683
5684 l3c2: l3-cache2 {
5685 compatible = "cache";
5686 cache-unified;
5687 cache-size = <2097152>;
5688 cache-line-size = <64>;
5689 cache-sets = <2048>;
5690 cache-level = <3>;
5691 };
5692 };
5693
5694 dsu-pmu0 {
5695 compatible = "arm,dsu-pmu";
5696 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
5697 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>;
5698 };
5699
5700 dsu-pmu1 {
5701 compatible = "arm,dsu-pmu";
5702 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
5703 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>;
5704 };
5705
5706 dsu-pmu2 {
5707 compatible = "arm,dsu-pmu";
5708 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
5709 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>;
5710 };
5711
5712 pmu {
5713 compatible = "arm,cortex-a78-pmu";
5714 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
5715 status = "okay";
5716 };
5717
5718 psci {
5719 compatible = "arm,psci-1.0";
5720 status = "okay";
5721 method = "smc";
5722 };
5723
5724 tcu: serial {
5725 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
5726 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
5727 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
5728 mbox-names = "rx", "tx";
5729 status = "disabled";
5730 };
5731
5732 sound {
5733 status = "disabled";
5734
5735 clocks = <&bpmp TEGRA234_CLK_PLLA>,
5736 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5737 clock-names = "pll_a", "plla_out0";
5738 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
5739 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
5740 <&bpmp TEGRA234_CLK_AUD_MCLK>;
5741 assigned-clock-parents = <0>,
5742 <&bpmp TEGRA234_CLK_PLLA>,
5743 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5744 };
5745
5746 thermal-zones {
5747 cpu-thermal {
5748 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
5749 status = "disabled";
5750 };
5751
5752 gpu-thermal {
5753 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
5754 status = "disabled";
5755 };
5756
5757 cv0-thermal {
5758 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
5759 status = "disabled";
5760 };
5761
5762 cv1-thermal {
5763 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
5764 status = "disabled";
5765 };
5766
5767 cv2-thermal {
5768 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
5769 status = "disabled";
5770 };
5771
5772 soc0-thermal {
5773 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
5774 status = "disabled";
5775 };
5776
5777 soc1-thermal {
5778 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
5779 status = "disabled";
5780 };
5781
5782 soc2-thermal {
5783 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
5784 status = "disabled";
5785 };
5786
5787 tj-thermal {
5788 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
5789 status = "disabled";
5790 };
5791 };
5792
5793 timer {
5794 compatible = "arm,armv8-timer";
5795 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
5796 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
5797 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
5798 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
5799 interrupt-parent = <&gic>;
5800 always-on;
5801 };
5802
5803 cl0_opp_tbl: opp-table-cluster0 {
5804 compatible = "operating-points-v2";
5805 opp-shared;
5806
5807 cl0_ch1_opp1: opp-115200000 {
5808 opp-hz = /bits/ 64 <115200000>;
5809 opp-peak-kBps = <816000>;
5810 };
5811
5812 cl0_ch1_opp2: opp-192000000 {
5813 opp-hz = /bits/ 64 <192000000>;
5814 opp-peak-kBps = <816000>;
5815 };
5816
5817 cl0_ch1_opp3: opp-268800000 {
5818 opp-hz = /bits/ 64 <268800000>;
5819 opp-peak-kBps = <816000>;
5820 };
5821
5822 cl0_ch1_opp4: opp-345600000 {
5823 opp-hz = /bits/ 64 <345600000>;
5824 opp-peak-kBps = <816000>;
5825 };
5826
5827 cl0_ch1_opp5: opp-422400000 {
5828 opp-hz = /bits/ 64 <422400000>;
5829 opp-peak-kBps = <816000>;
5830 };
5831
5832 cl0_ch1_opp6: opp-499200000 {
5833 opp-hz = /bits/ 64 <499200000>;
5834 opp-peak-kBps = <816000>;
5835 };
5836
5837 cl0_ch1_opp7: opp-576000000 {
5838 opp-hz = /bits/ 64 <576000000>;
5839 opp-peak-kBps = <816000>;
5840 };
5841
5842 cl0_ch1_opp8: opp-652800000 {
5843 opp-hz = /bits/ 64 <652800000>;
5844 opp-peak-kBps = <816000>;
5845 };
5846
5847 cl0_ch1_opp9: opp-729600000 {
5848 opp-hz = /bits/ 64 <729600000>;
5849 opp-peak-kBps = <816000>;
5850 };
5851
5852 cl0_ch1_opp10: opp-806400000 {
5853 opp-hz = /bits/ 64 <806400000>;
5854 opp-peak-kBps = <816000>;
5855 };
5856
5857 cl0_ch1_opp11: opp-883200000 {
5858 opp-hz = /bits/ 64 <883200000>;
5859 opp-peak-kBps = <816000>;
5860 };
5861
5862 cl0_ch1_opp12: opp-960000000 {
5863 opp-hz = /bits/ 64 <960000000>;
5864 opp-peak-kBps = <816000>;
5865 };
5866
5867 cl0_ch1_opp13: opp-1036800000 {
5868 opp-hz = /bits/ 64 <1036800000>;
5869 opp-peak-kBps = <816000>;
5870 };
5871
5872 cl0_ch1_opp14: opp-1113600000 {
5873 opp-hz = /bits/ 64 <1113600000>;
5874 opp-peak-kBps = <1632000>;
5875 };
5876
5877 cl0_ch1_opp15: opp-1190400000 {
5878 opp-hz = /bits/ 64 <1190400000>;
5879 opp-peak-kBps = <1632000>;
5880 };
5881
5882 cl0_ch1_opp16: opp-1267200000 {
5883 opp-hz = /bits/ 64 <1267200000>;
5884 opp-peak-kBps = <1632000>;
5885 };
5886
5887 cl0_ch1_opp17: opp-1344000000 {
5888 opp-hz = /bits/ 64 <1344000000>;
5889 opp-peak-kBps = <1632000>;
5890 };
5891
5892 cl0_ch1_opp18: opp-1420800000 {
5893 opp-hz = /bits/ 64 <1420800000>;
5894 opp-peak-kBps = <1632000>;
5895 };
5896
5897 cl0_ch1_opp19: opp-1497600000 {
5898 opp-hz = /bits/ 64 <1497600000>;
5899 opp-peak-kBps = <3200000>;
5900 };
5901
5902 cl0_ch1_opp20: opp-1574400000 {
5903 opp-hz = /bits/ 64 <1574400000>;
5904 opp-peak-kBps = <3200000>;
5905 };
5906
5907 cl0_ch1_opp21: opp-1651200000 {
5908 opp-hz = /bits/ 64 <1651200000>;
5909 opp-peak-kBps = <3200000>;
5910 };
5911
5912 cl0_ch1_opp22: opp-1728000000 {
5913 opp-hz = /bits/ 64 <1728000000>;
5914 opp-peak-kBps = <3200000>;
5915 };
5916
5917 cl0_ch1_opp23: opp-1804800000 {
5918 opp-hz = /bits/ 64 <1804800000>;
5919 opp-peak-kBps = <3200000>;
5920 };
5921
5922 cl0_ch1_opp24: opp-1881600000 {
5923 opp-hz = /bits/ 64 <1881600000>;
5924 opp-peak-kBps = <3200000>;
5925 };
5926
5927 cl0_ch1_opp25: opp-1958400000 {
5928 opp-hz = /bits/ 64 <1958400000>;
5929 opp-peak-kBps = <3200000>;
5930 };
5931
5932 cl0_ch1_opp26: opp-2035200000 {
5933 opp-hz = /bits/ 64 <2035200000>;
5934 opp-peak-kBps = <3200000>;
5935 };
5936
5937 cl0_ch1_opp27: opp-2112000000 {
5938 opp-hz = /bits/ 64 <2112000000>;
5939 opp-peak-kBps = <6400000>;
5940 };
5941
5942 cl0_ch1_opp28: opp-2188800000 {
5943 opp-hz = /bits/ 64 <2188800000>;
5944 opp-peak-kBps = <6400000>;
5945 };
5946
5947 cl0_ch1_opp29: opp-2201600000 {
5948 opp-hz = /bits/ 64 <2201600000>;
5949 opp-peak-kBps = <6400000>;
5950 };
5951 };
5952
5953 cl1_opp_tbl: opp-table-cluster1 {
5954 compatible = "operating-points-v2";
5955 opp-shared;
5956
5957 cl1_ch1_opp1: opp-115200000 {
5958 opp-hz = /bits/ 64 <115200000>;
5959 opp-peak-kBps = <816000>;
5960 };
5961
5962 cl1_ch1_opp2: opp-192000000 {
5963 opp-hz = /bits/ 64 <192000000>;
5964 opp-peak-kBps = <816000>;
5965 };
5966
5967 cl1_ch1_opp3: opp-268800000 {
5968 opp-hz = /bits/ 64 <268800000>;
5969 opp-peak-kBps = <816000>;
5970 };
5971
5972 cl1_ch1_opp4: opp-345600000 {
5973 opp-hz = /bits/ 64 <345600000>;
5974 opp-peak-kBps = <816000>;
5975 };
5976
5977 cl1_ch1_opp5: opp-422400000 {
5978 opp-hz = /bits/ 64 <422400000>;
5979 opp-peak-kBps = <816000>;
5980 };
5981
5982 cl1_ch1_opp6: opp-499200000 {
5983 opp-hz = /bits/ 64 <499200000>;
5984 opp-peak-kBps = <816000>;
5985 };
5986
5987 cl1_ch1_opp7: opp-576000000 {
5988 opp-hz = /bits/ 64 <576000000>;
5989 opp-peak-kBps = <816000>;
5990 };
5991
5992 cl1_ch1_opp8: opp-652800000 {
5993 opp-hz = /bits/ 64 <652800000>;
5994 opp-peak-kBps = <816000>;
5995 };
5996
5997 cl1_ch1_opp9: opp-729600000 {
5998 opp-hz = /bits/ 64 <729600000>;
5999 opp-peak-kBps = <816000>;
6000 };
6001
6002 cl1_ch1_opp10: opp-806400000 {
6003 opp-hz = /bits/ 64 <806400000>;
6004 opp-peak-kBps = <816000>;
6005 };
6006
6007 cl1_ch1_opp11: opp-883200000 {
6008 opp-hz = /bits/ 64 <883200000>;
6009 opp-peak-kBps = <816000>;
6010 };
6011
6012 cl1_ch1_opp12: opp-960000000 {
6013 opp-hz = /bits/ 64 <960000000>;
6014 opp-peak-kBps = <816000>;
6015 };
6016
6017 cl1_ch1_opp13: opp-1036800000 {
6018 opp-hz = /bits/ 64 <1036800000>;
6019 opp-peak-kBps = <816000>;
6020 };
6021
6022 cl1_ch1_opp14: opp-1113600000 {
6023 opp-hz = /bits/ 64 <1113600000>;
6024 opp-peak-kBps = <1632000>;
6025 };
6026
6027 cl1_ch1_opp15: opp-1190400000 {
6028 opp-hz = /bits/ 64 <1190400000>;
6029 opp-peak-kBps = <1632000>;
6030 };
6031
6032 cl1_ch1_opp16: opp-1267200000 {
6033 opp-hz = /bits/ 64 <1267200000>;
6034 opp-peak-kBps = <1632000>;
6035 };
6036
6037 cl1_ch1_opp17: opp-1344000000 {
6038 opp-hz = /bits/ 64 <1344000000>;
6039 opp-peak-kBps = <1632000>;
6040 };
6041
6042 cl1_ch1_opp18: opp-1420800000 {
6043 opp-hz = /bits/ 64 <1420800000>;
6044 opp-peak-kBps = <1632000>;
6045 };
6046
6047 cl1_ch1_opp19: opp-1497600000 {
6048 opp-hz = /bits/ 64 <1497600000>;
6049 opp-peak-kBps = <3200000>;
6050 };
6051
6052 cl1_ch1_opp20: opp-1574400000 {
6053 opp-hz = /bits/ 64 <1574400000>;
6054 opp-peak-kBps = <3200000>;
6055 };
6056
6057 cl1_ch1_opp21: opp-1651200000 {
6058 opp-hz = /bits/ 64 <1651200000>;
6059 opp-peak-kBps = <3200000>;
6060 };
6061
6062 cl1_ch1_opp22: opp-1728000000 {
6063 opp-hz = /bits/ 64 <1728000000>;
6064 opp-peak-kBps = <3200000>;
6065 };
6066
6067 cl1_ch1_opp23: opp-1804800000 {
6068 opp-hz = /bits/ 64 <1804800000>;
6069 opp-peak-kBps = <3200000>;
6070 };
6071
6072 cl1_ch1_opp24: opp-1881600000 {
6073 opp-hz = /bits/ 64 <1881600000>;
6074 opp-peak-kBps = <3200000>;
6075 };
6076
6077 cl1_ch1_opp25: opp-1958400000 {
6078 opp-hz = /bits/ 64 <1958400000>;
6079 opp-peak-kBps = <3200000>;
6080 };
6081
6082 cl1_ch1_opp26: opp-2035200000 {
6083 opp-hz = /bits/ 64 <2035200000>;
6084 opp-peak-kBps = <3200000>;
6085 };
6086
6087 cl1_ch1_opp27: opp-2112000000 {
6088 opp-hz = /bits/ 64 <2112000000>;
6089 opp-peak-kBps = <6400000>;
6090 };
6091
6092 cl1_ch1_opp28: opp-2188800000 {
6093 opp-hz = /bits/ 64 <2188800000>;
6094 opp-peak-kBps = <6400000>;
6095 };
6096
6097 cl1_ch1_opp29: opp-2201600000 {
6098 opp-hz = /bits/ 64 <2201600000>;
6099 opp-peak-kBps = <6400000>;
6100 };
6101 };
6102
6103 cl2_opp_tbl: opp-table-cluster2 {
6104 compatible = "operating-points-v2";
6105 opp-shared;
6106
6107 cl2_ch1_opp1: opp-115200000 {
6108 opp-hz = /bits/ 64 <115200000>;
6109 opp-peak-kBps = <816000>;
6110 };
6111
6112 cl2_ch1_opp2: opp-192000000 {
6113 opp-hz = /bits/ 64 <192000000>;
6114 opp-peak-kBps = <816000>;
6115 };
6116
6117 cl2_ch1_opp3: opp-268800000 {
6118 opp-hz = /bits/ 64 <268800000>;
6119 opp-peak-kBps = <816000>;
6120 };
6121
6122 cl2_ch1_opp4: opp-345600000 {
6123 opp-hz = /bits/ 64 <345600000>;
6124 opp-peak-kBps = <816000>;
6125 };
6126
6127 cl2_ch1_opp5: opp-422400000 {
6128 opp-hz = /bits/ 64 <422400000>;
6129 opp-peak-kBps = <816000>;
6130 };
6131
6132 cl2_ch1_opp6: opp-499200000 {
6133 opp-hz = /bits/ 64 <499200000>;
6134 opp-peak-kBps = <816000>;
6135 };
6136
6137 cl2_ch1_opp7: opp-576000000 {
6138 opp-hz = /bits/ 64 <576000000>;
6139 opp-peak-kBps = <816000>;
6140 };
6141
6142 cl2_ch1_opp8: opp-652800000 {
6143 opp-hz = /bits/ 64 <652800000>;
6144 opp-peak-kBps = <816000>;
6145 };
6146
6147 cl2_ch1_opp9: opp-729600000 {
6148 opp-hz = /bits/ 64 <729600000>;
6149 opp-peak-kBps = <816000>;
6150 };
6151
6152 cl2_ch1_opp10: opp-806400000 {
6153 opp-hz = /bits/ 64 <806400000>;
6154 opp-peak-kBps = <816000>;
6155 };
6156
6157 cl2_ch1_opp11: opp-883200000 {
6158 opp-hz = /bits/ 64 <883200000>;
6159 opp-peak-kBps = <816000>;
6160 };
6161
6162 cl2_ch1_opp12: opp-960000000 {
6163 opp-hz = /bits/ 64 <960000000>;
6164 opp-peak-kBps = <816000>;
6165 };
6166
6167 cl2_ch1_opp13: opp-1036800000 {
6168 opp-hz = /bits/ 64 <1036800000>;
6169 opp-peak-kBps = <816000>;
6170 };
6171
6172 cl2_ch1_opp14: opp-1113600000 {
6173 opp-hz = /bits/ 64 <1113600000>;
6174 opp-peak-kBps = <1632000>;
6175 };
6176
6177 cl2_ch1_opp15: opp-1190400000 {
6178 opp-hz = /bits/ 64 <1190400000>;
6179 opp-peak-kBps = <1632000>;
6180 };
6181
6182 cl2_ch1_opp16: opp-1267200000 {
6183 opp-hz = /bits/ 64 <1267200000>;
6184 opp-peak-kBps = <1632000>;
6185 };
6186
6187 cl2_ch1_opp17: opp-1344000000 {
6188 opp-hz = /bits/ 64 <1344000000>;
6189 opp-peak-kBps = <1632000>;
6190 };
6191
6192 cl2_ch1_opp18: opp-1420800000 {
6193 opp-hz = /bits/ 64 <1420800000>;
6194 opp-peak-kBps = <1632000>;
6195 };
6196
6197 cl2_ch1_opp19: opp-1497600000 {
6198 opp-hz = /bits/ 64 <1497600000>;
6199 opp-peak-kBps = <3200000>;
6200 };
6201
6202 cl2_ch1_opp20: opp-1574400000 {
6203 opp-hz = /bits/ 64 <1574400000>;
6204 opp-peak-kBps = <3200000>;
6205 };
6206
6207 cl2_ch1_opp21: opp-1651200000 {
6208 opp-hz = /bits/ 64 <1651200000>;
6209 opp-peak-kBps = <3200000>;
6210 };
6211
6212 cl2_ch1_opp22: opp-1728000000 {
6213 opp-hz = /bits/ 64 <1728000000>;
6214 opp-peak-kBps = <3200000>;
6215 };
6216
6217 cl2_ch1_opp23: opp-1804800000 {
6218 opp-hz = /bits/ 64 <1804800000>;
6219 opp-peak-kBps = <3200000>;
6220 };
6221
6222 cl2_ch1_opp24: opp-1881600000 {
6223 opp-hz = /bits/ 64 <1881600000>;
6224 opp-peak-kBps = <3200000>;
6225 };
6226
6227 cl2_ch1_opp25: opp-1958400000 {
6228 opp-hz = /bits/ 64 <1958400000>;
6229 opp-peak-kBps = <3200000>;
6230 };
6231
6232 cl2_ch1_opp26: opp-2035200000 {
6233 opp-hz = /bits/ 64 <2035200000>;
6234 opp-peak-kBps = <3200000>;
6235 };
6236
6237 cl2_ch1_opp27: opp-2112000000 {
6238 opp-hz = /bits/ 64 <2112000000>;
6239 opp-peak-kBps = <6400000>;
6240 };
6241
6242 cl2_ch1_opp28: opp-2188800000 {
6243 opp-hz = /bits/ 64 <2188800000>;
6244 opp-peak-kBps = <6400000>;
6245 };
6246
6247 cl2_ch1_opp29: opp-2201600000 {
6248 opp-hz = /bits/ 64 <2201600000>;
6249 opp-peak-kBps = <6400000>;
6250 };
6251 };
6252 };
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