1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h>
17
18 / {
19 interrupt-parent = <&intc>;
20
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 chosen { };
25
26 clocks {
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
32 };
33
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
39 };
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "qcom,kryo";
49 reg = <0x0 0x0>;
50 enable-method = "psci";
51 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>;
54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
55 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>;
57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache {
59 compatible = "cache";
60 cache-level = <2>;
61 cache-unified;
62 };
63 };
64
65 CPU1: cpu@1 {
66 device_type = "cpu";
67 compatible = "qcom,kryo";
68 reg = <0x0 0x1>;
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>;
73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
74 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>;
76 next-level-cache = <&L2_0>;
77 };
78
79 CPU2: cpu@100 {
80 device_type = "cpu";
81 compatible = "qcom,kryo";
82 reg = <0x0 0x100>;
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>;
87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
88 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 compatible = "cache";
93 cache-level = <2>;
94 cache-unified;
95 };
96 };
97
98 CPU3: cpu@101 {
99 device_type = "cpu";
100 compatible = "qcom,kryo";
101 reg = <0x0 0x101>;
102 enable-method = "psci";
103 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>;
106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
107 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>;
109 next-level-cache = <&L2_1>;
110 };
111
112 cpu-map {
113 cluster0 {
114 core0 {
115 cpu = <&CPU0>;
116 };
117
118 core1 {
119 cpu = <&CPU1>;
120 };
121 };
122
123 cluster1 {
124 core0 {
125 cpu = <&CPU2>;
126 };
127
128 core1 {
129 cpu = <&CPU3>;
130 };
131 };
132 };
133
134 idle-states {
135 entry-method = "psci";
136
137 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = "arm,idle-state";
139 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspend-param = <0x00000004>;
141 entry-latency-us = <130>;
142 exit-latency-us = <80>;
143 min-residency-us = <300>;
144 };
145 };
146 };
147
148 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse>;
151 opp-shared;
152
153 /* Nominal fmax for now */
154 opp-307200000 {
155 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0xf>;
157 clock-latency-ns = <200000>;
158 opp-peak-kBps = <307200>;
159 };
160 opp-422400000 {
161 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0xf>;
163 clock-latency-ns = <200000>;
164 opp-peak-kBps = <307200>;
165 };
166 opp-480000000 {
167 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0xf>;
169 clock-latency-ns = <200000>;
170 opp-peak-kBps = <307200>;
171 };
172 opp-556800000 {
173 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0xf>;
175 clock-latency-ns = <200000>;
176 opp-peak-kBps = <307200>;
177 };
178 opp-652800000 {
179 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0xf>;
181 clock-latency-ns = <200000>;
182 opp-peak-kBps = <384000>;
183 };
184 opp-729600000 {
185 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0xf>;
187 clock-latency-ns = <200000>;
188 opp-peak-kBps = <460800>;
189 };
190 opp-844800000 {
191 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0xf>;
193 clock-latency-ns = <200000>;
194 opp-peak-kBps = <537600>;
195 };
196 opp-960000000 {
197 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0xf>;
199 clock-latency-ns = <200000>;
200 opp-peak-kBps = <672000>;
201 };
202 opp-1036800000 {
203 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0xf>;
205 clock-latency-ns = <200000>;
206 opp-peak-kBps = <672000>;
207 };
208 opp-1113600000 {
209 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0xf>;
211 clock-latency-ns = <200000>;
212 opp-peak-kBps = <825600>;
213 };
214 opp-1190400000 {
215 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0xf>;
217 clock-latency-ns = <200000>;
218 opp-peak-kBps = <825600>;
219 };
220 opp-1228800000 {
221 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0xf>;
223 clock-latency-ns = <200000>;
224 opp-peak-kBps = <902400>;
225 };
226 opp-1324800000 {
227 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0xd>;
229 clock-latency-ns = <200000>;
230 opp-peak-kBps = <1056000>;
231 };
232 opp-1363200000 {
233 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x2>;
235 clock-latency-ns = <200000>;
236 opp-peak-kBps = <1132800>;
237 };
238 opp-1401600000 {
239 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0xd>;
241 clock-latency-ns = <200000>;
242 opp-peak-kBps = <1132800>;
243 };
244 opp-1478400000 {
245 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x9>;
247 clock-latency-ns = <200000>;
248 opp-peak-kBps = <1190400>;
249 };
250 opp-1497600000 {
251 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x04>;
253 clock-latency-ns = <200000>;
254 opp-peak-kBps = <1305600>;
255 };
256 opp-1593600000 {
257 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x9>;
259 clock-latency-ns = <200000>;
260 opp-peak-kBps = <1382400>;
261 };
262 };
263
264 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse>;
267 opp-shared;
268
269 /* Nominal fmax for now */
270 opp-307200000 {
271 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0xf>;
273 clock-latency-ns = <200000>;
274 opp-peak-kBps = <307200>;
275 };
276 opp-403200000 {
277 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0xf>;
279 clock-latency-ns = <200000>;
280 opp-peak-kBps = <307200>;
281 };
282 opp-480000000 {
283 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0xf>;
285 clock-latency-ns = <200000>;
286 opp-peak-kBps = <307200>;
287 };
288 opp-556800000 {
289 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0xf>;
291 clock-latency-ns = <200000>;
292 opp-peak-kBps = <307200>;
293 };
294 opp-652800000 {
295 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0xf>;
297 clock-latency-ns = <200000>;
298 opp-peak-kBps = <307200>;
299 };
300 opp-729600000 {
301 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0xf>;
303 clock-latency-ns = <200000>;
304 opp-peak-kBps = <307200>;
305 };
306 opp-806400000 {
307 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0xf>;
309 clock-latency-ns = <200000>;
310 opp-peak-kBps = <384000>;
311 };
312 opp-883200000 {
313 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0xf>;
315 clock-latency-ns = <200000>;
316 opp-peak-kBps = <460800>;
317 };
318 opp-940800000 {
319 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0xf>;
321 clock-latency-ns = <200000>;
322 opp-peak-kBps = <537600>;
323 };
324 opp-1036800000 {
325 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0xf>;
327 clock-latency-ns = <200000>;
328 opp-peak-kBps = <595200>;
329 };
330 opp-1113600000 {
331 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0xf>;
333 clock-latency-ns = <200000>;
334 opp-peak-kBps = <672000>;
335 };
336 opp-1190400000 {
337 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0xf>;
339 clock-latency-ns = <200000>;
340 opp-peak-kBps = <672000>;
341 };
342 opp-1248000000 {
343 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0xf>;
345 clock-latency-ns = <200000>;
346 opp-peak-kBps = <748800>;
347 };
348 opp-1324800000 {
349 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0xf>;
351 clock-latency-ns = <200000>;
352 opp-peak-kBps = <825600>;
353 };
354 opp-1401600000 {
355 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0xf>;
357 clock-latency-ns = <200000>;
358 opp-peak-kBps = <902400>;
359 };
360 opp-1478400000 {
361 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0xf>;
363 clock-latency-ns = <200000>;
364 opp-peak-kBps = <979200>;
365 };
366 opp-1555200000 {
367 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0xf>;
369 clock-latency-ns = <200000>;
370 opp-peak-kBps = <1056000>;
371 };
372 opp-1632000000 {
373 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0xf>;
375 clock-latency-ns = <200000>;
376 opp-peak-kBps = <1190400>;
377 };
378 opp-1708800000 {
379 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0xf>;
381 clock-latency-ns = <200000>;
382 opp-peak-kBps = <1228800>;
383 };
384 opp-1785600000 {
385 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0xf>;
387 clock-latency-ns = <200000>;
388 opp-peak-kBps = <1305600>;
389 };
390 opp-1804800000 {
391 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0xe>;
393 clock-latency-ns = <200000>;
394 opp-peak-kBps = <1305600>;
395 };
396 opp-1824000000 {
397 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x1>;
399 clock-latency-ns = <200000>;
400 opp-peak-kBps = <1382400>;
401 };
402 opp-1900800000 {
403 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x4>;
405 clock-latency-ns = <200000>;
406 opp-peak-kBps = <1305600>;
407 };
408 opp-1920000000 {
409 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x1>;
411 clock-latency-ns = <200000>;
412 opp-peak-kBps = <1459200>;
413 };
414 opp-1996800000 {
415 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x1>;
417 clock-latency-ns = <200000>;
418 opp-peak-kBps = <1593600>;
419 };
420 opp-2073600000 {
421 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x1>;
423 clock-latency-ns = <200000>;
424 opp-peak-kBps = <1593600>;
425 };
426 opp-2150400000 {
427 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x1>;
429 clock-latency-ns = <200000>;
430 opp-peak-kBps = <1593600>;
431 };
432 };
433
434 firmware {
435 scm {
436 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tcsr_2 0x13000>;
438 };
439 };
440
441 memory@80000000 {
442 device_type = "memory";
443 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0>;
445 };
446
447 etm {
448 compatible = "qcom,coresight-remote-etm";
449
450 out-ports {
451 port {
452 modem_etm_out_funnel_in2: endpoint {
453 remote-endpoint =
454 <&funnel_in2_in_modem_etm>;
455 };
456 };
457 };
458 };
459
460 psci {
461 compatible = "arm,psci-1.0";
462 method = "smc";
463 };
464
465 rpm: remoteproc {
466 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
467
468 glink-edge {
469 compatible = "qcom,glink-rpm";
470 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
471 qcom,rpm-msg-ram = <&rpm_msg_ram>;
472 mboxes = <&apcs_glb 0>;
473
474 rpm_requests: rpm-requests {
475 compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm";
476 qcom,glink-channels = "rpm_requests";
477
478 rpmcc: clock-controller {
479 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
480 #clock-cells = <1>;
481 clocks = <&xo_board>;
482 clock-names = "xo";
483 };
484
485 rpmpd: power-controller {
486 compatible = "qcom,msm8996-rpmpd";
487 #power-domain-cells = <1>;
488 operating-points-v2 = <&rpmpd_opp_table>;
489
490 rpmpd_opp_table: opp-table {
491 compatible = "operating-points-v2";
492
493 rpmpd_opp1: opp1 {
494 opp-level = <1>;
495 };
496
497 rpmpd_opp2: opp2 {
498 opp-level = <2>;
499 };
500
501 rpmpd_opp3: opp3 {
502 opp-level = <3>;
503 };
504
505 rpmpd_opp4: opp4 {
506 opp-level = <4>;
507 };
508
509 rpmpd_opp5: opp5 {
510 opp-level = <5>;
511 };
512
513 rpmpd_opp6: opp6 {
514 opp-level = <6>;
515 };
516 };
517 };
518 };
519 };
520 };
521
522 reserved-memory {
523 #address-cells = <2>;
524 #size-cells = <2>;
525 ranges;
526
527 hyp_mem: memory@85800000 {
528 reg = <0x0 0x85800000 0x0 0x600000>;
529 no-map;
530 };
531
532 xbl_mem: memory@85e00000 {
533 reg = <0x0 0x85e00000 0x0 0x200000>;
534 no-map;
535 };
536
537 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map;
540 };
541
542 tz_mem: memory@86200000 {
543 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map;
545 };
546
547 rmtfs_mem: rmtfs {
548 compatible = "qcom,rmtfs-mem";
549
550 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map;
553
554 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
556 };
557
558 mpss_mem: mpss@88800000 {
559 reg = <0x0 0x88800000 0x0 0x6200000>;
560 no-map;
561 };
562
563 adsp_mem: adsp@8ea00000 {
564 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
565 no-map;
566 };
567
568 slpi_mem: slpi@90500000 {
569 reg = <0x0 0x90500000 0x0 0xa00000>;
570 no-map;
571 };
572
573 gpu_mem: gpu@90f00000 {
574 compatible = "shared-dma-pool";
575 reg = <0x0 0x90f00000 0x0 0x100000>;
576 no-map;
577 };
578
579 venus_mem: venus@91000000 {
580 reg = <0x0 0x91000000 0x0 0x500000>;
581 no-map;
582 };
583
584 mba_mem: mba@91500000 {
585 reg = <0x0 0x91500000 0x0 0x200000>;
586 no-map;
587 };
588
589 mdata_mem: mpss-metadata {
590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 size = <0x0 0x4000>;
592 no-map;
593 };
594 };
595
596 smem {
597 compatible = "qcom,smem";
598 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>;
600 };
601
602 smp2p-adsp {
603 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>;
605
606 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
607
608 mboxes = <&apcs_glb 10>;
609
610 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>;
612
613 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells = <1>;
616 };
617
618 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "slave-kernel";
620
621 interrupt-controller;
622 #interrupt-cells = <2>;
623 };
624 };
625
626 smp2p-mpss {
627 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>;
629
630 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631
632 mboxes = <&apcs_glb 14>;
633
634 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>;
636
637 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells = <1>;
640 };
641
642 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "slave-kernel";
644
645 interrupt-controller;
646 #interrupt-cells = <2>;
647 };
648 };
649
650 smp2p-slpi {
651 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>;
653
654 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655
656 mboxes = <&apcs_glb 26>;
657
658 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>;
660
661 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells = <1>;
664 };
665
666 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "slave-kernel";
668
669 interrupt-controller;
670 #interrupt-cells = <2>;
671 };
672 };
673
674 soc: soc@0 {
675 #address-cells = <1>;
676 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus";
679
680 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x488>;
683 #address-cells = <1>;
684 #size-cells = <1>;
685 ranges = <0x0 0x00034000 0x4000>;
686
687 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", "cfg_ahb", "ref";
691
692 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", "common", "cfg";
696
697 status = "disabled";
698
699 pciephy_0: phy@1000 {
700 reg = <0x1000 0x130>,
701 <0x1200 0x200>,
702 <0x1400 0x1dc>;
703
704 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = "pipe0";
706 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = "lane0";
708
709 #clock-cells = <0>;
710 clock-output-names = "pcie_0_pipe_clk_src";
711
712 #phy-cells = <0>;
713 };
714
715 pciephy_1: phy@2000 {
716 reg = <0x2000 0x130>,
717 <0x2200 0x200>,
718 <0x2400 0x1dc>;
719
720 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = "pipe1";
722 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = "lane1";
724
725 #clock-cells = <0>;
726 clock-output-names = "pcie_1_pipe_clk_src";
727
728 #phy-cells = <0>;
729 };
730
731 pciephy_2: phy@3000 {
732 reg = <0x3000 0x130>,
733 <0x3200 0x200>,
734 <0x3400 0x1dc>;
735
736 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = "pipe2";
738 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = "lane2";
740
741 #clock-cells = <0>;
742 clock-output-names = "pcie_2_pipe_clk_src";
743
744 #phy-cells = <0>;
745 };
746 };
747
748 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x6000>;
751 };
752
753 qfprom@74000 {
754 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
755 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>;
757 #size-cells = <1>;
758
759 qusb2p_hstx_trim: hstx-trim@24e {
760 reg = <0x24e 0x2>;
761 bits = <5 4>;
762 };
763
764 qusb2s_hstx_trim: hstx-trim@24f {
765 reg = <0x24f 0x1>;
766 bits = <1 4>;
767 };
768
769 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0x1>;
771 bits = <5 3>;
772 };
773 };
774
775 rng: rng@83000 {
776 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core";
780 };
781
782 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90000>;
788
789 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
790 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>,
792 <&pciephy_0>,
793 <&pciephy_1>,
794 <&pciephy_2>,
795 <&usb3phy>,
796 <&ufsphy 0>,
797 <&ufsphy 1>,
798 <&ufsphy 2>;
799 clock-names = "cxo",
800 "cxo2",
801 "sleep_clk",
802 "pcie_0_pipe_clk_src",
803 "pcie_1_pipe_clk_src",
804 "pcie_2_pipe_clk_src",
805 "usb3_phy_pipe_clk_src",
806 "ufs_rx_symbol_0_clk_src",
807 "ufs_rx_symbol_1_clk_src",
808 "ufs_tx_symbol_0_clk_src";
809 };
810
811 bimc: interconnect@408000 {
812 compatible = "qcom,msm8996-bimc";
813 reg = <0x00408000 0x5a000>;
814 #interconnect-cells = <1>;
815 };
816
817 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells = <1>;
826 };
827
828 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells = <1>;
837 };
838
839 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk";
845 #dma-cells = <1>;
846 qcom,ee = <0>;
847 qcom,controlled-remotely;
848 };
849
850 crypto: crypto@67a000 {
851 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx";
859 };
860
861 cnoc: interconnect@500000 {
862 compatible = "qcom,msm8996-cnoc";
863 reg = <0x00500000 0x1000>;
864 #interconnect-cells = <1>;
865 };
866
867 snoc: interconnect@524000 {
868 compatible = "qcom,msm8996-snoc";
869 reg = <0x00524000 0x1c000>;
870 #interconnect-cells = <1>;
871 };
872
873 a0noc: interconnect@543000 {
874 compatible = "qcom,msm8996-a0noc";
875 reg = <0x00543000 0x6000>;
876 #interconnect-cells = <1>;
877 clock-names = "aggre0_snoc_axi",
878 "aggre0_cnoc_ahb",
879 "aggre0_noc_mpu_cfg";
880 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
881 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
882 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
883 power-domains = <&gcc AGGRE0_NOC_GDSC>;
884 };
885
886 a1noc: interconnect@562000 {
887 compatible = "qcom,msm8996-a1noc";
888 reg = <0x00562000 0x5000>;
889 #interconnect-cells = <1>;
890 };
891
892 a2noc: interconnect@583000 {
893 compatible = "qcom,msm8996-a2noc";
894 reg = <0x00583000 0x7000>;
895 #interconnect-cells = <1>;
896 clock-names = "aggre2_ufs_axi", "ufs_axi";
897 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
898 <&gcc GCC_UFS_AXI_CLK>;
899 };
900
901 mnoc: interconnect@5a4000 {
902 compatible = "qcom,msm8996-mnoc";
903 reg = <0x005a4000 0x1c000>;
904 #interconnect-cells = <1>;
905 clock-names = "iface";
906 clocks = <&mmcc AHB_CLK_SRC>;
907 };
908
909 pnoc: interconnect@5c0000 {
910 compatible = "qcom,msm8996-pnoc";
911 reg = <0x005c0000 0x3000>;
912 #interconnect-cells = <1>;
913 };
914
915 tcsr_mutex: hwlock@740000 {
916 compatible = "qcom,tcsr-mutex";
917 reg = <0x00740000 0x20000>;
918 #hwlock-cells = <1>;
919 };
920
921 tcsr_1: syscon@760000 {
922 compatible = "qcom,tcsr-msm8996", "syscon";
923 reg = <0x00760000 0x20000>;
924 };
925
926 tcsr_2: syscon@7a0000 {
927 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18000>;
929 };
930
931 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>;
934 #reset-cells = <1>;
935 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>,
938 <&gcc GPLL0>,
939 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
940 <&mdss_dsi0_phy 1>,
941 <&mdss_dsi0_phy 0>,
942 <&mdss_dsi1_phy 1>,
943 <&mdss_dsi1_phy 0>,
944 <&mdss_hdmi_phy>;
945 clock-names = "xo",
946 "gpll0",
947 "gcc_mmss_noc_cfg_ahb_clk",
948 "dsi0pll",
949 "dsi0pllbyte",
950 "dsi1pll",
951 "dsi1pllbyte",
952 "hdmipll";
953 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mmcc MMPLL1_PLL>,
955 <&mmcc MMPLL3_PLL>,
956 <&mmcc MMPLL4_PLL>,
957 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = <624000000>,
959 <810000000>,
960 <980000000>,
961 <960000000>,
962 <825000000>;
963 };
964
965 mdss: display-subsystem@900000 {
966 compatible = "qcom,mdss";
967
968 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x1040>,
970 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys",
972 "vbif_phys",
973 "vbif_nrt_phys";
974
975 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977
978 interrupt-controller;
979 #interrupt-cells = <1>;
980
981 clocks = <&mmcc MDSS_AHB_CLK>,
982 <&mmcc MDSS_MDP_CLK>;
983 clock-names = "iface", "core";
984
985 resets = <&mmcc MDSS_BCR>;
986
987 #address-cells = <1>;
988 #size-cells = <1>;
989 ranges;
990
991 status = "disabled";
992
993 mdp: display-controller@901000 {
994 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
995 reg = <0x00901000 0x90000>;
996 reg-names = "mdp_phys";
997
998 interrupt-parent = <&mdss>;
999 interrupts = <0>;
1000
1001 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mmcc MDSS_AXI_CLK>,
1003 <&mmcc MDSS_MDP_CLK>,
1004 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = "iface",
1007 "bus",
1008 "core",
1009 "iommu",
1010 "vsync";
1011
1012 iommus = <&mdp_smmu 0>;
1013
1014 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-clock-rates = <300000000>,
1017 <19200000>;
1018
1019 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1020 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1021 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1022 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1023
1024 ports {
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027
1028 port@0 {
1029 reg = <0>;
1030 mdp5_intf3_out: endpoint {
1031 remote-endpoint = <&mdss_hdmi_in>;
1032 };
1033 };
1034
1035 port@1 {
1036 reg = <1>;
1037 mdp5_intf1_out: endpoint {
1038 remote-endpoint = <&mdss_dsi0_in>;
1039 };
1040 };
1041
1042 port@2 {
1043 reg = <2>;
1044 mdp5_intf2_out: endpoint {
1045 remote-endpoint = <&mdss_dsi1_in>;
1046 };
1047 };
1048 };
1049 };
1050
1051 mdss_dsi0: dsi@994000 {
1052 compatible = "qcom,msm8996-dsi-ctrl",
1053 "qcom,mdss-dsi-ctrl";
1054 reg = <0x00994000 0x400>;
1055 reg-names = "dsi_ctrl";
1056
1057 interrupt-parent = <&mdss>;
1058 interrupts = <4>;
1059
1060 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mmcc MDSS_AHB_CLK>,
1063 <&mmcc MDSS_AXI_CLK>,
1064 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = "mdp_core",
1068 "byte",
1069 "iface",
1070 "bus",
1071 "core_mmss",
1072 "pixel",
1073 "core";
1074 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1075 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1076
1077 phys = <&mdss_dsi0_phy>;
1078 status = "disabled";
1079
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082
1083 ports {
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086
1087 port@0 {
1088 reg = <0>;
1089 mdss_dsi0_in: endpoint {
1090 remote-endpoint = <&mdp5_intf1_out>;
1091 };
1092 };
1093
1094 port@1 {
1095 reg = <1>;
1096 mdss_dsi0_out: endpoint {
1097 };
1098 };
1099 };
1100 };
1101
1102 mdss_dsi0_phy: phy@994400 {
1103 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x00994400 0x100>,
1105 <0x00994500 0x300>,
1106 <0x00994800 0x188>;
1107 reg-names = "dsi_phy",
1108 "dsi_phy_lane",
1109 "dsi_pll";
1110
1111 #clock-cells = <1>;
1112 #phy-cells = <0>;
1113
1114 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1115 clock-names = "iface", "ref";
1116 status = "disabled";
1117 };
1118
1119 mdss_dsi1: dsi@996000 {
1120 compatible = "qcom,msm8996-dsi-ctrl",
1121 "qcom,mdss-dsi-ctrl";
1122 reg = <0x00996000 0x400>;
1123 reg-names = "dsi_ctrl";
1124
1125 interrupt-parent = <&mdss>;
1126 interrupts = <5>;
1127
1128 clocks = <&mmcc MDSS_MDP_CLK>,
1129 <&mmcc MDSS_BYTE1_CLK>,
1130 <&mmcc MDSS_AHB_CLK>,
1131 <&mmcc MDSS_AXI_CLK>,
1132 <&mmcc MMSS_MISC_AHB_CLK>,
1133 <&mmcc MDSS_PCLK1_CLK>,
1134 <&mmcc MDSS_ESC1_CLK>;
1135 clock-names = "mdp_core",
1136 "byte",
1137 "iface",
1138 "bus",
1139 "core_mmss",
1140 "pixel",
1141 "core";
1142 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1143 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1144
1145 phys = <&mdss_dsi1_phy>;
1146 status = "disabled";
1147
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1150
1151 ports {
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154
1155 port@0 {
1156 reg = <0>;
1157 mdss_dsi1_in: endpoint {
1158 remote-endpoint = <&mdp5_intf2_out>;
1159 };
1160 };
1161
1162 port@1 {
1163 reg = <1>;
1164 mdss_dsi1_out: endpoint {
1165 };
1166 };
1167 };
1168 };
1169
1170 mdss_dsi1_phy: phy@996400 {
1171 compatible = "qcom,dsi-phy-14nm";
1172 reg = <0x00996400 0x100>,
1173 <0x00996500 0x300>,
1174 <0x00996800 0x188>;
1175 reg-names = "dsi_phy",
1176 "dsi_phy_lane",
1177 "dsi_pll";
1178
1179 #clock-cells = <1>;
1180 #phy-cells = <0>;
1181
1182 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1183 clock-names = "iface", "ref";
1184 status = "disabled";
1185 };
1186
1187 mdss_hdmi: hdmi-tx@9a0000 {
1188 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a0000 0x50c>,
1190 <0x00070000 0x6158>,
1191 <0x009e0000 0xfff>;
1192 reg-names = "core_physical",
1193 "qfprom_physical",
1194 "hdcp_physical";
1195
1196 interrupt-parent = <&mdss>;
1197 interrupts = <8>;
1198
1199 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mmcc MDSS_AHB_CLK>,
1201 <&mmcc MDSS_HDMI_CLK>,
1202 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names =
1205 "mdp_core",
1206 "iface",
1207 "core",
1208 "alt_iface",
1209 "extp";
1210
1211 phys = <&mdss_hdmi_phy>;
1212 #sound-dai-cells = <1>;
1213
1214 status = "disabled";
1215
1216 ports {
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219
1220 port@0 {
1221 reg = <0>;
1222 mdss_hdmi_in: endpoint {
1223 remote-endpoint = <&mdp5_intf3_out>;
1224 };
1225 };
1226 };
1227 };
1228
1229 mdss_hdmi_phy: phy@9a0600 {
1230 #phy-cells = <0>;
1231 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a0600 0x1c4>,
1233 <0x009a0a00 0x124>,
1234 <0x009a0c00 0x124>,
1235 <0x009a0e00 0x124>,
1236 <0x009a1000 0x124>,
1237 <0x009a1200 0x0c8>;
1238 reg-names = "hdmi_pll",
1239 "hdmi_tx_l0",
1240 "hdmi_tx_l1",
1241 "hdmi_tx_l2",
1242 "hdmi_tx_l3",
1243 "hdmi_phy";
1244
1245 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gcc GCC_HDMI_CLKREF_CLK>,
1247 <&xo_board>;
1248 clock-names = "iface",
1249 "ref",
1250 "xo";
1251
1252 #clock-cells = <0>;
1253
1254 status = "disabled";
1255 };
1256 };
1257
1258 gpu: gpu@b00000 {
1259 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260
1261 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0_reg_memory";
1263
1264 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1265
1266 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271
1272 clock-names = "core",
1273 "iface",
1274 "rbbmtimer",
1275 "mem",
1276 "mem_iface";
1277
1278 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1279 interconnect-names = "gfx-mem";
1280
1281 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smmu 0>;
1283
1284 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "speed_bin";
1286
1287 operating-points-v2 = <&gpu_opp_table>;
1288
1289 status = "disabled";
1290
1291 #cooling-cells = <2>;
1292
1293 gpu_opp_table: opp-table {
1294 compatible = "operating-points-v2";
1295
1296 /*
1297 * 624Mhz is only available on speed bins 0 and 3.
1298 * 560Mhz is only available on speed bins 0, 2 and 3.
1299 * All the rest are available on all bins of the hardware.
1300 */
1301 opp-624000000 {
1302 opp-hz = /bits/ 64 <624000000>;
1303 opp-supported-hw = <0x09>;
1304 };
1305 opp-560000000 {
1306 opp-hz = /bits/ 64 <560000000>;
1307 opp-supported-hw = <0x0d>;
1308 };
1309 opp-510000000 {
1310 opp-hz = /bits/ 64 <510000000>;
1311 opp-supported-hw = <0xff>;
1312 };
1313 opp-401800000 {
1314 opp-hz = /bits/ 64 <401800000>;
1315 opp-supported-hw = <0xff>;
1316 };
1317 opp-315000000 {
1318 opp-hz = /bits/ 64 <315000000>;
1319 opp-supported-hw = <0xff>;
1320 };
1321 opp-214000000 {
1322 opp-hz = /bits/ 64 <214000000>;
1323 opp-supported-hw = <0xff>;
1324 };
1325 opp-133000000 {
1326 opp-hz = /bits/ 64 <133000000>;
1327 opp-supported-hw = <0xff>;
1328 };
1329 };
1330
1331 zap-shader {
1332 memory-region = <&gpu_mem>;
1333 };
1334 };
1335
1336 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller;
1341 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>;
1343 interrupt-controller;
1344 #interrupt-cells = <2>;
1345
1346 blsp1_spi1_default: blsp1-spi1-default-state {
1347 spi-pins {
1348 pins = "gpio0", "gpio1", "gpio3";
1349 function = "blsp_spi1";
1350 drive-strength = <12>;
1351 bias-disable;
1352 };
1353
1354 cs-pins {
1355 pins = "gpio2";
1356 function = "gpio";
1357 drive-strength = <16>;
1358 bias-disable;
1359 output-high;
1360 };
1361 };
1362
1363 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1364 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "gpio";
1366 drive-strength = <2>;
1367 bias-pull-down;
1368 };
1369
1370 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1371 pins = "gpio4", "gpio5";
1372 function = "blsp_uart8";
1373 drive-strength = <16>;
1374 bias-disable;
1375 };
1376
1377 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1378 pins = "gpio4", "gpio5";
1379 function = "gpio";
1380 drive-strength = <2>;
1381 bias-disable;
1382 };
1383
1384 blsp2_i2c2_default: blsp2-i2c2-state {
1385 pins = "gpio6", "gpio7";
1386 function = "blsp_i2c8";
1387 drive-strength = <16>;
1388 bias-disable;
1389 };
1390
1391 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1392 pins = "gpio6", "gpio7";
1393 function = "gpio";
1394 drive-strength = <2>;
1395 bias-disable;
1396 };
1397
1398 blsp1_i2c6_default: blsp1-i2c6-state {
1399 pins = "gpio27", "gpio28";
1400 function = "blsp_i2c6";
1401 drive-strength = <16>;
1402 bias-disable;
1403 };
1404
1405 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1406 pins = "gpio27", "gpio28";
1407 function = "gpio";
1408 drive-strength = <2>;
1409 bias-pull-up;
1410 };
1411
1412 cci0_default: cci0-default-state {
1413 pins = "gpio17", "gpio18";
1414 function = "cci_i2c";
1415 drive-strength = <16>;
1416 bias-disable;
1417 };
1418
1419 camera0_state_on:
1420 camera_rear_default: camera-rear-default-state {
1421 camera0_mclk: mclk0-pins {
1422 pins = "gpio13";
1423 function = "cam_mclk";
1424 drive-strength = <16>;
1425 bias-disable;
1426 };
1427
1428 camera0_rst: rst-pins {
1429 pins = "gpio25";
1430 function = "gpio";
1431 drive-strength = <16>;
1432 bias-disable;
1433 };
1434
1435 camera0_pwdn: pwdn-pins {
1436 pins = "gpio26";
1437 function = "gpio";
1438 drive-strength = <16>;
1439 bias-disable;
1440 };
1441 };
1442
1443 cci1_default: cci1-default-state {
1444 pins = "gpio19", "gpio20";
1445 function = "cci_i2c";
1446 drive-strength = <16>;
1447 bias-disable;
1448 };
1449
1450 camera1_state_on:
1451 camera_board_default: camera-board-default-state {
1452 mclk1-pins {
1453 pins = "gpio14";
1454 function = "cam_mclk";
1455 drive-strength = <16>;
1456 bias-disable;
1457 };
1458
1459 pwdn-pins {
1460 pins = "gpio98";
1461 function = "gpio";
1462 drive-strength = <16>;
1463 bias-disable;
1464 };
1465
1466 rst-pins {
1467 pins = "gpio104";
1468 function = "gpio";
1469 drive-strength = <16>;
1470 bias-disable;
1471 };
1472 };
1473
1474 camera2_state_on:
1475 camera_front_default: camera-front-default-state {
1476 camera2_mclk: mclk2-pins {
1477 pins = "gpio15";
1478 function = "cam_mclk";
1479 drive-strength = <16>;
1480 bias-disable;
1481 };
1482
1483 camera2_rst: rst-pins {
1484 pins = "gpio23";
1485 function = "gpio";
1486 drive-strength = <16>;
1487 bias-disable;
1488 };
1489
1490 pwdn-pins {
1491 pins = "gpio133";
1492 function = "gpio";
1493 drive-strength = <16>;
1494 bias-disable;
1495 };
1496 };
1497
1498 pcie0_state_on: pcie0-state-on-state {
1499 perst-pins {
1500 pins = "gpio35";
1501 function = "gpio";
1502 drive-strength = <2>;
1503 bias-pull-down;
1504 };
1505
1506 clkreq-pins {
1507 pins = "gpio36";
1508 function = "pci_e0";
1509 drive-strength = <2>;
1510 bias-pull-up;
1511 };
1512
1513 wake-pins {
1514 pins = "gpio37";
1515 function = "gpio";
1516 drive-strength = <2>;
1517 bias-pull-up;
1518 };
1519 };
1520
1521 pcie0_state_off: pcie0-state-off-state {
1522 perst-pins {
1523 pins = "gpio35";
1524 function = "gpio";
1525 drive-strength = <2>;
1526 bias-pull-down;
1527 };
1528
1529 clkreq-pins {
1530 pins = "gpio36";
1531 function = "gpio";
1532 drive-strength = <2>;
1533 bias-disable;
1534 };
1535
1536 wake-pins {
1537 pins = "gpio37";
1538 function = "gpio";
1539 drive-strength = <2>;
1540 bias-disable;
1541 };
1542 };
1543
1544 blsp1_uart2_default: blsp1-uart2-default-state {
1545 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "blsp_uart2";
1547 drive-strength = <16>;
1548 bias-disable;
1549 };
1550
1551 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1552 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "gpio";
1554 drive-strength = <2>;
1555 bias-disable;
1556 };
1557
1558 blsp1_i2c3_default: blsp1-i2c3-default-state {
1559 pins = "gpio47", "gpio48";
1560 function = "blsp_i2c3";
1561 drive-strength = <16>;
1562 bias-disable;
1563 };
1564
1565 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1566 pins = "gpio47", "gpio48";
1567 function = "gpio";
1568 drive-strength = <2>;
1569 bias-disable;
1570 };
1571
1572 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1573 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "blsp_uart9";
1575 drive-strength = <16>;
1576 bias-disable;
1577 };
1578
1579 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1580 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "blsp_uart9";
1582 drive-strength = <2>;
1583 bias-disable;
1584 };
1585
1586 blsp2_i2c3_default: blsp2-i2c3-state-state {
1587 pins = "gpio51", "gpio52";
1588 function = "blsp_i2c9";
1589 drive-strength = <16>;
1590 bias-disable;
1591 };
1592
1593 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1594 pins = "gpio51", "gpio52";
1595 function = "gpio";
1596 drive-strength = <2>;
1597 bias-disable;
1598 };
1599
1600 wcd_intr_default: wcd-intr-default-state {
1601 pins = "gpio54";
1602 function = "gpio";
1603 drive-strength = <2>;
1604 bias-pull-down;
1605 };
1606
1607 blsp2_i2c1_default: blsp2-i2c1-state {
1608 pins = "gpio55", "gpio56";
1609 function = "blsp_i2c7";
1610 drive-strength = <16>;
1611 bias-disable;
1612 };
1613
1614 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1615 pins = "gpio55", "gpio56";
1616 function = "gpio";
1617 drive-strength = <2>;
1618 bias-disable;
1619 };
1620
1621 blsp2_i2c5_default: blsp2-i2c5-state {
1622 pins = "gpio60", "gpio61";
1623 function = "blsp_i2c11";
1624 drive-strength = <2>;
1625 bias-disable;
1626 };
1627
1628 /* Sleep state for BLSP2_I2C5 is missing.. */
1629
1630 cdc_reset_active: cdc-reset-active-state {
1631 pins = "gpio64";
1632 function = "gpio";
1633 drive-strength = <16>;
1634 bias-pull-down;
1635 output-high;
1636 };
1637
1638 cdc_reset_sleep: cdc-reset-sleep-state {
1639 pins = "gpio64";
1640 function = "gpio";
1641 drive-strength = <16>;
1642 bias-disable;
1643 output-low;
1644 };
1645
1646 blsp2_spi6_default: blsp2-spi6-default-state {
1647 spi-pins {
1648 pins = "gpio85", "gpio86", "gpio88";
1649 function = "blsp_spi12";
1650 drive-strength = <12>;
1651 bias-disable;
1652 };
1653
1654 cs-pins {
1655 pins = "gpio87";
1656 function = "gpio";
1657 drive-strength = <16>;
1658 bias-disable;
1659 output-high;
1660 };
1661 };
1662
1663 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1664 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "gpio";
1666 drive-strength = <2>;
1667 bias-pull-down;
1668 };
1669
1670 blsp2_i2c6_default: blsp2-i2c6-state {
1671 pins = "gpio87", "gpio88";
1672 function = "blsp_i2c12";
1673 drive-strength = <16>;
1674 bias-disable;
1675 };
1676
1677 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1678 pins = "gpio87", "gpio88";
1679 function = "gpio";
1680 drive-strength = <2>;
1681 bias-disable;
1682 };
1683
1684 pcie1_state_on: pcie1-on-state {
1685 perst-pins {
1686 pins = "gpio130";
1687 function = "gpio";
1688 drive-strength = <2>;
1689 bias-pull-down;
1690 };
1691
1692 clkreq-pins {
1693 pins = "gpio131";
1694 function = "pci_e1";
1695 drive-strength = <2>;
1696 bias-pull-up;
1697 };
1698
1699 wake-pins {
1700 pins = "gpio132";
1701 function = "gpio";
1702 drive-strength = <2>;
1703 bias-pull-down;
1704 };
1705 };
1706
1707 pcie1_state_off: pcie1-off-state {
1708 /* Perst is missing? */
1709 clkreq-pins {
1710 pins = "gpio131";
1711 function = "gpio";
1712 drive-strength = <2>;
1713 bias-disable;
1714 };
1715
1716 wake-pins {
1717 pins = "gpio132";
1718 function = "gpio";
1719 drive-strength = <2>;
1720 bias-disable;
1721 };
1722 };
1723
1724 pcie2_state_on: pcie2-on-state {
1725 perst-pins {
1726 pins = "gpio114";
1727 function = "gpio";
1728 drive-strength = <2>;
1729 bias-pull-down;
1730 };
1731
1732 clkreq-pins {
1733 pins = "gpio115";
1734 function = "pci_e2";
1735 drive-strength = <2>;
1736 bias-pull-up;
1737 };
1738
1739 wake-pins {
1740 pins = "gpio116";
1741 function = "gpio";
1742 drive-strength = <2>;
1743 bias-pull-down;
1744 };
1745 };
1746
1747 pcie2_state_off: pcie2-off-state {
1748 /* Perst is missing? */
1749 clkreq-pins {
1750 pins = "gpio115";
1751 function = "gpio";
1752 drive-strength = <2>;
1753 bias-disable;
1754 };
1755
1756 wake-pins {
1757 pins = "gpio116";
1758 function = "gpio";
1759 drive-strength = <2>;
1760 bias-disable;
1761 };
1762 };
1763
1764 sdc1_state_on: sdc1-on-state {
1765 clk-pins {
1766 pins = "sdc1_clk";
1767 bias-disable;
1768 drive-strength = <16>;
1769 };
1770
1771 cmd-pins {
1772 pins = "sdc1_cmd";
1773 bias-pull-up;
1774 drive-strength = <10>;
1775 };
1776
1777 data-pins {
1778 pins = "sdc1_data";
1779 bias-pull-up;
1780 drive-strength = <10>;
1781 };
1782
1783 rclk-pins {
1784 pins = "sdc1_rclk";
1785 bias-pull-down;
1786 };
1787 };
1788
1789 sdc1_state_off: sdc1-off-state {
1790 clk-pins {
1791 pins = "sdc1_clk";
1792 bias-disable;
1793 drive-strength = <2>;
1794 };
1795
1796 cmd-pins {
1797 pins = "sdc1_cmd";
1798 bias-pull-up;
1799 drive-strength = <2>;
1800 };
1801
1802 data-pins {
1803 pins = "sdc1_data";
1804 bias-pull-up;
1805 drive-strength = <2>;
1806 };
1807
1808 rclk-pins {
1809 pins = "sdc1_rclk";
1810 bias-pull-down;
1811 };
1812 };
1813
1814 sdc2_state_on: sdc2-on-state {
1815 clk-pins {
1816 pins = "sdc2_clk";
1817 bias-disable;
1818 drive-strength = <16>;
1819 };
1820
1821 cmd-pins {
1822 pins = "sdc2_cmd";
1823 bias-pull-up;
1824 drive-strength = <10>;
1825 };
1826
1827 data-pins {
1828 pins = "sdc2_data";
1829 bias-pull-up;
1830 drive-strength = <10>;
1831 };
1832 };
1833
1834 sdc2_state_off: sdc2-off-state {
1835 clk-pins {
1836 pins = "sdc2_clk";
1837 bias-disable;
1838 drive-strength = <2>;
1839 };
1840
1841 cmd-pins {
1842 pins = "sdc2_cmd";
1843 bias-pull-up;
1844 drive-strength = <2>;
1845 };
1846
1847 data-pins {
1848 pins = "sdc2_data";
1849 bias-pull-up;
1850 drive-strength = <2>;
1851 };
1852 };
1853 };
1854
1855 sram@290000 {
1856 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x10000>;
1858 };
1859
1860 spmi_bus: spmi@400f000 {
1861 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x800000>,
1864 <0x04c00000 0x800000>,
1865 <0x05800000 0x200000>,
1866 <0x0400a000 0x002100>;
1867 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>;
1871 qcom,channel = <0>;
1872 #address-cells = <2>;
1873 #size-cells = <0>;
1874 interrupt-controller;
1875 #interrupt-cells = <4>;
1876 };
1877
1878 bus@0 {
1879 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple-pm-bus";
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xffffffff>;
1884
1885 pcie0: pcie@600000 {
1886 compatible = "qcom,pcie-msm8996";
1887 status = "disabled";
1888 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = <0x00 0xff>;
1890 num-lanes = <1>;
1891
1892 reg = <0x00600000 0x2000>,
1893 <0x0c000000 0xf1d>,
1894 <0x0c000f20 0xa8>,
1895 <0x0c100000 0x100000>;
1896 reg-names = "parf", "dbi", "elbi","config";
1897
1898 phys = <&pciephy_0>;
1899 phy-names = "pciephy";
1900
1901 #address-cells = <3>;
1902 #size-cells = <2>;
1903 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1904 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905
1906 device_type = "pci";
1907
1908 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-names = "msi";
1910 #interrupt-cells = <1>;
1911 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916
1917 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = <&pcie0_state_off>;
1920
1921 linux,pci-domain = <0>;
1922
1923 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928
1929 clock-names = "pipe",
1930 "aux",
1931 "cfg",
1932 "bus_master",
1933 "bus_slave";
1934
1935 pcie@0 {
1936 device_type = "pci";
1937 reg = <0x0 0x0 0x0 0x0 0x0>;
1938 bus-range = <0x01 0xff>;
1939
1940 #address-cells = <3>;
1941 #size-cells = <2>;
1942 ranges;
1943 };
1944 };
1945
1946 pcie1: pcie@608000 {
1947 compatible = "qcom,pcie-msm8996";
1948 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = <0x00 0xff>;
1950 num-lanes = <1>;
1951
1952 status = "disabled";
1953
1954 reg = <0x00608000 0x2000>,
1955 <0x0d000000 0xf1d>,
1956 <0x0d000f20 0xa8>,
1957 <0x0d100000 0x100000>;
1958
1959 reg-names = "parf", "dbi", "elbi","config";
1960
1961 phys = <&pciephy_1>;
1962 phy-names = "pciephy";
1963
1964 #address-cells = <3>;
1965 #size-cells = <2>;
1966 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1967 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968
1969 device_type = "pci";
1970
1971 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-names = "msi";
1973 #interrupt-cells = <1>;
1974 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979
1980 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = <&pcie1_state_off>;
1983
1984 linux,pci-domain = <1>;
1985
1986 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991
1992 clock-names = "pipe",
1993 "aux",
1994 "cfg",
1995 "bus_master",
1996 "bus_slave";
1997
1998 pcie@0 {
1999 device_type = "pci";
2000 reg = <0x0 0x0 0x0 0x0 0x0>;
2001 bus-range = <0x01 0xff>;
2002
2003 #address-cells = <3>;
2004 #size-cells = <2>;
2005 ranges;
2006 };
2007 };
2008
2009 pcie2: pcie@610000 {
2010 compatible = "qcom,pcie-msm8996";
2011 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = <0x00 0xff>;
2013 num-lanes = <1>;
2014 status = "disabled";
2015 reg = <0x00610000 0x2000>,
2016 <0x0e000000 0xf1d>,
2017 <0x0e000f20 0xa8>,
2018 <0x0e100000 0x100000>;
2019
2020 reg-names = "parf", "dbi", "elbi","config";
2021
2022 phys = <&pciephy_2>;
2023 phy-names = "pciephy";
2024
2025 #address-cells = <3>;
2026 #size-cells = <2>;
2027 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2028 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029
2030 device_type = "pci";
2031
2032 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-names = "msi";
2034 #interrupt-cells = <1>;
2035 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040
2041 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = <&pcie2_state_off>;
2044
2045 linux,pci-domain = <2>;
2046 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051
2052 clock-names = "pipe",
2053 "aux",
2054 "cfg",
2055 "bus_master",
2056 "bus_slave";
2057
2058 pcie@0 {
2059 device_type = "pci";
2060 reg = <0x0 0x0 0x0 0x0 0x0>;
2061 bus-range = <0x01 0xff>;
2062
2063 #address-cells = <3>;
2064 #size-cells = <2>;
2065 ranges;
2066 };
2067 };
2068 };
2069
2070 ufshc: ufshc@624000 {
2071 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2072 "jedec,ufs-2.0";
2073 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075
2076 phys = <&ufsphy>;
2077 phy-names = "ufsphy";
2078
2079 power-domains = <&gcc UFS_GDSC>;
2080
2081 clock-names =
2082 "core_clk",
2083 "bus_clk",
2084 "bus_aggr_clk",
2085 "iface_clk",
2086 "core_clk_unipro",
2087 "core_clk_ice",
2088 "ref_clk",
2089 "tx_lane0_sync_clk",
2090 "rx_lane0_sync_clk";
2091 clocks =
2092 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS_AHB_CLK>,
2096 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz =
2102 <100000000 200000000>,
2103 <0 0>,
2104 <0 0>,
2105 <0 0>,
2106 <75000000 150000000>,
2107 <150000000 300000000>,
2108 <0 0>,
2109 <0 0>,
2110 <0 0>;
2111
2112 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
2113 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
2114 interconnect-names = "ufs-ddr", "cpu-ufs";
2115
2116 lanes-per-direction = <1>;
2117 #reset-cells = <1>;
2118 status = "disabled";
2119 };
2120
2121 ufsphy: phy@627000 {
2122 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1000>;
2124
2125 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", "qref";
2127
2128 resets = <&ufshc 0>;
2129 reset-names = "ufsphy";
2130
2131 #clock-cells = <1>;
2132 #phy-cells = <0>;
2133
2134 status = "disabled";
2135 };
2136
2137 camss: camss@a34000 {
2138 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4>,
2141 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4>,
2143 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4>,
2145 <0x00a30000 0x100>,
2146 <0x00a30400 0x100>,
2147 <0x00a30800 0x100>,
2148 <0x00a30c00 0x100>,
2149 <0x00a31000 0x500>,
2150 <0x00a00020 0x10>,
2151 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0",
2154 "csiphy0_clk_mux",
2155 "csiphy1",
2156 "csiphy1_clk_mux",
2157 "csiphy2",
2158 "csiphy2_clk_mux",
2159 "csid0",
2160 "csid1",
2161 "csid2",
2162 "csid3",
2163 "ispif",
2164 "csi_clk_mux",
2165 "vfe0",
2166 "vfe1";
2167 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "csiphy0",
2178 "csiphy1",
2179 "csiphy2",
2180 "csid0",
2181 "csid1",
2182 "csid2",
2183 "csid3",
2184 "ispif",
2185 "vfe0",
2186 "vfe1";
2187 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ahb",
2226 "ispif_ahb",
2227 "csiphy0_timer",
2228 "csiphy1_timer",
2229 "csiphy2_timer",
2230 "csi0_ahb",
2231 "csi0",
2232 "csi0_phy",
2233 "csi0_pix",
2234 "csi0_rdi",
2235 "csi1_ahb",
2236 "csi1",
2237 "csi1_phy",
2238 "csi1_pix",
2239 "csi1_rdi",
2240 "csi2_ahb",
2241 "csi2",
2242 "csi2_phy",
2243 "csi2_pix",
2244 "csi2_rdi",
2245 "csi3_ahb",
2246 "csi3",
2247 "csi3_phy",
2248 "csi3_pix",
2249 "csi3_rdi",
2250 "ahb",
2251 "vfe0",
2252 "csi_vfe0",
2253 "vfe0_ahb",
2254 "vfe0_stream",
2255 "vfe1",
2256 "csi_vfe1",
2257 "vfe1_ahb",
2258 "vfe1_stream",
2259 "vfe_ahb",
2260 "vfe_axi";
2261 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1>,
2263 <&vfe_smmu 2>,
2264 <&vfe_smmu 3>;
2265 status = "disabled";
2266 ports {
2267 #address-cells = <1>;
2268 #size-cells = <0>;
2269 };
2270 };
2271
2272 cci: cci@a0c000 {
2273 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>;
2275 #size-cells = <0>;
2276 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_top_ahb",
2284 "cci_ahb",
2285 "cci",
2286 "camss_ahb";
2287 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled";
2293
2294 cci_i2c0: i2c-bus@0 {
2295 reg = <0>;
2296 clock-frequency = <400000>;
2297 #address-cells = <1>;
2298 #size-cells = <0>;
2299 };
2300
2301 cci_i2c1: i2c-bus@1 {
2302 reg = <1>;
2303 clock-frequency = <400000>;
2304 #address-cells = <1>;
2305 #size-cells = <0>;
2306 };
2307 };
2308
2309 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x10000>;
2312
2313 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>;
2318
2319 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2320 <&mmcc GPU_AHB_CLK>;
2321 clock-names = "bus", "iface";
2322
2323 power-domains = <&mmcc GPU_GDSC>;
2324 };
2325
2326 venus: video-codec@c00000 {
2327 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2337 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2338 interconnect-names = "video-mem", "cpu-cfg";
2339 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 0x01>,
2341 <&venus_smmu 0x0a>,
2342 <&venus_smmu 0x07>,
2343 <&venus_smmu 0x0e>,
2344 <&venus_smmu 0x0f>,
2345 <&venus_smmu 0x08>,
2346 <&venus_smmu 0x09>,
2347 <&venus_smmu 0x0b>,
2348 <&venus_smmu 0x0c>,
2349 <&venus_smmu 0x0d>,
2350 <&venus_smmu 0x10>,
2351 <&venus_smmu 0x11>,
2352 <&venus_smmu 0x21>,
2353 <&venus_smmu 0x28>,
2354 <&venus_smmu 0x29>,
2355 <&venus_smmu 0x2b>,
2356 <&venus_smmu 0x2c>,
2357 <&venus_smmu 0x2d>,
2358 <&venus_smmu 0x31>;
2359 memory-region = <&venus_mem>;
2360 status = "disabled";
2361
2362 video-decoder {
2363 compatible = "venus-decoder";
2364 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = "core";
2366 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 };
2368
2369 video-encoder {
2370 compatible = "venus-encoder";
2371 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = "core";
2373 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 };
2375 };
2376
2377 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x10000>;
2380
2381 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2387 <&mmcc SMMU_MDP_AHB_CLK>;
2388 clock-names = "bus", "iface";
2389
2390 power-domains = <&mmcc MDSS_GDSC>;
2391 };
2392
2393 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2407 <&mmcc SMMU_VIDEO_AHB_CLK>;
2408 clock-names = "bus", "iface";
2409 #iommu-cells = <1>;
2410 status = "okay";
2411 };
2412
2413 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x10000>;
2416
2417 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2423 <&mmcc SMMU_VFE_AHB_CLK>;
2424 clock-names = "bus", "iface";
2425 #iommu-cells = <1>;
2426 };
2427
2428 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>;
2432 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433
2434 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448
2449 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2450 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2451 clock-names = "bus", "iface";
2452 };
2453
2454 slpi_pil: remoteproc@1c00000 {
2455 compatible = "qcom,msm8996-slpi-pil";
2456 reg = <0x01c00000 0x4000>;
2457
2458 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2459 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2460 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2461 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2462 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2463 interrupt-names = "wdog",
2464 "fatal",
2465 "ready",
2466 "handover",
2467 "stop-ack";
2468
2469 clocks = <&xo_board>;
2470 clock-names = "xo";
2471
2472 memory-region = <&slpi_mem>;
2473
2474 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names = "stop";
2476
2477 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = "ssc_cx";
2479
2480 status = "disabled";
2481
2482 glink-edge {
2483 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
2484 label = "dsps";
2485 qcom,remote-pid = <3>;
2486 mboxes = <&apcs_glb 27>;
2487 };
2488
2489 smd-edge {
2490 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2491
2492 label = "dsps";
2493 mboxes = <&apcs_glb 25>;
2494 qcom,smd-edge = <3>;
2495 qcom,remote-pid = <3>;
2496 };
2497 };
2498
2499 mss_pil: remoteproc@2080000 {
2500 compatible = "qcom,msm8996-mss-pil";
2501 reg = <0x2080000 0x100>,
2502 <0x2180000 0x020>;
2503 reg-names = "qdsp6", "rmb";
2504
2505 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2506 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2507 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2508 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2509 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2510 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2511 interrupt-names = "wdog", "fatal", "ready",
2512 "handover", "stop-ack",
2513 "shutdown-ack";
2514
2515 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2516 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2517 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2518 <&xo_board>,
2519 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2520 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2521 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2522 <&rpmcc RPM_SMD_QDSS_CLK>;
2523 clock-names = "iface",
2524 "bus",
2525 "mem",
2526 "xo",
2527 "gpll0_mss",
2528 "snoc_axi",
2529 "mnoc_axi",
2530 "qdss";
2531
2532 resets = <&gcc GCC_MSS_RESTART>;
2533 reset-names = "mss_restart";
2534
2535 power-domains = <&rpmpd MSM8996_VDDCX>,
2536 <&rpmpd MSM8996_VDDMX>;
2537 power-domain-names = "cx", "mx";
2538
2539 qcom,smem-states = <&mpss_smp2p_out 0>;
2540 qcom,smem-state-names = "stop";
2541
2542 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2543
2544 status = "disabled";
2545
2546 mba {
2547 memory-region = <&mba_mem>;
2548 };
2549
2550 mpss {
2551 memory-region = <&mpss_mem>;
2552 };
2553
2554 metadata {
2555 memory-region = <&mdata_mem>;
2556 };
2557
2558 glink-edge {
2559 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
2560 label = "modem";
2561 qcom,remote-pid = <1>;
2562 mboxes = <&apcs_glb 15>;
2563 };
2564
2565 smd-edge {
2566 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2567
2568 label = "mpss";
2569 mboxes = <&apcs_glb 12>;
2570 qcom,smd-edge = <0>;
2571 qcom,remote-pid = <1>;
2572 };
2573 };
2574
2575 stm@3002000 {
2576 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x180000>;
2579 reg-names = "stm-base", "stm-stimulus-base";
2580
2581 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pclk", "atclk";
2583
2584 out-ports {
2585 port {
2586 stm_out: endpoint {
2587 remote-endpoint =
2588 <&funnel0_in>;
2589 };
2590 };
2591 };
2592 };
2593
2594 tpiu@3020000 {
2595 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x1000>;
2597
2598 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pclk", "atclk";
2600
2601 in-ports {
2602 port {
2603 tpiu_in: endpoint {
2604 remote-endpoint =
2605 <&replicator_out1>;
2606 };
2607 };
2608 };
2609 };
2610
2611 funnel@3021000 {
2612 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x1000>;
2614
2615 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pclk", "atclk";
2617
2618 in-ports {
2619 #address-cells = <1>;
2620 #size-cells = <0>;
2621
2622 port@7 {
2623 reg = <7>;
2624 funnel0_in: endpoint {
2625 remote-endpoint =
2626 <&stm_out>;
2627 };
2628 };
2629 };
2630
2631 out-ports {
2632 port {
2633 funnel0_out: endpoint {
2634 remote-endpoint =
2635 <&merge_funnel_in0>;
2636 };
2637 };
2638 };
2639 };
2640
2641 funnel@3022000 {
2642 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x1000>;
2644
2645 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pclk", "atclk";
2647
2648 in-ports {
2649 #address-cells = <1>;
2650 #size-cells = <0>;
2651
2652 port@6 {
2653 reg = <6>;
2654 funnel1_in: endpoint {
2655 remote-endpoint =
2656 <&apss_merge_funnel_out>;
2657 };
2658 };
2659 };
2660
2661 out-ports {
2662 port {
2663 funnel1_out: endpoint {
2664 remote-endpoint =
2665 <&merge_funnel_in1>;
2666 };
2667 };
2668 };
2669 };
2670
2671 funnel@3023000 {
2672 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x1000>;
2674
2675 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pclk", "atclk";
2677
2678 in-ports {
2679 port {
2680 funnel_in2_in_modem_etm: endpoint {
2681 remote-endpoint =
2682 <&modem_etm_out_funnel_in2>;
2683 };
2684 };
2685 };
2686
2687 out-ports {
2688 port {
2689 funnel2_out: endpoint {
2690 remote-endpoint =
2691 <&merge_funnel_in2>;
2692 };
2693 };
2694 };
2695 };
2696
2697 funnel@3025000 {
2698 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x1000>;
2700
2701 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pclk", "atclk";
2703
2704 in-ports {
2705 #address-cells = <1>;
2706 #size-cells = <0>;
2707
2708 port@0 {
2709 reg = <0>;
2710 merge_funnel_in0: endpoint {
2711 remote-endpoint =
2712 <&funnel0_out>;
2713 };
2714 };
2715
2716 port@1 {
2717 reg = <1>;
2718 merge_funnel_in1: endpoint {
2719 remote-endpoint =
2720 <&funnel1_out>;
2721 };
2722 };
2723
2724 port@2 {
2725 reg = <2>;
2726 merge_funnel_in2: endpoint {
2727 remote-endpoint =
2728 <&funnel2_out>;
2729 };
2730 };
2731 };
2732
2733 out-ports {
2734 port {
2735 merge_funnel_out: endpoint {
2736 remote-endpoint =
2737 <&etf_in>;
2738 };
2739 };
2740 };
2741 };
2742
2743 replicator@3026000 {
2744 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x1000>;
2746
2747 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pclk", "atclk";
2749
2750 in-ports {
2751 port {
2752 replicator_in: endpoint {
2753 remote-endpoint =
2754 <&etf_out>;
2755 };
2756 };
2757 };
2758
2759 out-ports {
2760 #address-cells = <1>;
2761 #size-cells = <0>;
2762
2763 port@0 {
2764 reg = <0>;
2765 replicator_out0: endpoint {
2766 remote-endpoint =
2767 <&etr_in>;
2768 };
2769 };
2770
2771 port@1 {
2772 reg = <1>;
2773 replicator_out1: endpoint {
2774 remote-endpoint =
2775 <&tpiu_in>;
2776 };
2777 };
2778 };
2779 };
2780
2781 etf@3027000 {
2782 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x1000>;
2784
2785 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pclk", "atclk";
2787
2788 in-ports {
2789 port {
2790 etf_in: endpoint {
2791 remote-endpoint =
2792 <&merge_funnel_out>;
2793 };
2794 };
2795 };
2796
2797 out-ports {
2798 port {
2799 etf_out: endpoint {
2800 remote-endpoint =
2801 <&replicator_in>;
2802 };
2803 };
2804 };
2805 };
2806
2807 etr@3028000 {
2808 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x1000>;
2810
2811 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather;
2814
2815 in-ports {
2816 port {
2817 etr_in: endpoint {
2818 remote-endpoint =
2819 <&replicator_out0>;
2820 };
2821 };
2822 };
2823 };
2824
2825 debug@3810000 {
2826 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x1000>;
2828
2829 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pclk";
2831
2832 cpu = <&CPU0>;
2833 };
2834
2835 etm@3840000 {
2836 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x1000>;
2838
2839 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pclk", "atclk";
2841
2842 cpu = <&CPU0>;
2843
2844 out-ports {
2845 port {
2846 etm0_out: endpoint {
2847 remote-endpoint =
2848 <&apss_funnel0_in0>;
2849 };
2850 };
2851 };
2852 };
2853
2854 debug@3910000 {
2855 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x1000>;
2857
2858 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pclk";
2860
2861 cpu = <&CPU1>;
2862 };
2863
2864 etm@3940000 {
2865 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x1000>;
2867
2868 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pclk", "atclk";
2870
2871 cpu = <&CPU1>;
2872
2873 out-ports {
2874 port {
2875 etm1_out: endpoint {
2876 remote-endpoint =
2877 <&apss_funnel0_in1>;
2878 };
2879 };
2880 };
2881 };
2882
2883 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x1000>;
2886
2887 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pclk", "atclk";
2889
2890 in-ports {
2891 #address-cells = <1>;
2892 #size-cells = <0>;
2893
2894 port@0 {
2895 reg = <0>;
2896 apss_funnel0_in0: endpoint {
2897 remote-endpoint = <&etm0_out>;
2898 };
2899 };
2900
2901 port@1 {
2902 reg = <1>;
2903 apss_funnel0_in1: endpoint {
2904 remote-endpoint = <&etm1_out>;
2905 };
2906 };
2907 };
2908
2909 out-ports {
2910 port {
2911 apss_funnel0_out: endpoint {
2912 remote-endpoint =
2913 <&apss_merge_funnel_in0>;
2914 };
2915 };
2916 };
2917 };
2918
2919 debug@3a10000 {
2920 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x1000>;
2922
2923 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pclk";
2925
2926 cpu = <&CPU2>;
2927 };
2928
2929 etm@3a40000 {
2930 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x1000>;
2932
2933 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pclk", "atclk";
2935
2936 cpu = <&CPU2>;
2937
2938 out-ports {
2939 port {
2940 etm2_out: endpoint {
2941 remote-endpoint =
2942 <&apss_funnel1_in0>;
2943 };
2944 };
2945 };
2946 };
2947
2948 debug@3b10000 {
2949 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x1000>;
2951
2952 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pclk";
2954
2955 cpu = <&CPU3>;
2956 };
2957
2958 etm@3b40000 {
2959 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x1000>;
2961
2962 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pclk", "atclk";
2964
2965 cpu = <&CPU3>;
2966
2967 out-ports {
2968 port {
2969 etm3_out: endpoint {
2970 remote-endpoint =
2971 <&apss_funnel1_in1>;
2972 };
2973 };
2974 };
2975 };
2976
2977 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x1000>;
2980
2981 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pclk", "atclk";
2983
2984 in-ports {
2985 #address-cells = <1>;
2986 #size-cells = <0>;
2987
2988 port@0 {
2989 reg = <0>;
2990 apss_funnel1_in0: endpoint {
2991 remote-endpoint = <&etm2_out>;
2992 };
2993 };
2994
2995 port@1 {
2996 reg = <1>;
2997 apss_funnel1_in1: endpoint {
2998 remote-endpoint = <&etm3_out>;
2999 };
3000 };
3001 };
3002
3003 out-ports {
3004 port {
3005 apss_funnel1_out: endpoint {
3006 remote-endpoint =
3007 <&apss_merge_funnel_in1>;
3008 };
3009 };
3010 };
3011 };
3012
3013 funnel@3bc0000 {
3014 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x1000>;
3016
3017 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pclk", "atclk";
3019
3020 in-ports {
3021 #address-cells = <1>;
3022 #size-cells = <0>;
3023
3024 port@0 {
3025 reg = <0>;
3026 apss_merge_funnel_in0: endpoint {
3027 remote-endpoint =
3028 <&apss_funnel0_out>;
3029 };
3030 };
3031
3032 port@1 {
3033 reg = <1>;
3034 apss_merge_funnel_in1: endpoint {
3035 remote-endpoint =
3036 <&apss_funnel1_out>;
3037 };
3038 };
3039 };
3040
3041 out-ports {
3042 port {
3043 apss_merge_funnel_out: endpoint {
3044 remote-endpoint =
3045 <&funnel1_in>;
3046 };
3047 };
3048 };
3049 };
3050
3051 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x90000>;
3054
3055 clock-names = "xo", "sys_apcs_aux";
3056 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3057
3058 #clock-cells = <1>;
3059 };
3060
3061 usb3: usb@6af8800 {
3062 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>;
3065 #size-cells = <1>;
3066 ranges;
3067
3068 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071
3072 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_USB30_SLEEP_CLK>,
3076 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3077 clock-names = "cfg_noc",
3078 "core",
3079 "iface",
3080 "sleep",
3081 "mock_utmi";
3082
3083 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates = <19200000>, <120000000>;
3086
3087 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3088 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3089 interconnect-names = "usb-ddr", "apps-usb";
3090
3091 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled";
3093
3094 usb3_dwc3: usb@6a00000 {
3095 compatible = "snps,dwc3";
3096 reg = <0x06a00000 0xcc00>;
3097 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsusb_phy1>, <&usb3phy>;
3099 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-threshold = /bits/ 8 <0>;
3101 snps,dis_u2_susphy_quirk;
3102 snps,dis_enblslpm_quirk;
3103 snps,is-utmi-l1-suspend;
3104 snps,parkmode-disable-ss-quirk;
3105 tx-fifo-resize;
3106 };
3107 };
3108
3109 usb3phy: phy@7410000 {
3110 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1000>;
3112
3113 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_USB3_CLKREF_CLK>,
3115 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3116 <&gcc GCC_USB3_PHY_PIPE_CLK>;
3117 clock-names = "aux",
3118 "ref",
3119 "cfg_ahb",
3120 "pipe";
3121 clock-output-names = "usb3_phy_pipe_clk_src";
3122 #clock-cells = <0>;
3123 #phy-cells = <0>;
3124
3125 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy",
3128 "phy_phy";
3129
3130 status = "disabled";
3131 };
3132
3133 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>;
3137
3138 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ahb", "ref";
3141
3142 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled";
3145 };
3146
3147 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>;
3151
3152 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ahb", "ref";
3155
3156 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled";
3159 };
3160
3161 sdhc1: mmc@7464900 {
3162 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "core";
3165
3166 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc_irq", "pwr_irq";
3169
3170 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3174 resets = <&gcc GCC_SDCC1_BCR>;
3175
3176 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_state_off>;
3179
3180 bus-width = <8>;
3181 non-removable;
3182 status = "disabled";
3183 };
3184
3185 sdhc2: mmc@74a4900 {
3186 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "core";
3189
3190 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc_irq", "pwr_irq";
3193
3194 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3198 resets = <&gcc GCC_SDCC2_BCR>;
3199
3200 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_state_off>;
3203
3204 bus-width = <4>;
3205 status = "disabled";
3206 };
3207
3208 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_clk";
3214 qcom,controlled-remotely;
3215 #dma-cells = <1>;
3216 qcom,ee = <0>;
3217 };
3218
3219 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", "iface";
3226 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx";
3231 status = "disabled";
3232 };
3233
3234 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", "iface";
3241 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx";
3246 #address-cells = <1>;
3247 #size-cells = <0>;
3248 status = "disabled";
3249 };
3250
3251 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3256 <&gcc GCC_BLSP1_AHB_CLK>;
3257 clock-names = "core", "iface";
3258 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx";
3263 #address-cells = <1>;
3264 #size-cells = <0>;
3265 status = "disabled";
3266 };
3267
3268 blsp1_i2c6: i2c@757a000 {
3269 compatible = "qcom,i2c-qup-v2.2.1";
3270 reg = <0x757a000 0x1000>;
3271 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3272 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3273 <&gcc GCC_BLSP1_AHB_CLK>;
3274 clock-names = "core", "iface";
3275 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i2c6_default>;
3277 pinctrl-1 = <&blsp1_i2c6_sleep>;
3278 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3279 dma-names = "tx", "rx";
3280 #address-cells = <1>;
3281 #size-cells = <0>;
3282 status = "disabled";
3283 };
3284
3285 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_clk";
3291 qcom,controlled-remotely;
3292 #dma-cells = <1>;
3293 qcom,ee = <0>;
3294 };
3295
3296 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", "iface";
3303 status = "disabled";
3304 };
3305
3306 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", "iface";
3313 status = "disabled";
3314 };
3315
3316 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3321 <&gcc GCC_BLSP2_AHB_CLK>;
3322 clock-names = "core", "iface";
3323 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx";
3328 #address-cells = <1>;
3329 #size-cells = <0>;
3330 status = "disabled";
3331 };
3332
3333 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3338 <&gcc GCC_BLSP2_AHB_CLK>;
3339 clock-names = "core", "iface";
3340 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx";
3345 #address-cells = <1>;
3346 #size-cells = <0>;
3347 status = "disabled";
3348 };
3349
3350 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3355 <&gcc GCC_BLSP2_AHB_CLK>;
3356 clock-names = "core", "iface";
3357 clock-frequency = <400000>;
3358 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx";
3363 #address-cells = <1>;
3364 #size-cells = <0>;
3365 status = "disabled";
3366 };
3367
3368 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3373 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", "iface";
3375 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx";
3379 #address-cells = <1>;
3380 #size-cells = <0>;
3381 status = "disabled";
3382 };
3383
3384 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3389 <&gcc GCC_BLSP2_AHB_CLK>;
3390 clock-names = "core", "iface";
3391 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx";
3396 #address-cells = <1>;
3397 #size-cells = <0>;
3398 status = "disabled";
3399 };
3400
3401 blsp2_spi6: spi@75ba000 {
3402 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", "iface";
3408 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx";
3413 #address-cells = <1>;
3414 #size-cells = <0>;
3415 status = "disabled";
3416 };
3417
3418 usb2: usb@76f8800 {
3419 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>;
3422 #size-cells = <1>;
3423 ranges;
3424
3425 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
3426 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
3427 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
3428 interrupt-names = "pwr_event",
3429 "qusb2_phy",
3430 "hs_phy_irq";
3431
3432 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_noc",
3438 "core",
3439 "iface",
3440 "sleep",
3441 "mock_utmi";
3442
3443 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates = <19200000>, <60000000>;
3446
3447 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled";
3450
3451 usb2_dwc3: usb@7600000 {
3452 compatible = "snps,dwc3";
3453 reg = <0x07600000 0xcc00>;
3454 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsusb_phy2>;
3456 phy-names = "usb2-phy";
3457 maximum-speed = "high-speed";
3458 snps,dis_u2_susphy_quirk;
3459 snps,dis_enblslpm_quirk;
3460 };
3461 };
3462
3463 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remotely;
3466 reg = <0x09184000 0x32000>;
3467 num-channels = <31>;
3468 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>;
3470 qcom,ee = <1>;
3471 qcom,num-ees = <2>;
3472 };
3473
3474 slim_msm: slim-ngd@91c0000 {
3475 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2c000>;
3477 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3478 dmas = <&slimbam 3>, <&slimbam 4>;
3479 dma-names = "rx", "tx";
3480 #address-cells = <1>;
3481 #size-cells = <0>;
3482
3483 status = "disabled";
3484 };
3485
3486 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x80000>;
3489
3490 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3492 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3493 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3494 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wdog", "fatal", "ready",
3496 "handover", "stop-ack";
3497
3498 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3499 clock-names = "xo";
3500
3501 memory-region = <&adsp_mem>;
3502
3503 qcom,smem-states = <&adsp_smp2p_out 0>;
3504 qcom,smem-state-names = "stop";
3505
3506 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = "cx";
3508
3509 status = "disabled";
3510
3511 glink-edge {
3512 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3513 label = "lpass";
3514 qcom,remote-pid = <2>;
3515 mboxes = <&apcs_glb 9>;
3516 };
3517
3518
3519 smd-edge {
3520 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521
3522 label = "lpass";
3523 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge = <1>;
3525 qcom,remote-pid = <2>;
3526
3527 apr {
3528 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compatible = "qcom,apr-v2";
3530 qcom,smd-channels = "apr_audio_svc";
3531 qcom,domain = <APR_DOMAIN_ADSP>;
3532 #address-cells = <1>;
3533 #size-cells = <0>;
3534
3535 service@3 {
3536 reg = <APR_SVC_ADSP_CORE>;
3537 compatible = "qcom,q6core";
3538 };
3539
3540 q6afe: service@4 {
3541 compatible = "qcom,q6afe";
3542 reg = <APR_SVC_AFE>;
3543 q6afedai: dais {
3544 compatible = "qcom,q6afe-dais";
3545 #address-cells = <1>;
3546 #size-cells = <0>;
3547 #sound-dai-cells = <1>;
3548 dai@1 {
3549 reg = <1>;
3550 };
3551 };
3552 };
3553
3554 q6asm: service@7 {
3555 compatible = "qcom,q6asm";
3556 reg = <APR_SVC_ASM>;
3557 q6asmdai: dais {
3558 compatible = "qcom,q6asm-dais";
3559 #address-cells = <1>;
3560 #size-cells = <0>;
3561 #sound-dai-cells = <1>;
3562 iommus = <&lpass_q6_smmu 1>;
3563 };
3564 };
3565
3566 q6adm: service@8 {
3567 compatible = "qcom,q6adm";
3568 reg = <APR_SVC_ADM>;
3569 q6routing: routing {
3570 compatible = "qcom,q6adm-routing";
3571 #sound-dai-cells = <0>;
3572 };
3573 };
3574 };
3575
3576 fastrpc {
3577 compatible = "qcom,fastrpc";
3578 qcom,smd-channels = "fastrpcsmd-apps-dsp";
3579 label = "adsp";
3580 qcom,non-secure-domain;
3581 #address-cells = <1>;
3582 #size-cells = <0>;
3583
3584 cb@5 {
3585 compatible = "qcom,fastrpc-compute-cb";
3586 reg = <5>;
3587 iommus = <&lpass_q6_smmu 5>;
3588 };
3589
3590 cb@6 {
3591 compatible = "qcom,fastrpc-compute-cb";
3592 reg = <6>;
3593 iommus = <&lpass_q6_smmu 6>;
3594 };
3595
3596 cb@7 {
3597 compatible = "qcom,fastrpc-compute-cb";
3598 reg = <7>;
3599 iommus = <&lpass_q6_smmu 7>;
3600 };
3601
3602 cb@8 {
3603 compatible = "qcom,fastrpc-compute-cb";
3604 reg = <8>;
3605 iommus = <&lpass_q6_smmu 8>;
3606 };
3607
3608 cb@9 {
3609 compatible = "qcom,fastrpc-compute-cb";
3610 reg = <9>;
3611 iommus = <&lpass_q6_smmu 9>;
3612 };
3613
3614 cb@10 {
3615 compatible = "qcom,fastrpc-compute-cb";
3616 reg = <10>;
3617 iommus = <&lpass_q6_smmu 10>;
3618 };
3619
3620 cb@11 {
3621 compatible = "qcom,fastrpc-compute-cb";
3622 reg = <11>;
3623 iommus = <&lpass_q6_smmu 11>;
3624 };
3625
3626 cb@12 {
3627 compatible = "qcom,fastrpc-compute-cb";
3628 reg = <12>;
3629 iommus = <&lpass_q6_smmu 12>;
3630 };
3631 };
3632 };
3633 };
3634
3635 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1000>;
3638
3639 #mbox-cells = <1>;
3640 #clock-cells = <0>;
3641 };
3642
3643 timer@9840000 {
3644 #address-cells = <1>;
3645 #size-cells = <1>;
3646 ranges;
3647 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19200000>;
3650
3651 frame@9850000 {
3652 frame-number = <0>;
3653 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x09850000 0x1000>,
3656 <0x09860000 0x1000>;
3657 };
3658
3659 frame@9870000 {
3660 frame-number = <1>;
3661 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x09870000 0x1000>;
3663 status = "disabled";
3664 };
3665
3666 frame@9880000 {
3667 frame-number = <2>;
3668 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x09880000 0x1000>;
3670 status = "disabled";
3671 };
3672
3673 frame@9890000 {
3674 frame-number = <3>;
3675 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x09890000 0x1000>;
3677 status = "disabled";
3678 };
3679
3680 frame@98a0000 {
3681 frame-number = <4>;
3682 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a0000 0x1000>;
3684 status = "disabled";
3685 };
3686
3687 frame@98b0000 {
3688 frame-number = <5>;
3689 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b0000 0x1000>;
3691 status = "disabled";
3692 };
3693
3694 frame@98c0000 {
3695 frame-number = <6>;
3696 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c0000 0x1000>;
3698 status = "disabled";
3699 };
3700 };
3701
3702 saw3: syscon@9a10000 {
3703 compatible = "syscon";
3704 reg = <0x09a10000 0x1000>;
3705 };
3706
3707 cbf: clock-controller@9a11000 {
3708 compatible = "qcom,msm8996-cbf";
3709 reg = <0x09a11000 0x10000>;
3710 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3711 #clock-cells = <0>;
3712 #interconnect-cells = <1>;
3713 };
3714
3715 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3>;
3718 interrupt-controller;
3719 #redistributor-regions = <1>;
3720 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 };
3725 };
3726
3727 sound: sound {
3728 };
3729
3730 thermal-zones {
3731 cpu0-thermal {
3732 polling-delay-passive = <250>;
3733
3734 thermal-sensors = <&tsens0 3>;
3735
3736 trips {
3737 cpu0_alert0: trip-point0 {
3738 temperature = <75000>;
3739 hysteresis = <2000>;
3740 type = "passive";
3741 };
3742
3743 cpu0_crit: cpu-crit {
3744 temperature = <110000>;
3745 hysteresis = <2000>;
3746 type = "critical";
3747 };
3748 };
3749 };
3750
3751 cpu1-thermal {
3752 polling-delay-passive = <250>;
3753
3754 thermal-sensors = <&tsens0 5>;
3755
3756 trips {
3757 cpu1_alert0: trip-point0 {
3758 temperature = <75000>;
3759 hysteresis = <2000>;
3760 type = "passive";
3761 };
3762
3763 cpu1_crit: cpu-crit {
3764 temperature = <110000>;
3765 hysteresis = <2000>;
3766 type = "critical";
3767 };
3768 };
3769 };
3770
3771 cpu2-thermal {
3772 polling-delay-passive = <250>;
3773
3774 thermal-sensors = <&tsens0 8>;
3775
3776 trips {
3777 cpu2_alert0: trip-point0 {
3778 temperature = <75000>;
3779 hysteresis = <2000>;
3780 type = "passive";
3781 };
3782
3783 cpu2_crit: cpu-crit {
3784 temperature = <110000>;
3785 hysteresis = <2000>;
3786 type = "critical";
3787 };
3788 };
3789 };
3790
3791 cpu3-thermal {
3792 polling-delay-passive = <250>;
3793
3794 thermal-sensors = <&tsens0 10>;
3795
3796 trips {
3797 cpu3_alert0: trip-point0 {
3798 temperature = <75000>;
3799 hysteresis = <2000>;
3800 type = "passive";
3801 };
3802
3803 cpu3_crit: cpu-crit {
3804 temperature = <110000>;
3805 hysteresis = <2000>;
3806 type = "critical";
3807 };
3808 };
3809 };
3810
3811 gpu-top-thermal {
3812 polling-delay-passive = <250>;
3813
3814 thermal-sensors = <&tsens1 6>;
3815
3816 trips {
3817 gpu1_alert0: trip-point0 {
3818 temperature = <90000>;
3819 hysteresis = <2000>;
3820 type = "passive";
3821 };
3822 };
3823
3824 cooling-maps {
3825 map0 {
3826 trip = <&gpu1_alert0>;
3827 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 };
3829 };
3830 };
3831
3832 gpu-bottom-thermal {
3833 polling-delay-passive = <250>;
3834
3835 thermal-sensors = <&tsens1 7>;
3836
3837 trips {
3838 gpu2_alert0: trip-point0 {
3839 temperature = <90000>;
3840 hysteresis = <2000>;
3841 type = "passive";
3842 };
3843 };
3844
3845 cooling-maps {
3846 map0 {
3847 trip = <&gpu2_alert0>;
3848 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 };
3850 };
3851 };
3852
3853 m4m-thermal {
3854 polling-delay-passive = <250>;
3855
3856 thermal-sensors = <&tsens0 1>;
3857
3858 trips {
3859 m4m_alert0: trip-point0 {
3860 temperature = <90000>;
3861 hysteresis = <2000>;
3862 type = "hot";
3863 };
3864 };
3865 };
3866
3867 l3-or-venus-thermal {
3868 polling-delay-passive = <250>;
3869
3870 thermal-sensors = <&tsens0 2>;
3871
3872 trips {
3873 l3_or_venus_alert0: trip-point0 {
3874 temperature = <90000>;
3875 hysteresis = <2000>;
3876 type = "hot";
3877 };
3878 };
3879 };
3880
3881 cluster0-l2-thermal {
3882 polling-delay-passive = <250>;
3883
3884 thermal-sensors = <&tsens0 7>;
3885
3886 trips {
3887 cluster0_l2_alert0: trip-point0 {
3888 temperature = <90000>;
3889 hysteresis = <2000>;
3890 type = "hot";
3891 };
3892 };
3893 };
3894
3895 cluster1-l2-thermal {
3896 polling-delay-passive = <250>;
3897
3898 thermal-sensors = <&tsens0 12>;
3899
3900 trips {
3901 cluster1_l2_alert0: trip-point0 {
3902 temperature = <90000>;
3903 hysteresis = <2000>;
3904 type = "hot";
3905 };
3906 };
3907 };
3908
3909 camera-thermal {
3910 polling-delay-passive = <250>;
3911
3912 thermal-sensors = <&tsens1 1>;
3913
3914 trips {
3915 camera_alert0: trip-point0 {
3916 temperature = <90000>;
3917 hysteresis = <2000>;
3918 type = "hot";
3919 };
3920 };
3921 };
3922
3923 q6-dsp-thermal {
3924 polling-delay-passive = <250>;
3925
3926 thermal-sensors = <&tsens1 2>;
3927
3928 trips {
3929 q6_dsp_alert0: trip-point0 {
3930 temperature = <90000>;
3931 hysteresis = <2000>;
3932 type = "hot";
3933 };
3934 };
3935 };
3936
3937 mem-thermal {
3938 polling-delay-passive = <250>;
3939
3940 thermal-sensors = <&tsens1 3>;
3941
3942 trips {
3943 mem_alert0: trip-point0 {
3944 temperature = <90000>;
3945 hysteresis = <2000>;
3946 type = "hot";
3947 };
3948 };
3949 };
3950
3951 modemtx-thermal {
3952 polling-delay-passive = <250>;
3953
3954 thermal-sensors = <&tsens1 4>;
3955
3956 trips {
3957 modemtx_alert0: trip-point0 {
3958 temperature = <90000>;
3959 hysteresis = <2000>;
3960 type = "hot";
3961 };
3962 };
3963 };
3964 };
3965
3966 timer {
3967 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 };
3973 };
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