1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8180x.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #include <dt-bindings/thermal/thermal.h>
19
20 / {
21 interrupt-parent = <&intc>;
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 clocks {
27 xo_board_clk: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <38400000>;
31 };
32
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32764>;
37 clock-output-names = "sleep_clk";
38 };
39 };
40
41 cpus {
42 #address-cells = <2>;
43 #size-cells = <0>;
44
45 CPU0: cpu@0 {
46 device_type = "cpu";
47 compatible = "qcom,kryo485";
48 reg = <0x0 0x0>;
49 enable-method = "psci";
50 capacity-dmips-mhz = <602>;
51 next-level-cache = <&L2_0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
53 operating-points-v2 = <&cpu0_opp_table>;
54 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
55 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
56 power-domains = <&CPU_PD0>;
57 power-domain-names = "psci";
58 #cooling-cells = <2>;
59 clocks = <&cpufreq_hw 0>;
60
61 L2_0: l2-cache {
62 compatible = "cache";
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&L3_0>;
66 L3_0: l3-cache {
67 compatible = "cache";
68 cache-level = <3>;
69 cache-unified;
70 };
71 };
72 };
73
74 CPU1: cpu@100 {
75 device_type = "cpu";
76 compatible = "qcom,kryo485";
77 reg = <0x0 0x100>;
78 enable-method = "psci";
79 capacity-dmips-mhz = <602>;
80 next-level-cache = <&L2_100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
82 operating-points-v2 = <&cpu0_opp_table>;
83 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
84 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
85 power-domains = <&CPU_PD1>;
86 power-domain-names = "psci";
87 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 0>;
89
90 L2_100: l2-cache {
91 compatible = "cache";
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&L3_0>;
95 };
96
97 };
98
99 CPU2: cpu@200 {
100 device_type = "cpu";
101 compatible = "qcom,kryo485";
102 reg = <0x0 0x200>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <602>;
105 next-level-cache = <&L2_200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 operating-points-v2 = <&cpu0_opp_table>;
108 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
109 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
110 power-domains = <&CPU_PD2>;
111 power-domain-names = "psci";
112 #cooling-cells = <2>;
113 clocks = <&cpufreq_hw 0>;
114
115 L2_200: l2-cache {
116 compatible = "cache";
117 cache-level = <2>;
118 cache-unified;
119 next-level-cache = <&L3_0>;
120 };
121 };
122
123 CPU3: cpu@300 {
124 device_type = "cpu";
125 compatible = "qcom,kryo485";
126 reg = <0x0 0x300>;
127 enable-method = "psci";
128 capacity-dmips-mhz = <602>;
129 next-level-cache = <&L2_300>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
132 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
134 power-domains = <&CPU_PD3>;
135 power-domain-names = "psci";
136 #cooling-cells = <2>;
137 clocks = <&cpufreq_hw 0>;
138
139 L2_300: l2-cache {
140 compatible = "cache";
141 cache-unified;
142 cache-level = <2>;
143 next-level-cache = <&L3_0>;
144 };
145 };
146
147 CPU4: cpu@400 {
148 device_type = "cpu";
149 compatible = "qcom,kryo485";
150 reg = <0x0 0x400>;
151 enable-method = "psci";
152 capacity-dmips-mhz = <1024>;
153 next-level-cache = <&L2_400>;
154 qcom,freq-domain = <&cpufreq_hw 1>;
155 operating-points-v2 = <&cpu4_opp_table>;
156 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
157 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
158 power-domains = <&CPU_PD4>;
159 power-domain-names = "psci";
160 #cooling-cells = <2>;
161 clocks = <&cpufreq_hw 1>;
162
163 L2_400: l2-cache {
164 compatible = "cache";
165 cache-unified;
166 cache-level = <2>;
167 next-level-cache = <&L3_0>;
168 };
169 };
170
171 CPU5: cpu@500 {
172 device_type = "cpu";
173 compatible = "qcom,kryo485";
174 reg = <0x0 0x500>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <1024>;
177 next-level-cache = <&L2_500>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
180 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
181 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
182 power-domains = <&CPU_PD5>;
183 power-domain-names = "psci";
184 #cooling-cells = <2>;
185 clocks = <&cpufreq_hw 1>;
186
187 L2_500: l2-cache {
188 compatible = "cache";
189 cache-unified;
190 cache-level = <2>;
191 next-level-cache = <&L3_0>;
192 };
193 };
194
195 CPU6: cpu@600 {
196 device_type = "cpu";
197 compatible = "qcom,kryo485";
198 reg = <0x0 0x600>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 next-level-cache = <&L2_600>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
204 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
206 power-domains = <&CPU_PD6>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 clocks = <&cpufreq_hw 1>;
210
211 L2_600: l2-cache {
212 compatible = "cache";
213 cache-unified;
214 cache-level = <2>;
215 next-level-cache = <&L3_0>;
216 };
217 };
218
219 CPU7: cpu@700 {
220 device_type = "cpu";
221 compatible = "qcom,kryo485";
222 reg = <0x0 0x700>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1024>;
225 next-level-cache = <&L2_700>;
226 qcom,freq-domain = <&cpufreq_hw 1>;
227 operating-points-v2 = <&cpu4_opp_table>;
228 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
230 power-domains = <&CPU_PD7>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
233 clocks = <&cpufreq_hw 1>;
234
235 L2_700: l2-cache {
236 compatible = "cache";
237 cache-unified;
238 cache-level = <2>;
239 next-level-cache = <&L3_0>;
240 };
241 };
242
243 cpu-map {
244 cluster0 {
245 core0 {
246 cpu = <&CPU0>;
247 };
248
249 core1 {
250 cpu = <&CPU1>;
251 };
252
253 core2 {
254 cpu = <&CPU2>;
255 };
256
257 core3 {
258 cpu = <&CPU3>;
259 };
260
261 core4 {
262 cpu = <&CPU4>;
263 };
264
265 core5 {
266 cpu = <&CPU5>;
267 };
268
269 core6 {
270 cpu = <&CPU6>;
271 };
272
273 core7 {
274 cpu = <&CPU7>;
275 };
276 };
277 };
278
279 idle-states {
280 entry-method = "psci";
281
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 arm,psci-suspend-param = <0x40000004>;
285 entry-latency-us = <355>;
286 exit-latency-us = <909>;
287 min-residency-us = <3934>;
288 local-timer-stop;
289 };
290
291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 arm,psci-suspend-param = <0x40000004>;
294 entry-latency-us = <2411>;
295 exit-latency-us = <1461>;
296 min-residency-us = <4488>;
297 local-timer-stop;
298 };
299 };
300
301 domain-idle-states {
302 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
303 compatible = "domain-idle-state";
304 arm,psci-suspend-param = <0x41000044>;
305 entry-latency-us = <3300>;
306 exit-latency-us = <3300>;
307 min-residency-us = <6000>;
308 };
309
310 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
311 compatible = "domain-idle-state";
312 arm,psci-suspend-param = <0x4100a344>;
313 entry-latency-us = <3263>;
314 exit-latency-us = <6562>;
315 min-residency-us = <9987>;
316 };
317 };
318 };
319
320 cpu0_opp_table: opp-table-cpu0 {
321 compatible = "operating-points-v2";
322 opp-shared;
323
324 opp-300000000 {
325 opp-hz = /bits/ 64 <300000000>;
326 opp-peak-kBps = <800000 9600000>;
327 };
328
329 opp-422400000 {
330 opp-hz = /bits/ 64 <422400000>;
331 opp-peak-kBps = <800000 9600000>;
332 };
333
334 opp-537600000 {
335 opp-hz = /bits/ 64 <537600000>;
336 opp-peak-kBps = <800000 12902400>;
337 };
338
339 opp-652800000 {
340 opp-hz = /bits/ 64 <652800000>;
341 opp-peak-kBps = <800000 12902400>;
342 };
343
344 opp-768000000 {
345 opp-hz = /bits/ 64 <768000000>;
346 opp-peak-kBps = <800000 15974400>;
347 };
348
349 opp-883200000 {
350 opp-hz = /bits/ 64 <883200000>;
351 opp-peak-kBps = <1804000 19660800>;
352 };
353
354 opp-998400000 {
355 opp-hz = /bits/ 64 <998400000>;
356 opp-peak-kBps = <1804000 19660800>;
357 };
358
359 opp-1113600000 {
360 opp-hz = /bits/ 64 <1113600000>;
361 opp-peak-kBps = <1804000 22732800>;
362 };
363
364 opp-1228800000 {
365 opp-hz = /bits/ 64 <1228800000>;
366 opp-peak-kBps = <1804000 22732800>;
367 };
368
369 opp-1363200000 {
370 opp-hz = /bits/ 64 <1363200000>;
371 opp-peak-kBps = <2188000 25804800>;
372 };
373
374 opp-1478400000 {
375 opp-hz = /bits/ 64 <1478400000>;
376 opp-peak-kBps = <2188000 31948800>;
377 };
378
379 opp-1574400000 {
380 opp-hz = /bits/ 64 <1574400000>;
381 opp-peak-kBps = <3072000 31948800>;
382 };
383
384 opp-1670400000 {
385 opp-hz = /bits/ 64 <1670400000>;
386 opp-peak-kBps = <3072000 31948800>;
387 };
388
389 opp-1766400000 {
390 opp-hz = /bits/ 64 <1766400000>;
391 opp-peak-kBps = <3072000 31948800>;
392 };
393 };
394
395 cpu4_opp_table: opp-table-cpu4 {
396 compatible = "operating-points-v2";
397 opp-shared;
398
399 opp-825600000 {
400 opp-hz = /bits/ 64 <825600000>;
401 opp-peak-kBps = <1804000 15974400>;
402 };
403
404 opp-940800000 {
405 opp-hz = /bits/ 64 <940800000>;
406 opp-peak-kBps = <2188000 19660800>;
407 };
408
409 opp-1056000000 {
410 opp-hz = /bits/ 64 <1056000000>;
411 opp-peak-kBps = <2188000 22732800>;
412 };
413
414 opp-1171200000 {
415 opp-hz = /bits/ 64 <1171200000>;
416 opp-peak-kBps = <3072000 25804800>;
417 };
418
419 opp-1286400000 {
420 opp-hz = /bits/ 64 <1286400000>;
421 opp-peak-kBps = <3072000 31948800>;
422 };
423
424 opp-1420800000 {
425 opp-hz = /bits/ 64 <1420800000>;
426 opp-peak-kBps = <4068000 31948800>;
427 };
428
429 opp-1536000000 {
430 opp-hz = /bits/ 64 <1536000000>;
431 opp-peak-kBps = <4068000 31948800>;
432 };
433
434 opp-1651200000 {
435 opp-hz = /bits/ 64 <1651200000>;
436 opp-peak-kBps = <4068000 40550400>;
437 };
438
439 opp-1766400000 {
440 opp-hz = /bits/ 64 <1766400000>;
441 opp-peak-kBps = <4068000 40550400>;
442 };
443
444 opp-1881600000 {
445 opp-hz = /bits/ 64 <1881600000>;
446 opp-peak-kBps = <4068000 43008000>;
447 };
448
449 opp-1996800000 {
450 opp-hz = /bits/ 64 <1996800000>;
451 opp-peak-kBps = <6220000 43008000>;
452 };
453
454 opp-2131200000 {
455 opp-hz = /bits/ 64 <2131200000>;
456 opp-peak-kBps = <6220000 49152000>;
457 };
458
459 opp-2246400000 {
460 opp-hz = /bits/ 64 <2246400000>;
461 opp-peak-kBps = <7216000 49152000>;
462 };
463
464 opp-2361600000 {
465 opp-hz = /bits/ 64 <2361600000>;
466 opp-peak-kBps = <8368000 49152000>;
467 };
468
469 opp-2457600000 {
470 opp-hz = /bits/ 64 <2457600000>;
471 opp-peak-kBps = <8368000 51609600>;
472 };
473
474 opp-2553600000 {
475 opp-hz = /bits/ 64 <2553600000>;
476 opp-peak-kBps = <8368000 51609600>;
477 };
478
479 opp-2649600000 {
480 opp-hz = /bits/ 64 <2649600000>;
481 opp-peak-kBps = <8368000 51609600>;
482 };
483
484 opp-2745600000 {
485 opp-hz = /bits/ 64 <2745600000>;
486 opp-peak-kBps = <8368000 51609600>;
487 };
488
489 opp-2841600000 {
490 opp-hz = /bits/ 64 <2841600000>;
491 opp-peak-kBps = <8368000 51609600>;
492 };
493
494 opp-2918400000 {
495 opp-hz = /bits/ 64 <2918400000>;
496 opp-peak-kBps = <8368000 51609600>;
497 };
498
499 opp-2995200000 {
500 opp-hz = /bits/ 64 <2995200000>;
501 opp-peak-kBps = <8368000 51609600>;
502 };
503 };
504
505 firmware {
506 scm: scm {
507 compatible = "qcom,scm-sc8180x", "qcom,scm";
508 };
509 };
510
511 camnoc_virt: interconnect-camnoc-virt {
512 compatible = "qcom,sc8180x-camnoc-virt";
513 #interconnect-cells = <2>;
514 qcom,bcm-voters = <&apps_bcm_voter>;
515 };
516
517 mc_virt: interconnect-mc-virt {
518 compatible = "qcom,sc8180x-mc-virt";
519 #interconnect-cells = <2>;
520 qcom,bcm-voters = <&apps_bcm_voter>;
521 };
522
523 qup_virt: interconnect-qup-virt {
524 compatible = "qcom,sc8180x-qup-virt";
525 #interconnect-cells = <2>;
526 qcom,bcm-voters = <&apps_bcm_voter>;
527 };
528
529 memory@80000000 {
530 device_type = "memory";
531 /* We expect the bootloader to fill in the size */
532 reg = <0x0 0x80000000 0x0 0x0>;
533 };
534
535 pmu {
536 compatible = "arm,armv8-pmuv3";
537 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
538 };
539
540 psci {
541 compatible = "arm,psci-1.0";
542 method = "smc";
543
544 CPU_PD0: power-domain-cpu0 {
545 #power-domain-cells = <0>;
546 power-domains = <&CLUSTER_PD>;
547 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
548 };
549
550 CPU_PD1: power-domain-cpu1 {
551 #power-domain-cells = <0>;
552 power-domains = <&CLUSTER_PD>;
553 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
554 };
555
556 CPU_PD2: power-domain-cpu2 {
557 #power-domain-cells = <0>;
558 power-domains = <&CLUSTER_PD>;
559 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
560 };
561
562 CPU_PD3: power-domain-cpu3 {
563 #power-domain-cells = <0>;
564 power-domains = <&CLUSTER_PD>;
565 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
566 };
567
568 CPU_PD4: power-domain-cpu4 {
569 #power-domain-cells = <0>;
570 power-domains = <&CLUSTER_PD>;
571 domain-idle-states = <&BIG_CPU_SLEEP_0>;
572 };
573
574 CPU_PD5: power-domain-cpu5 {
575 #power-domain-cells = <0>;
576 power-domains = <&CLUSTER_PD>;
577 domain-idle-states = <&BIG_CPU_SLEEP_0>;
578 };
579
580 CPU_PD6: power-domain-cpu6 {
581 #power-domain-cells = <0>;
582 power-domains = <&CLUSTER_PD>;
583 domain-idle-states = <&BIG_CPU_SLEEP_0>;
584 };
585
586 CPU_PD7: power-domain-cpu7 {
587 #power-domain-cells = <0>;
588 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = <&BIG_CPU_SLEEP_0>;
590 };
591
592 CLUSTER_PD: power-domain-cpu-cluster0 {
593 #power-domain-cells = <0>;
594 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
595 };
596 };
597
598 reserved-memory {
599 #address-cells = <2>;
600 #size-cells = <2>;
601 ranges;
602
603 hyp_mem: hyp@85700000 {
604 reg = <0x0 0x85700000 0x0 0x600000>;
605 no-map;
606 };
607
608 xbl_mem: xbl@85d00000 {
609 reg = <0x0 0x85d00000 0x0 0x140000>;
610 no-map;
611 };
612
613 aop_mem: aop@85f00000 {
614 reg = <0x0 0x85f00000 0x0 0x20000>;
615 no-map;
616 };
617
618 aop_cmd_db: cmd-db@85f20000 {
619 compatible = "qcom,cmd-db";
620 reg = <0x0 0x85f20000 0x0 0x20000>;
621 no-map;
622 };
623
624 reserved@85f40000 {
625 reg = <0x0 0x85f40000 0x0 0x10000>;
626 no-map;
627 };
628
629 smem_mem: smem@86000000 {
630 compatible = "qcom,smem";
631 reg = <0x0 0x86000000 0x0 0x200000>;
632 no-map;
633 hwlocks = <&tcsr_mutex 3>;
634 };
635
636 reserved@86200000 {
637 reg = <0x0 0x86200000 0x0 0x3900000>;
638 no-map;
639 };
640
641 reserved@89b00000 {
642 reg = <0x0 0x89b00000 0x0 0x1c00000>;
643 no-map;
644 };
645
646 reserved@9d400000 {
647 reg = <0x0 0x9d400000 0x0 0x1000000>;
648 no-map;
649 };
650
651 reserved@9e400000 {
652 reg = <0x0 0x9e400000 0x0 0x1400000>;
653 no-map;
654 };
655
656 reserved@9f800000 {
657 reg = <0x0 0x9f800000 0x0 0x800000>;
658 no-map;
659 };
660 };
661
662 smp2p-cdsp {
663 compatible = "qcom,smp2p";
664 qcom,smem = <94>, <432>;
665
666 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
667
668 mboxes = <&apss_shared 6>;
669
670 qcom,local-pid = <0>;
671 qcom,remote-pid = <5>;
672
673 cdsp_smp2p_out: master-kernel {
674 qcom,entry-name = "master-kernel";
675 #qcom,smem-state-cells = <1>;
676 };
677
678 cdsp_smp2p_in: slave-kernel {
679 qcom,entry-name = "slave-kernel";
680
681 interrupt-controller;
682 #interrupt-cells = <2>;
683 };
684 };
685
686 smp2p-lpass {
687 compatible = "qcom,smp2p";
688 qcom,smem = <443>, <429>;
689
690 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
691
692 mboxes = <&apss_shared 10>;
693
694 qcom,local-pid = <0>;
695 qcom,remote-pid = <2>;
696
697 adsp_smp2p_out: master-kernel {
698 qcom,entry-name = "master-kernel";
699 #qcom,smem-state-cells = <1>;
700 };
701
702 adsp_smp2p_in: slave-kernel {
703 qcom,entry-name = "slave-kernel";
704
705 interrupt-controller;
706 #interrupt-cells = <2>;
707 };
708 };
709
710 smp2p-mpss {
711 compatible = "qcom,smp2p";
712 qcom,smem = <435>, <428>;
713
714 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
715
716 mboxes = <&apss_shared 14>;
717
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <1>;
720
721 modem_smp2p_out: master-kernel {
722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells = <1>;
724 };
725
726 modem_smp2p_in: slave-kernel {
727 qcom,entry-name = "slave-kernel";
728
729 interrupt-controller;
730 #interrupt-cells = <2>;
731 };
732
733 modem_smp2p_ipa_out: ipa-ap-to-modem {
734 qcom,entry-name = "ipa";
735 #qcom,smem-state-cells = <1>;
736 };
737
738 modem_smp2p_ipa_in: ipa-modem-to-ap {
739 qcom,entry-name = "ipa";
740 interrupt-controller;
741 #interrupt-cells = <2>;
742 };
743
744 modem_smp2p_wlan_in: wlan-wpss-to-ap {
745 qcom,entry-name = "wlan";
746 interrupt-controller;
747 #interrupt-cells = <2>;
748 };
749 };
750
751 smp2p-slpi {
752 compatible = "qcom,smp2p";
753 qcom,smem = <481>, <430>;
754
755 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
756
757 mboxes = <&apss_shared 26>;
758
759 qcom,local-pid = <0>;
760 qcom,remote-pid = <3>;
761
762 slpi_smp2p_out: master-kernel {
763 qcom,entry-name = "master-kernel";
764 #qcom,smem-state-cells = <1>;
765 };
766
767 slpi_smp2p_in: slave-kernel {
768 qcom,entry-name = "slave-kernel";
769
770 interrupt-controller;
771 #interrupt-cells = <2>;
772 };
773 };
774
775 soc: soc@0 {
776 compatible = "simple-bus";
777 #address-cells = <2>;
778 #size-cells = <2>;
779 ranges = <0 0 0 0 0x10 0>;
780 dma-ranges = <0 0 0 0 0x10 0>;
781
782 gcc: clock-controller@100000 {
783 compatible = "qcom,gcc-sc8180x";
784 reg = <0x0 0x00100000 0x0 0x1f0000>;
785 #clock-cells = <1>;
786 #reset-cells = <1>;
787 #power-domain-cells = <1>;
788 clocks = <&rpmhcc RPMH_CXO_CLK>,
789 <&rpmhcc RPMH_CXO_CLK_A>,
790 <&sleep_clk>;
791 clock-names = "bi_tcxo",
792 "bi_tcxo_ao",
793 "sleep_clk";
794 power-domains = <&rpmhpd SC8180X_CX>;
795 };
796
797 qupv3_id_0: geniqup@8c0000 {
798 compatible = "qcom,geni-se-qup";
799 reg = <0 0x008c0000 0 0x6000>;
800 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
801 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
802 clock-names = "m-ahb", "s-ahb";
803 #address-cells = <2>;
804 #size-cells = <2>;
805 ranges;
806 iommus = <&apps_smmu 0x4c3 0>;
807 status = "disabled";
808
809 i2c0: i2c@880000 {
810 compatible = "qcom,geni-i2c";
811 reg = <0 0x00880000 0 0x4000>;
812 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
813 clock-names = "se";
814 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
815 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
816 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
817 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
818 interconnect-names = "qup-core", "qup-config", "qup-memory";
819 #address-cells = <1>;
820 #size-cells = <0>;
821 status = "disabled";
822 };
823
824 spi0: spi@880000 {
825 compatible = "qcom,geni-spi";
826 reg = <0 0x00880000 0 0x4000>;
827 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
828 clock-names = "se";
829 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
830 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
831 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
832 interconnect-names = "qup-core", "qup-config";
833 #address-cells = <1>;
834 #size-cells = <0>;
835 status = "disabled";
836 };
837
838 uart0: serial@880000 {
839 compatible = "qcom,geni-uart";
840 reg = <0 0x00880000 0 0x4000>;
841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
842 clock-names = "se";
843 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
844 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
845 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
846 interconnect-names = "qup-core", "qup-config";
847 status = "disabled";
848 };
849
850 i2c1: i2c@884000 {
851 compatible = "qcom,geni-i2c";
852 reg = <0 0x00884000 0 0x4000>;
853 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
854 clock-names = "se";
855 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
856 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
857 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
858 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
859 interconnect-names = "qup-core", "qup-config", "qup-memory";
860 #address-cells = <1>;
861 #size-cells = <0>;
862 status = "disabled";
863 };
864
865 spi1: spi@884000 {
866 compatible = "qcom,geni-spi";
867 reg = <0 0x00884000 0 0x4000>;
868 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
869 clock-names = "se";
870 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
871 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
872 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
873 interconnect-names = "qup-core", "qup-config";
874 #address-cells = <1>;
875 #size-cells = <0>;
876 status = "disabled";
877 };
878
879 uart1: serial@884000 {
880 compatible = "qcom,geni-uart";
881 reg = <0 0x00884000 0 0x4000>;
882 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
883 clock-names = "se";
884 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
885 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
886 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
887 interconnect-names = "qup-core", "qup-config";
888 status = "disabled";
889 };
890
891 i2c2: i2c@888000 {
892 compatible = "qcom,geni-i2c";
893 reg = <0 0x00888000 0 0x4000>;
894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
895 clock-names = "se";
896 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
898 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
899 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
900 interconnect-names = "qup-core", "qup-config", "qup-memory";
901 #address-cells = <1>;
902 #size-cells = <0>;
903 status = "disabled";
904 };
905
906 spi2: spi@888000 {
907 compatible = "qcom,geni-spi";
908 reg = <0 0x00888000 0 0x4000>;
909 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
910 clock-names = "se";
911 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
912 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
913 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
914 interconnect-names = "qup-core", "qup-config";
915 #address-cells = <1>;
916 #size-cells = <0>;
917 status = "disabled";
918 };
919
920 uart2: serial@888000 {
921 compatible = "qcom,geni-uart";
922 reg = <0 0x00888000 0 0x4000>;
923 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
924 clock-names = "se";
925 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
926 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
927 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
928 interconnect-names = "qup-core", "qup-config";
929 status = "disabled";
930 };
931
932 i2c3: i2c@88c000 {
933 compatible = "qcom,geni-i2c";
934 reg = <0 0x0088c000 0 0x4000>;
935 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
936 clock-names = "se";
937 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
938 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
939 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
940 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
941 interconnect-names = "qup-core", "qup-config", "qup-memory";
942 #address-cells = <1>;
943 #size-cells = <0>;
944 status = "disabled";
945 };
946
947 spi3: spi@88c000 {
948 compatible = "qcom,geni-spi";
949 reg = <0 0x0088c000 0 0x4000>;
950 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
951 clock-names = "se";
952 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
953 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
955 interconnect-names = "qup-core", "qup-config";
956 #address-cells = <1>;
957 #size-cells = <0>;
958 status = "disabled";
959 };
960
961 uart3: serial@88c000 {
962 compatible = "qcom,geni-uart";
963 reg = <0 0x0088c000 0 0x4000>;
964 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
965 clock-names = "se";
966 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
967 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
968 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
969 interconnect-names = "qup-core", "qup-config";
970 status = "disabled";
971 };
972
973 i2c4: i2c@890000 {
974 compatible = "qcom,geni-i2c";
975 reg = <0 0x00890000 0 0x4000>;
976 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
977 clock-names = "se";
978 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
979 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
980 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
981 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
982 interconnect-names = "qup-core", "qup-config", "qup-memory";
983 #address-cells = <1>;
984 #size-cells = <0>;
985 status = "disabled";
986 };
987
988 spi4: spi@890000 {
989 compatible = "qcom,geni-spi";
990 reg = <0 0x00890000 0 0x4000>;
991 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
992 clock-names = "se";
993 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
994 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
995 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
996 interconnect-names = "qup-core", "qup-config";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 status = "disabled";
1000 };
1001
1002 uart4: serial@890000 {
1003 compatible = "qcom,geni-uart";
1004 reg = <0 0x00890000 0 0x4000>;
1005 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1006 clock-names = "se";
1007 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1008 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1009 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1010 interconnect-names = "qup-core", "qup-config";
1011 status = "disabled";
1012 };
1013
1014 i2c5: i2c@894000 {
1015 compatible = "qcom,geni-i2c";
1016 reg = <0 0x00894000 0 0x4000>;
1017 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1018 clock-names = "se";
1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1020 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1021 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1022 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1023 interconnect-names = "qup-core", "qup-config", "qup-memory";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 status = "disabled";
1027 };
1028
1029 spi5: spi@894000 {
1030 compatible = "qcom,geni-spi";
1031 reg = <0 0x00894000 0 0x4000>;
1032 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1033 clock-names = "se";
1034 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1035 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1037 interconnect-names = "qup-core", "qup-config";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 status = "disabled";
1041 };
1042
1043 uart5: serial@894000 {
1044 compatible = "qcom,geni-uart";
1045 reg = <0 0x00894000 0 0x4000>;
1046 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1047 clock-names = "se";
1048 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1049 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1050 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1051 interconnect-names = "qup-core", "qup-config";
1052 status = "disabled";
1053 };
1054
1055 i2c6: i2c@898000 {
1056 compatible = "qcom,geni-i2c";
1057 reg = <0 0x00898000 0 0x4000>;
1058 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1059 clock-names = "se";
1060 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1062 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1063 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1067 status = "disabled";
1068 };
1069
1070 spi6: spi@898000 {
1071 compatible = "qcom,geni-spi";
1072 reg = <0 0x00898000 0 0x4000>;
1073 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1074 clock-names = "se";
1075 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1076 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1077 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1078 interconnect-names = "qup-core", "qup-config";
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081 status = "disabled";
1082 };
1083
1084 uart6: serial@898000 {
1085 compatible = "qcom,geni-uart";
1086 reg = <0 0x00898000 0 0x4000>;
1087 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1088 clock-names = "se";
1089 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1090 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1091 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1092 interconnect-names = "qup-core", "qup-config";
1093 status = "disabled";
1094 };
1095
1096 i2c7: i2c@89c000 {
1097 compatible = "qcom,geni-i2c";
1098 reg = <0 0x0089c000 0 0x4000>;
1099 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1100 clock-names = "se";
1101 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1102 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1104 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1105 interconnect-names = "qup-core", "qup-config", "qup-memory";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1108 status = "disabled";
1109 };
1110
1111 spi7: spi@89c000 {
1112 compatible = "qcom,geni-spi";
1113 reg = <0 0x0089c000 0 0x4000>;
1114 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1115 clock-names = "se";
1116 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1117 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect-names = "qup-core", "qup-config";
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1122 status = "disabled";
1123 };
1124
1125 uart7: serial@89c000 {
1126 compatible = "qcom,geni-uart";
1127 reg = <0 0x0089c000 0 0x4000>;
1128 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1129 clock-names = "se";
1130 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1132 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1133 interconnect-names = "qup-core", "qup-config";
1134 status = "disabled";
1135 };
1136 };
1137
1138 qupv3_id_1: geniqup@ac0000 {
1139 compatible = "qcom,geni-se-qup";
1140 reg = <0x0 0x00ac0000 0x0 0x6000>;
1141 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1142 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1143 clock-names = "m-ahb", "s-ahb";
1144 #address-cells = <2>;
1145 #size-cells = <2>;
1146 ranges;
1147 iommus = <&apps_smmu 0x603 0>;
1148 status = "disabled";
1149
1150 i2c8: i2c@a80000 {
1151 compatible = "qcom,geni-i2c";
1152 reg = <0 0x00a80000 0 0x4000>;
1153 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1154 clock-names = "se";
1155 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1156 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1157 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1158 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1159 interconnect-names = "qup-core", "qup-config", "qup-memory";
1160 #address-cells = <1>;
1161 #size-cells = <0>;
1162 status = "disabled";
1163 };
1164
1165 spi8: spi@a80000 {
1166 compatible = "qcom,geni-spi";
1167 reg = <0 0x00a80000 0 0x4000>;
1168 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1169 clock-names = "se";
1170 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1171 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1172 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1173 interconnect-names = "qup-core", "qup-config";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 status = "disabled";
1177 };
1178
1179 uart8: serial@a80000 {
1180 compatible = "qcom,geni-uart";
1181 reg = <0 0x00a80000 0 0x4000>;
1182 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1183 clock-names = "se";
1184 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1185 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1186 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1187 interconnect-names = "qup-core", "qup-config";
1188 status = "disabled";
1189 };
1190
1191 i2c9: i2c@a84000 {
1192 compatible = "qcom,geni-i2c";
1193 reg = <0 0x00a84000 0 0x4000>;
1194 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1195 clock-names = "se";
1196 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1198 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1200 interconnect-names = "qup-core", "qup-config", "qup-memory";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1203 status = "disabled";
1204 };
1205
1206 spi9: spi@a84000 {
1207 compatible = "qcom,geni-spi";
1208 reg = <0 0x00a84000 0 0x4000>;
1209 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1210 clock-names = "se";
1211 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1212 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1214 interconnect-names = "qup-core", "qup-config";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 status = "disabled";
1218 };
1219
1220 uart9: serial@a84000 {
1221 compatible = "qcom,geni-debug-uart";
1222 reg = <0 0x00a84000 0 0x4000>;
1223 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1224 clock-names = "se";
1225 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1226 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1227 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1228 interconnect-names = "qup-core", "qup-config";
1229 status = "disabled";
1230 };
1231
1232 i2c10: i2c@a88000 {
1233 compatible = "qcom,geni-i2c";
1234 reg = <0 0x00a88000 0 0x4000>;
1235 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1236 clock-names = "se";
1237 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1238 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1240 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1241 interconnect-names = "qup-core", "qup-config", "qup-memory";
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1244 status = "disabled";
1245 };
1246
1247 spi10: spi@a88000 {
1248 compatible = "qcom,geni-spi";
1249 reg = <0 0x00a88000 0 0x4000>;
1250 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1251 clock-names = "se";
1252 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1253 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1255 interconnect-names = "qup-core", "qup-config";
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1258 status = "disabled";
1259 };
1260
1261 uart10: serial@a88000 {
1262 compatible = "qcom,geni-uart";
1263 reg = <0 0x00a88000 0 0x4000>;
1264 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1265 clock-names = "se";
1266 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1267 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1268 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1269 interconnect-names = "qup-core", "qup-config";
1270 status = "disabled";
1271 };
1272
1273 i2c11: i2c@a8c000 {
1274 compatible = "qcom,geni-i2c";
1275 reg = <0 0x00a8c000 0 0x4000>;
1276 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1277 clock-names = "se";
1278 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1279 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1280 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1281 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1282 interconnect-names = "qup-core", "qup-config", "qup-memory";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285 status = "disabled";
1286 };
1287
1288 spi11: spi@a8c000 {
1289 compatible = "qcom,geni-spi";
1290 reg = <0 0x00a8c000 0 0x4000>;
1291 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1292 clock-names = "se";
1293 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1294 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1296 interconnect-names = "qup-core", "qup-config";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1299 status = "disabled";
1300 };
1301
1302 uart11: serial@a8c000 {
1303 compatible = "qcom,geni-uart";
1304 reg = <0 0x00a8c000 0 0x4000>;
1305 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1306 clock-names = "se";
1307 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1309 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1310 interconnect-names = "qup-core", "qup-config";
1311 status = "disabled";
1312 };
1313
1314 i2c12: i2c@a90000 {
1315 compatible = "qcom,geni-i2c";
1316 reg = <0 0x00a90000 0 0x4000>;
1317 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1318 clock-names = "se";
1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1320 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1321 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1322 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1323 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1326 status = "disabled";
1327 };
1328
1329 spi12: spi@a90000 {
1330 compatible = "qcom,geni-spi";
1331 reg = <0 0x00a90000 0 0x4000>;
1332 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1333 clock-names = "se";
1334 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1335 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1336 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1337 interconnect-names = "qup-core", "qup-config";
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340 status = "disabled";
1341 };
1342
1343 uart12: serial@a90000 {
1344 compatible = "qcom,geni-uart";
1345 reg = <0 0x00a90000 0 0x4000>;
1346 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1347 clock-names = "se";
1348 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1349 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1350 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1351 interconnect-names = "qup-core", "qup-config";
1352 status = "disabled";
1353 };
1354
1355 i2c16: i2c@a94000 {
1356 compatible = "qcom,geni-i2c";
1357 reg = <0 0x00a94000 0 0x4000>;
1358 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1359 clock-names = "se";
1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1362 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1363 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1364 interconnect-names = "qup-core", "qup-config", "qup-memory";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1367 status = "disabled";
1368 };
1369
1370 spi16: spi@a94000 {
1371 compatible = "qcom,geni-spi";
1372 reg = <0 0x00a94000 0 0x4000>;
1373 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1374 clock-names = "se";
1375 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1376 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1377 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1378 interconnect-names = "qup-core", "qup-config";
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1381 status = "disabled";
1382 };
1383
1384 uart16: serial@a94000 {
1385 compatible = "qcom,geni-uart";
1386 reg = <0 0x00a94000 0 0x4000>;
1387 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1388 clock-names = "se";
1389 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1390 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1391 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1392 interconnect-names = "qup-core", "qup-config";
1393 status = "disabled";
1394 };
1395 };
1396
1397 qupv3_id_2: geniqup@cc0000 {
1398 compatible = "qcom,geni-se-qup";
1399 reg = <0x0 0x00cc0000 0x0 0x6000>;
1400 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1401 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1402 clock-names = "m-ahb", "s-ahb";
1403 #address-cells = <2>;
1404 #size-cells = <2>;
1405 ranges;
1406 iommus = <&apps_smmu 0x7a3 0>;
1407 status = "disabled";
1408
1409 i2c17: i2c@c80000 {
1410 compatible = "qcom,geni-i2c";
1411 reg = <0 0x00c80000 0 0x4000>;
1412 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1413 clock-names = "se";
1414 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1415 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1416 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1417 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1419 #address-cells = <1>;
1420 #size-cells = <0>;
1421 status = "disabled";
1422 };
1423
1424 spi17: spi@c80000 {
1425 compatible = "qcom,geni-spi";
1426 reg = <0 0x00c80000 0 0x4000>;
1427 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1428 clock-names = "se";
1429 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1430 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1431 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1432 interconnect-names = "qup-core", "qup-config";
1433 #address-cells = <1>;
1434 #size-cells = <0>;
1435 status = "disabled";
1436 };
1437
1438 uart17: serial@c80000 {
1439 compatible = "qcom,geni-uart";
1440 reg = <0 0x00c80000 0 0x4000>;
1441 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1442 clock-names = "se";
1443 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1444 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1445 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1446 interconnect-names = "qup-core", "qup-config";
1447 status = "disabled";
1448 };
1449
1450 i2c18: i2c@c84000 {
1451 compatible = "qcom,geni-i2c";
1452 reg = <0 0x00c84000 0 0x4000>;
1453 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1454 clock-names = "se";
1455 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1456 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1457 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1458 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1459 interconnect-names = "qup-core", "qup-config", "qup-memory";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1462 status = "disabled";
1463 };
1464
1465 spi18: spi@c84000 {
1466 compatible = "qcom,geni-spi";
1467 reg = <0 0x00c84000 0 0x4000>;
1468 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1469 clock-names = "se";
1470 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1471 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1472 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1473 interconnect-names = "qup-core", "qup-config";
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1476 status = "disabled";
1477 };
1478
1479 uart18: serial@c84000 {
1480 compatible = "qcom,geni-uart";
1481 reg = <0 0x00c84000 0 0x4000>;
1482 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1483 clock-names = "se";
1484 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1485 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1486 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1487 interconnect-names = "qup-core", "qup-config";
1488 status = "disabled";
1489 };
1490
1491 i2c19: i2c@c88000 {
1492 compatible = "qcom,geni-i2c";
1493 reg = <0 0x00c88000 0 0x4000>;
1494 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1495 clock-names = "se";
1496 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1497 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1498 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1499 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1500 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1503 status = "disabled";
1504 };
1505
1506 spi19: spi@c88000 {
1507 compatible = "qcom,geni-spi";
1508 reg = <0 0x00c88000 0 0x4000>;
1509 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1510 clock-names = "se";
1511 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1512 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1513 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1514 interconnect-names = "qup-core", "qup-config";
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1517 status = "disabled";
1518 };
1519
1520 uart19: serial@c88000 {
1521 compatible = "qcom,geni-uart";
1522 reg = <0 0x00c88000 0 0x4000>;
1523 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1524 clock-names = "se";
1525 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1526 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1528 interconnect-names = "qup-core", "qup-config";
1529 status = "disabled";
1530 };
1531
1532 i2c13: i2c@c8c000 {
1533 compatible = "qcom,geni-i2c";
1534 reg = <0 0x00c8c000 0 0x4000>;
1535 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1536 clock-names = "se";
1537 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1538 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1539 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1540 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1541 interconnect-names = "qup-core", "qup-config", "qup-memory";
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544 status = "disabled";
1545 };
1546
1547 spi13: spi@c8c000 {
1548 compatible = "qcom,geni-spi";
1549 reg = <0 0x00c8c000 0 0x4000>;
1550 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1551 clock-names = "se";
1552 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1553 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1554 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1555 interconnect-names = "qup-core", "qup-config";
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1558 status = "disabled";
1559 };
1560
1561 uart13: serial@c8c000 {
1562 compatible = "qcom,geni-uart";
1563 reg = <0 0x00c8c000 0 0x4000>;
1564 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1565 clock-names = "se";
1566 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1567 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1568 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1569 interconnect-names = "qup-core", "qup-config";
1570 status = "disabled";
1571 };
1572
1573 i2c14: i2c@c90000 {
1574 compatible = "qcom,geni-i2c";
1575 reg = <0 0x00c90000 0 0x4000>;
1576 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1577 clock-names = "se";
1578 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1579 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1580 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1581 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1582 interconnect-names = "qup-core", "qup-config", "qup-memory";
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1585 status = "disabled";
1586 };
1587
1588 spi14: spi@c90000 {
1589 compatible = "qcom,geni-spi";
1590 reg = <0 0x00c90000 0 0x4000>;
1591 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1592 clock-names = "se";
1593 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1594 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1596 interconnect-names = "qup-core", "qup-config";
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1599 status = "disabled";
1600 };
1601
1602 uart14: serial@c90000 {
1603 compatible = "qcom,geni-uart";
1604 reg = <0 0x00c90000 0 0x4000>;
1605 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1606 clock-names = "se";
1607 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1608 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1609 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1610 interconnect-names = "qup-core", "qup-config";
1611 status = "disabled";
1612 };
1613
1614 i2c15: i2c@c94000 {
1615 compatible = "qcom,geni-i2c";
1616 reg = <0 0x00c94000 0 0x4000>;
1617 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1618 clock-names = "se";
1619 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1620 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1621 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1622 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626 status = "disabled";
1627 };
1628
1629 spi15: spi@c94000 {
1630 compatible = "qcom,geni-spi";
1631 reg = <0 0x00c94000 0 0x4000>;
1632 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1633 clock-names = "se";
1634 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1635 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1636 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1637 interconnect-names = "qup-core", "qup-config";
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1640 status = "disabled";
1641 };
1642
1643 uart15: serial@c94000 {
1644 compatible = "qcom,geni-uart";
1645 reg = <0 0x00c94000 0 0x4000>;
1646 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1647 clock-names = "se";
1648 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1649 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1650 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1651 interconnect-names = "qup-core", "qup-config";
1652 status = "disabled";
1653 };
1654 };
1655
1656 config_noc: interconnect@1500000 {
1657 compatible = "qcom,sc8180x-config-noc";
1658 reg = <0 0x01500000 0 0x7400>;
1659 #interconnect-cells = <2>;
1660 qcom,bcm-voters = <&apps_bcm_voter>;
1661 };
1662
1663 system_noc: interconnect@1620000 {
1664 compatible = "qcom,sc8180x-system-noc";
1665 reg = <0 0x01620000 0 0x19400>;
1666 #interconnect-cells = <2>;
1667 qcom,bcm-voters = <&apps_bcm_voter>;
1668 };
1669
1670 aggre1_noc: interconnect@16e0000 {
1671 compatible = "qcom,sc8180x-aggre1-noc";
1672 reg = <0 0x016e0000 0 0xd080>;
1673 #interconnect-cells = <2>;
1674 qcom,bcm-voters = <&apps_bcm_voter>;
1675 };
1676
1677 aggre2_noc: interconnect@1700000 {
1678 compatible = "qcom,sc8180x-aggre2-noc";
1679 reg = <0 0x01700000 0 0x20000>;
1680 #interconnect-cells = <2>;
1681 qcom,bcm-voters = <&apps_bcm_voter>;
1682 };
1683
1684 compute_noc: interconnect@1720000 {
1685 compatible = "qcom,sc8180x-compute-noc";
1686 reg = <0 0x01720000 0 0x7000>;
1687 #interconnect-cells = <2>;
1688 qcom,bcm-voters = <&apps_bcm_voter>;
1689 };
1690
1691 mmss_noc: interconnect@1740000 {
1692 compatible = "qcom,sc8180x-mmss-noc";
1693 reg = <0 0x01740000 0 0x1c100>;
1694 #interconnect-cells = <2>;
1695 qcom,bcm-voters = <&apps_bcm_voter>;
1696 };
1697
1698 pcie0: pcie@1c00000 {
1699 compatible = "qcom,pcie-sc8180x";
1700 reg = <0 0x01c00000 0 0x3000>,
1701 <0 0x60000000 0 0xf1d>,
1702 <0 0x60000f20 0 0xa8>,
1703 <0 0x60001000 0 0x1000>,
1704 <0 0x60100000 0 0x100000>;
1705 reg-names = "parf",
1706 "dbi",
1707 "elbi",
1708 "atu",
1709 "config";
1710 device_type = "pci";
1711 linux,pci-domain = <0>;
1712 bus-range = <0x00 0xff>;
1713 num-lanes = <2>;
1714
1715 #address-cells = <3>;
1716 #size-cells = <2>;
1717
1718 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1719 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1720
1721 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1722 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1723 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1724 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1725 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1726 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1728 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1729 interrupt-names = "msi0",
1730 "msi1",
1731 "msi2",
1732 "msi3",
1733 "msi4",
1734 "msi5",
1735 "msi6",
1736 "msi7";
1737 #interrupt-cells = <1>;
1738 interrupt-map-mask = <0 0 0 0x7>;
1739 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1740 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1741 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1742 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1743
1744 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1745 <&gcc GCC_PCIE_0_AUX_CLK>,
1746 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1747 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1748 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1749 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1750 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1751 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1752 clock-names = "pipe",
1753 "aux",
1754 "cfg",
1755 "bus_master",
1756 "bus_slave",
1757 "slave_q2a",
1758 "ref",
1759 "tbu";
1760
1761 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1762 assigned-clock-rates = <19200000>;
1763
1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1765 <0x100 &apps_smmu 0x1d81 0x1>;
1766
1767 resets = <&gcc GCC_PCIE_0_BCR>;
1768 reset-names = "pci";
1769
1770 power-domains = <&gcc PCIE_0_GDSC>;
1771
1772 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1773 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1774 interconnect-names = "pcie-mem", "cpu-pcie";
1775
1776 phys = <&pcie0_phy>;
1777 phy-names = "pciephy";
1778 dma-coherent;
1779
1780 status = "disabled";
1781
1782 pcie@0 {
1783 device_type = "pci";
1784 reg = <0x0 0x0 0x0 0x0 0x0>;
1785 bus-range = <0x01 0xff>;
1786
1787 #address-cells = <3>;
1788 #size-cells = <2>;
1789 ranges;
1790 };
1791 };
1792
1793 pcie0_phy: phy@1c06000 {
1794 compatible = "qcom,sc8180x-qmp-pcie-phy";
1795 reg = <0 0x01c06000 0 0x1000>;
1796 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1797 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1798 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1799 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1800 <&gcc GCC_PCIE_0_PIPE_CLK>;
1801 clock-names = "aux",
1802 "cfg_ahb",
1803 "ref",
1804 "refgen",
1805 "pipe";
1806 #clock-cells = <0>;
1807 clock-output-names = "pcie_0_pipe_clk";
1808 #phy-cells = <0>;
1809
1810 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1811 reset-names = "phy";
1812
1813 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1814 assigned-clock-rates = <100000000>;
1815
1816 status = "disabled";
1817 };
1818
1819 pcie3: pcie@1c08000 {
1820 compatible = "qcom,pcie-sc8180x";
1821 reg = <0 0x01c08000 0 0x3000>,
1822 <0 0x40000000 0 0xf1d>,
1823 <0 0x40000f20 0 0xa8>,
1824 <0 0x40001000 0 0x1000>,
1825 <0 0x40100000 0 0x100000>;
1826 reg-names = "parf",
1827 "dbi",
1828 "elbi",
1829 "atu",
1830 "config";
1831 device_type = "pci";
1832 linux,pci-domain = <3>;
1833 bus-range = <0x00 0xff>;
1834 num-lanes = <2>;
1835
1836 #address-cells = <3>;
1837 #size-cells = <2>;
1838
1839 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1840 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1841
1842 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1846 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1850 interrupt-names = "msi0",
1851 "msi1",
1852 "msi2",
1853 "msi3",
1854 "msi4",
1855 "msi5",
1856 "msi6",
1857 "msi7";
1858 #interrupt-cells = <1>;
1859 interrupt-map-mask = <0 0 0 0x7>;
1860 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1861 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1862 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1863 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1864
1865 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1866 <&gcc GCC_PCIE_3_AUX_CLK>,
1867 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1868 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1869 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1870 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
1871 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1872 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1873 clock-names = "pipe",
1874 "aux",
1875 "cfg",
1876 "bus_master",
1877 "bus_slave",
1878 "slave_q2a",
1879 "ref",
1880 "tbu";
1881
1882 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1883 assigned-clock-rates = <19200000>;
1884
1885 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1886 <0x100 &apps_smmu 0x1e01 0x1>;
1887
1888 resets = <&gcc GCC_PCIE_3_BCR>;
1889 reset-names = "pci";
1890
1891 power-domains = <&gcc PCIE_3_GDSC>;
1892
1893 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1894 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
1895 interconnect-names = "pcie-mem", "cpu-pcie";
1896
1897 phys = <&pcie3_phy>;
1898 phy-names = "pciephy";
1899 dma-coherent;
1900
1901 status = "disabled";
1902
1903 pcie@0 {
1904 device_type = "pci";
1905 reg = <0x0 0x0 0x0 0x0 0x0>;
1906 bus-range = <0x01 0xff>;
1907
1908 #address-cells = <3>;
1909 #size-cells = <2>;
1910 ranges;
1911 };
1912 };
1913
1914 pcie3_phy: phy@1c0c000 {
1915 compatible = "qcom,sc8180x-qmp-pcie-phy";
1916 reg = <0 0x01c0c000 0 0x1000>;
1917 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1918 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1919 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1920 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
1921 <&gcc GCC_PCIE_3_PIPE_CLK>;
1922 clock-names = "aux",
1923 "cfg_ahb",
1924 "ref",
1925 "refgen",
1926 "pipe";
1927 #clock-cells = <0>;
1928 clock-output-names = "pcie_3_pipe_clk";
1929
1930 #phy-cells = <0>;
1931
1932 resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1933 reset-names = "phy";
1934
1935 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1936 assigned-clock-rates = <100000000>;
1937
1938 status = "disabled";
1939 };
1940
1941 pcie1: pcie@1c10000 {
1942 compatible = "qcom,pcie-sc8180x";
1943 reg = <0 0x01c10000 0 0x3000>,
1944 <0 0x68000000 0 0xf1d>,
1945 <0 0x68000f20 0 0xa8>,
1946 <0 0x68001000 0 0x1000>,
1947 <0 0x68100000 0 0x100000>;
1948 reg-names = "parf",
1949 "dbi",
1950 "elbi",
1951 "atu",
1952 "config";
1953 device_type = "pci";
1954 linux,pci-domain = <1>;
1955 bus-range = <0x00 0xff>;
1956 num-lanes = <2>;
1957
1958 #address-cells = <3>;
1959 #size-cells = <2>;
1960
1961 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1962 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1963
1964 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-names = "msi0",
1973 "msi1",
1974 "msi2",
1975 "msi3",
1976 "msi4",
1977 "msi5",
1978 "msi6",
1979 "msi7";
1980 #interrupt-cells = <1>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1983 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1984 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1985 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1986
1987 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1988 <&gcc GCC_PCIE_1_AUX_CLK>,
1989 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1990 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1991 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1992 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1993 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1994 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1995 clock-names = "pipe",
1996 "aux",
1997 "cfg",
1998 "bus_master",
1999 "bus_slave",
2000 "slave_q2a",
2001 "ref",
2002 "tbu";
2003
2004 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2005 assigned-clock-rates = <19200000>;
2006
2007 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2008 <0x100 &apps_smmu 0x1c81 0x1>;
2009
2010 resets = <&gcc GCC_PCIE_1_BCR>;
2011 reset-names = "pci";
2012
2013 power-domains = <&gcc PCIE_1_GDSC>;
2014
2015 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2016 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
2017 interconnect-names = "pcie-mem", "cpu-pcie";
2018
2019 phys = <&pcie1_phy>;
2020 phy-names = "pciephy";
2021 dma-coherent;
2022
2023 status = "disabled";
2024
2025 pcie@0 {
2026 device_type = "pci";
2027 reg = <0x0 0x0 0x0 0x0 0x0>;
2028 bus-range = <0x01 0xff>;
2029
2030 #address-cells = <3>;
2031 #size-cells = <2>;
2032 ranges;
2033 };
2034 };
2035
2036 pcie1_phy: phy@1c16000 {
2037 compatible = "qcom,sc8180x-qmp-pcie-phy";
2038 reg = <0 0x01c16000 0 0x1000>;
2039 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2040 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2041 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2042 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2043 <&gcc GCC_PCIE_1_PIPE_CLK>;
2044 clock-names = "aux",
2045 "cfg_ahb",
2046 "ref",
2047 "refgen",
2048 "pipe";
2049 #clock-cells = <0>;
2050 clock-output-names = "pcie_1_pipe_clk";
2051
2052 #phy-cells = <0>;
2053
2054 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2055 reset-names = "phy";
2056
2057 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2058 assigned-clock-rates = <100000000>;
2059
2060 status = "disabled";
2061 };
2062
2063 pcie2: pcie@1c18000 {
2064 compatible = "qcom,pcie-sc8180x";
2065 reg = <0 0x01c18000 0 0x3000>,
2066 <0 0x70000000 0 0xf1d>,
2067 <0 0x70000f20 0 0xa8>,
2068 <0 0x70001000 0 0x1000>,
2069 <0 0x70100000 0 0x100000>;
2070 reg-names = "parf",
2071 "dbi",
2072 "elbi",
2073 "atu",
2074 "config";
2075 device_type = "pci";
2076 linux,pci-domain = <2>;
2077 bus-range = <0x00 0xff>;
2078 num-lanes = <4>;
2079
2080 #address-cells = <3>;
2081 #size-cells = <2>;
2082
2083 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2084 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2085
2086 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>;
2094 interrupt-names = "msi0",
2095 "msi1",
2096 "msi2",
2097 "msi3",
2098 "msi4",
2099 "msi5",
2100 "msi6",
2101 "msi7";
2102 #interrupt-cells = <1>;
2103 interrupt-map-mask = <0 0 0 0x7>;
2104 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2105 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2106 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2107 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2108
2109 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2110 <&gcc GCC_PCIE_2_AUX_CLK>,
2111 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2112 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2113 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2114 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2115 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2116 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2117 clock-names = "pipe",
2118 "aux",
2119 "cfg",
2120 "bus_master",
2121 "bus_slave",
2122 "slave_q2a",
2123 "ref",
2124 "tbu";
2125
2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2127 assigned-clock-rates = <19200000>;
2128
2129 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2130 <0x100 &apps_smmu 0x1d01 0x1>;
2131
2132 resets = <&gcc GCC_PCIE_2_BCR>;
2133 reset-names = "pci";
2134
2135 power-domains = <&gcc PCIE_2_GDSC>;
2136
2137 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2138 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
2139 interconnect-names = "pcie-mem", "cpu-pcie";
2140
2141 phys = <&pcie2_phy>;
2142 phy-names = "pciephy";
2143 dma-coherent;
2144
2145 status = "disabled";
2146
2147 pcie@0 {
2148 device_type = "pci";
2149 reg = <0x0 0x0 0x0 0x0 0x0>;
2150 bus-range = <0x01 0xff>;
2151
2152 #address-cells = <3>;
2153 #size-cells = <2>;
2154 ranges;
2155 };
2156 };
2157
2158 pcie2_phy: phy@1c1c000 {
2159 compatible = "qcom,sc8180x-qmp-pcie-phy";
2160 reg = <0 0x01c1c000 0 0x1000>;
2161 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2162 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2163 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2164 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2165 <&gcc GCC_PCIE_2_PIPE_CLK>;
2166 clock-names = "aux",
2167 "cfg_ahb",
2168 "ref",
2169 "refgen",
2170 "pipe";
2171 #clock-cells = <0>;
2172 clock-output-names = "pcie_2_pipe_clk";
2173
2174 #phy-cells = <0>;
2175
2176 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2177 reset-names = "phy";
2178
2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2180 assigned-clock-rates = <100000000>;
2181
2182 status = "disabled";
2183 };
2184
2185 ufs_mem_hc: ufshc@1d84000 {
2186 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2187 "jedec,ufs-2.0";
2188 reg = <0 0x01d84000 0 0x2500>;
2189 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2190 phys = <&ufs_mem_phy>;
2191 phy-names = "ufsphy";
2192 lanes-per-direction = <2>;
2193 #reset-cells = <1>;
2194 resets = <&gcc GCC_UFS_PHY_BCR>;
2195 reset-names = "rst";
2196
2197 iommus = <&apps_smmu 0x300 0>;
2198
2199 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2200 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2201 <&gcc GCC_UFS_PHY_AHB_CLK>,
2202 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2203 <&rpmhcc RPMH_CXO_CLK>,
2204 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2205 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2206 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2207 clock-names = "core_clk",
2208 "bus_aggr_clk",
2209 "iface_clk",
2210 "core_clk_unipro",
2211 "ref_clk",
2212 "tx_lane0_sync_clk",
2213 "rx_lane0_sync_clk",
2214 "rx_lane1_sync_clk";
2215 freq-table-hz = <37500000 300000000>,
2216 <0 0>,
2217 <0 0>,
2218 <37500000 300000000>,
2219 <0 0>,
2220 <0 0>,
2221 <0 0>,
2222 <0 0>;
2223
2224 power-domains = <&gcc UFS_PHY_GDSC>;
2225
2226 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
2227 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2228 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
2229 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>;
2230 interconnect-names = "ufs-ddr", "cpu-ufs";
2231
2232 status = "disabled";
2233 };
2234
2235 ufs_mem_phy: phy-wrapper@1d87000 {
2236 compatible = "qcom,sc8180x-qmp-ufs-phy";
2237 reg = <0 0x01d87000 0 0x1000>;
2238
2239 clocks = <&rpmhcc RPMH_CXO_CLK>,
2240 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2241 <&gcc GCC_UFS_MEM_CLKREF_EN>;
2242 clock-names = "ref",
2243 "ref_aux",
2244 "qref";
2245
2246 resets = <&ufs_mem_hc 0>;
2247 reset-names = "ufsphy";
2248
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2250
2251 #phy-cells = <0>;
2252
2253 status = "disabled";
2254 };
2255
2256 tcsr_mutex: hwlock@1f40000 {
2257 compatible = "qcom,tcsr-mutex";
2258 reg = <0x0 0x01f40000 0x0 0x40000>;
2259 #hwlock-cells = <1>;
2260 };
2261
2262 gpu: gpu@2c00000 {
2263 compatible = "qcom,adreno-680.1", "qcom,adreno";
2264
2265 reg = <0 0x02c00000 0 0x40000>;
2266 reg-names = "kgsl_3d0_reg_memory";
2267
2268 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2269
2270 iommus = <&adreno_smmu 0 0xc01>;
2271
2272 operating-points-v2 = <&gpu_opp_table>;
2273
2274 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2275 interconnect-names = "gfx-mem";
2276
2277 qcom,gmu = <&gmu>;
2278 #cooling-cells = <2>;
2279
2280 status = "disabled";
2281
2282 gpu_opp_table: opp-table {
2283 compatible = "operating-points-v2";
2284
2285 opp-514000000 {
2286 opp-hz = /bits/ 64 <514000000>;
2287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2288 };
2289
2290 opp-500000000 {
2291 opp-hz = /bits/ 64 <500000000>;
2292 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2293 };
2294
2295 opp-461000000 {
2296 opp-hz = /bits/ 64 <461000000>;
2297 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2298 };
2299
2300 opp-405000000 {
2301 opp-hz = /bits/ 64 <405000000>;
2302 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2303 };
2304
2305 opp-315000000 {
2306 opp-hz = /bits/ 64 <315000000>;
2307 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2308 };
2309
2310 opp-256000000 {
2311 opp-hz = /bits/ 64 <256000000>;
2312 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2313 };
2314
2315 opp-177000000 {
2316 opp-hz = /bits/ 64 <177000000>;
2317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2318 };
2319 };
2320 };
2321
2322 gmu: gmu@2c6a000 {
2323 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2324
2325 reg = <0 0x02c6a000 0 0x30000>,
2326 <0 0x0b290000 0 0x10000>,
2327 <0 0x0b490000 0 0x10000>;
2328 reg-names = "gmu",
2329 "gmu_pdc",
2330 "gmu_pdc_seq";
2331
2332 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2334 interrupt-names = "hfi", "gmu";
2335
2336 clocks = <&gpucc GPU_CC_AHB_CLK>,
2337 <&gpucc GPU_CC_CX_GMU_CLK>,
2338 <&gpucc GPU_CC_CXO_CLK>,
2339 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2340 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2341 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2342
2343 power-domains = <&gpucc GPU_CX_GDSC>,
2344 <&gpucc GPU_GX_GDSC>;
2345 power-domain-names = "cx", "gx";
2346
2347 iommus = <&adreno_smmu 5 0xc00>;
2348
2349 operating-points-v2 = <&gmu_opp_table>;
2350
2351 gmu_opp_table: opp-table {
2352 compatible = "operating-points-v2";
2353
2354 opp-200000000 {
2355 opp-hz = /bits/ 64 <200000000>;
2356 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2357 };
2358
2359 opp-500000000 {
2360 opp-hz = /bits/ 64 <500000000>;
2361 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2362 };
2363 };
2364 };
2365
2366 gpucc: clock-controller@2c90000 {
2367 compatible = "qcom,sc8180x-gpucc";
2368 reg = <0 0x02c90000 0 0x9000>;
2369 clocks = <&rpmhcc RPMH_CXO_CLK>,
2370 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2371 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2372 clock-names = "bi_tcxo",
2373 "gcc_gpu_gpll0_clk_src",
2374 "gcc_gpu_gpll0_div_clk_src";
2375 #clock-cells = <1>;
2376 #reset-cells = <1>;
2377 #power-domain-cells = <1>;
2378 };
2379
2380 adreno_smmu: iommu@2ca0000 {
2381 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2382 "qcom,smmu-500", "arm,mmu-500";
2383 reg = <0 0x02ca0000 0 0x10000>;
2384 #iommu-cells = <2>;
2385 #global-interrupts = <1>;
2386 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2387 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2388 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2389 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2390 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2391 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2392 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2395 clocks = <&gpucc GPU_CC_AHB_CLK>,
2396 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2397 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2398 clock-names = "ahb", "bus", "iface";
2399
2400 power-domains = <&gpucc GPU_CX_GDSC>;
2401 };
2402
2403 tlmm: pinctrl@3100000 {
2404 compatible = "qcom,sc8180x-tlmm";
2405 reg = <0 0x03100000 0 0x300000>,
2406 <0 0x03500000 0 0x700000>,
2407 <0 0x03d00000 0 0x300000>;
2408 reg-names = "west", "east", "south";
2409 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2410 gpio-controller;
2411 #gpio-cells = <2>;
2412 interrupt-controller;
2413 #interrupt-cells = <2>;
2414 gpio-ranges = <&tlmm 0 0 191>;
2415 wakeup-parent = <&pdc>;
2416 };
2417
2418 remoteproc_mpss: remoteproc@4080000 {
2419 compatible = "qcom,sc8180x-mpss-pas";
2420 reg = <0x0 0x04080000 0x0 0x4040>;
2421
2422 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2423 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2424 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2425 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2426 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2427 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2428 interrupt-names = "wdog", "fatal", "ready", "handover",
2429 "stop-ack", "shutdown-ack";
2430
2431 clocks = <&rpmhcc RPMH_CXO_CLK>;
2432 clock-names = "xo";
2433
2434 power-domains = <&rpmhpd SC8180X_CX>,
2435 <&rpmhpd SC8180X_MSS>;
2436 power-domain-names = "cx", "mss";
2437
2438 qcom,qmp = <&aoss_qmp>;
2439
2440 qcom,smem-states = <&modem_smp2p_out 0>;
2441 qcom,smem-state-names = "stop";
2442
2443 glink-edge {
2444 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2445 label = "modem";
2446 qcom,remote-pid = <1>;
2447 mboxes = <&apss_shared 12>;
2448 };
2449 };
2450
2451 remoteproc_cdsp: remoteproc@8300000 {
2452 compatible = "qcom,sc8180x-cdsp-pas";
2453 reg = <0x0 0x08300000 0x0 0x4040>;
2454
2455 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2456 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2457 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2458 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2459 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2460 interrupt-names = "wdog", "fatal", "ready",
2461 "handover", "stop-ack";
2462
2463 clocks = <&rpmhcc RPMH_CXO_CLK>;
2464 clock-names = "xo";
2465
2466 power-domains = <&rpmhpd SC8180X_CX>;
2467 power-domain-names = "cx";
2468
2469 qcom,qmp = <&aoss_qmp>;
2470
2471 qcom,smem-states = <&cdsp_smp2p_out 0>;
2472 qcom,smem-state-names = "stop";
2473
2474 status = "disabled";
2475
2476 glink-edge {
2477 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
2478 label = "cdsp";
2479 qcom,remote-pid = <5>;
2480 mboxes = <&apss_shared 4>;
2481 };
2482 };
2483
2484 usb_prim_hsphy: phy@88e2000 {
2485 compatible = "qcom,sc8180x-usb-hs-phy",
2486 "qcom,usb-snps-hs-7nm-phy";
2487 reg = <0 0x088e2000 0 0x400>;
2488 clocks = <&rpmhcc RPMH_CXO_CLK>;
2489 clock-names = "ref";
2490 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2491
2492 #phy-cells = <0>;
2493
2494 status = "disabled";
2495 };
2496
2497 usb_sec_hsphy: phy@88e3000 {
2498 compatible = "qcom,sc8180x-usb-hs-phy",
2499 "qcom,usb-snps-hs-7nm-phy";
2500 reg = <0 0x088e3000 0 0x400>;
2501 clocks = <&rpmhcc RPMH_CXO_CLK>;
2502 clock-names = "ref";
2503 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2504
2505 #phy-cells = <0>;
2506
2507 status = "disabled";
2508 };
2509
2510 usb_mp_hsphy0: phy@88e4000 {
2511 compatible = "qcom,sc8180x-usb-hs-phy",
2512 "qcom,usb-snps-hs-7nm-phy";
2513 reg = <0 0x088e4000 0 0x400>;
2514 #phy-cells = <0>;
2515
2516 clocks = <&rpmhcc RPMH_CXO_CLK>;
2517 clock-names = "ref";
2518
2519 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;
2520
2521 status = "disabled";
2522 };
2523
2524 usb_mp_hsphy1: phy@88e5000 {
2525 compatible = "qcom,sc8180x-usb-hs-phy",
2526 "qcom,usb-snps-hs-7nm-phy";
2527 reg = <0 0x088e5000 0 0x400>;
2528 #phy-cells = <0>;
2529
2530 clocks = <&rpmhcc RPMH_CXO_CLK>;
2531 clock-names = "ref";
2532
2533 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;
2534
2535 status = "disabled";
2536 };
2537
2538 usb_prim_qmpphy: phy@88e8000 {
2539 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2540 reg = <0 0x088e8000 0 0x3000>;
2541
2542 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2543 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2544 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2545 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2546 clock-names = "aux",
2547 "ref",
2548 "com_aux",
2549 "usb3_pipe";
2550
2551 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
2552 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
2553 reset-names = "phy", "common";
2554
2555 #clock-cells = <1>;
2556 #phy-cells = <1>;
2557
2558 status = "disabled";
2559
2560 ports {
2561 #address-cells = <1>;
2562 #size-cells = <0>;
2563
2564 port@0 {
2565 reg = <0>;
2566
2567 usb_prim_qmpphy_out: endpoint {};
2568 };
2569
2570 port@1 {
2571 reg = <1>;
2572
2573 usb_prim_qmpphy_usb_ss_in: endpoint {
2574 remote-endpoint = <&usb_prim_dwc3_ss>;
2575 };
2576 };
2577
2578 port@2 {
2579 reg = <2>;
2580
2581 usb_prim_qmpphy_dp_in: endpoint {};
2582 };
2583 };
2584 };
2585
2586 usb_mp_qmpphy0: phy@88eb000 {
2587 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2588 reg = <0 0x088eb000 0 0x1000>;
2589
2590 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2591 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2592 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2593 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2594 clock-names = "aux",
2595 "ref",
2596 "com_aux",
2597 "pipe";
2598
2599 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2600 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2601 reset-names = "phy", "phy_phy";
2602
2603 power-domains = <&gcc USB30_MP_GDSC>;
2604
2605 #clock-cells = <0>;
2606 clock-output-names = "usb2_phy0_pipe_clk";
2607
2608 #phy-cells = <0>;
2609
2610 status = "disabled";
2611 };
2612
2613 usb_mp_qmpphy1: phy@88ec000 {
2614 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2615 reg = <0 0x088ec000 0 0x1000>;
2616
2617 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2618 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2619 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2620 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2621 clock-names = "aux",
2622 "ref",
2623 "com_aux",
2624 "pipe";
2625
2626 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2627 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2628 reset-names = "phy", "phy_phy";
2629
2630 power-domains = <&gcc USB30_MP_GDSC>;
2631
2632 #clock-cells = <0>;
2633 clock-output-names = "usb2_phy1_pipe_clk";
2634
2635 #phy-cells = <0>;
2636
2637 status = "disabled";
2638 };
2639
2640 usb_sec_qmpphy: phy@88ee000 {
2641 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2642 reg = <0 0x088ed000 0 0x3000>;
2643
2644 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2645 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2646 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2647 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2648 clock-names = "aux",
2649 "ref",
2650 "com_aux",
2651 "usb3_pipe";
2652 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
2653 <&gcc GCC_USB3_PHY_SEC_BCR>;
2654 reset-names = "phy", "common";
2655
2656 #clock-cells = <1>;
2657 #phy-cells = <1>;
2658
2659 status = "disabled";
2660
2661 ports {
2662 #address-cells = <1>;
2663 #size-cells = <0>;
2664
2665 port@0 {
2666 reg = <0>;
2667
2668 usb_sec_qmpphy_out: endpoint {};
2669 };
2670
2671 port@1 {
2672 reg = <1>;
2673
2674 usb_sec_qmpphy_usb_ss_in: endpoint {
2675 remote-endpoint = <&usb_sec_dwc3_ss>;
2676 };
2677 };
2678
2679 port@2 {
2680 reg = <2>;
2681
2682 usb_sec_qmpphy_dp_in: endpoint {};
2683 };
2684 };
2685 };
2686
2687 system-cache-controller@9200000 {
2688 compatible = "qcom,sc8180x-llcc";
2689 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2690 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2691 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
2692 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
2693 <0 0x09600000 0 0x58000>;
2694 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2695 "llcc3_base", "llcc4_base", "llcc5_base",
2696 "llcc6_base", "llcc7_base", "llcc_broadcast_base";
2697 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2698 };
2699
2700 gem_noc: interconnect@9680000 {
2701 compatible = "qcom,sc8180x-gem-noc";
2702 reg = <0 0x09680000 0 0x58200>;
2703 #interconnect-cells = <2>;
2704 qcom,bcm-voters = <&apps_bcm_voter>;
2705 };
2706
2707 usb_mp: usb@a4f8800 {
2708 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
2709 reg = <0 0x0a4f8800 0 0x400>;
2710 #address-cells = <2>;
2711 #size-cells = <2>;
2712 ranges;
2713 dma-ranges;
2714
2715 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
2716 <&gcc GCC_USB30_MP_MASTER_CLK>,
2717 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
2718 <&gcc GCC_USB30_MP_SLEEP_CLK>,
2719 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2720 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2721 clock-names = "cfg_noc",
2722 "core",
2723 "iface",
2724 "sleep",
2725 "mock_utmi",
2726 "xo";
2727
2728 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2729 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
2730 interconnect-names = "usb-ddr", "apps-usb";
2731
2732 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2733 <&gcc GCC_USB30_MP_MASTER_CLK>;
2734 assigned-clock-rates = <19200000>, <200000000>;
2735
2736 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
2737 <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
2738 <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
2739 <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
2740 <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
2741 <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
2742 <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
2743 <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
2744 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
2745 <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
2746 interrupt-names = "pwr_event_1", "pwr_event_2",
2747 "hs_phy_1", "hs_phy_2",
2748 "dp_hs_phy_1", "dm_hs_phy_1",
2749 "dp_hs_phy_2", "dm_hs_phy_2",
2750 "ss_phy_1", "ss_phy_2";
2751
2752 power-domains = <&gcc USB30_MP_GDSC>;
2753
2754 resets = <&gcc GCC_USB30_MP_BCR>;
2755
2756 status = "disabled";
2757
2758 usb_mp_dwc3: usb@a400000 {
2759 compatible = "snps,dwc3";
2760 reg = <0 0x0a400000 0 0xcd00>;
2761 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
2762 iommus = <&apps_smmu 0x60 0>;
2763 snps,dis_u2_susphy_quirk;
2764 snps,dis_enblslpm_quirk;
2765 phys = <&usb_mp_hsphy0>,
2766 <&usb_mp_qmpphy0>,
2767 <&usb_mp_hsphy1>,
2768 <&usb_mp_qmpphy1>;
2769 phy-names = "usb2-0",
2770 "usb3-0",
2771 "usb2-1",
2772 "usb3-1";
2773 dr_mode = "host";
2774 };
2775 };
2776
2777 usb_prim: usb@a6f8800 {
2778 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2779 reg = <0 0x0a6f8800 0 0x400>;
2780 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2781 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2782 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
2783 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2784 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
2785 interrupt-names = "pwr_event",
2786 "hs_phy_irq",
2787 "dp_hs_phy_irq",
2788 "dm_hs_phy_irq",
2789 "ss_phy_irq";
2790
2791 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2792 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2793 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2794 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2795 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2796 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2797 clock-names = "cfg_noc",
2798 "core",
2799 "iface",
2800 "sleep",
2801 "mock_utmi",
2802 "xo";
2803 resets = <&gcc GCC_USB30_PRIM_BCR>;
2804 power-domains = <&gcc USB30_PRIM_GDSC>;
2805
2806 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2807 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2808 interconnect-names = "usb-ddr", "apps-usb";
2809
2810 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2811 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2812 assigned-clock-rates = <19200000>, <200000000>;
2813
2814 #address-cells = <2>;
2815 #size-cells = <2>;
2816 ranges;
2817 dma-ranges;
2818
2819 status = "disabled";
2820
2821 usb_prim_dwc3: usb@a600000 {
2822 compatible = "snps,dwc3";
2823 reg = <0 0x0a600000 0 0xcd00>;
2824 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2825 iommus = <&apps_smmu 0x140 0>;
2826 snps,dis_u2_susphy_quirk;
2827 snps,dis_enblslpm_quirk;
2828 phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
2829 phy-names = "usb2-phy", "usb3-phy";
2830
2831 ports {
2832 #address-cells = <1>;
2833 #size-cells = <0>;
2834
2835 port@0 {
2836 reg = <0>;
2837
2838 usb_prim_dwc3_hs: endpoint {
2839 };
2840 };
2841
2842 port@1 {
2843 reg = <1>;
2844
2845 usb_prim_dwc3_ss: endpoint {
2846 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
2847 };
2848 };
2849 };
2850 };
2851 };
2852
2853 usb_sec: usb@a8f8800 {
2854 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2855 reg = <0 0x0a8f8800 0 0x400>;
2856
2857 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2858 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2859 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2860 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2861 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2862 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2863 clock-names = "cfg_noc",
2864 "core",
2865 "iface",
2866 "sleep",
2867 "mock_utmi",
2868 "xo";
2869 resets = <&gcc GCC_USB30_SEC_BCR>;
2870 power-domains = <&gcc USB30_SEC_GDSC>;
2871
2872 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2873 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2874 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
2875 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
2876 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
2877 interrupt-names = "pwr_event",
2878 "hs_phy_irq",
2879 "dp_hs_phy_irq",
2880 "dm_hs_phy_irq",
2881 "ss_phy_irq";
2882
2883 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2884 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2885 assigned-clock-rates = <19200000>, <200000000>;
2886
2887 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2888 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2889 interconnect-names = "usb-ddr", "apps-usb";
2890
2891 #address-cells = <2>;
2892 #size-cells = <2>;
2893 ranges;
2894 dma-ranges;
2895
2896 status = "disabled";
2897
2898 usb_sec_dwc3: usb@a800000 {
2899 compatible = "snps,dwc3";
2900 reg = <0 0x0a800000 0 0xcd00>;
2901 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2902 iommus = <&apps_smmu 0x160 0>;
2903 snps,dis_u2_susphy_quirk;
2904 snps,dis_enblslpm_quirk;
2905 phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
2906 phy-names = "usb2-phy", "usb3-phy";
2907
2908 ports {
2909 #address-cells = <1>;
2910 #size-cells = <0>;
2911
2912 port@0 {
2913 reg = <0>;
2914
2915 usb_sec_dwc3_hs: endpoint {
2916 };
2917 };
2918
2919 port@1 {
2920 reg = <1>;
2921
2922 usb_sec_dwc3_ss: endpoint {
2923 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
2924 };
2925 };
2926 };
2927 };
2928 };
2929
2930 mdss: mdss@ae00000 {
2931 compatible = "qcom,sc8180x-mdss";
2932 reg = <0 0x0ae00000 0 0x1000>;
2933 reg-names = "mdss";
2934
2935 power-domains = <&dispcc MDSS_GDSC>;
2936
2937 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2938 <&gcc GCC_DISP_HF_AXI_CLK>,
2939 <&gcc GCC_DISP_SF_AXI_CLK>,
2940 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2941 clock-names = "iface",
2942 "bus",
2943 "nrt_bus",
2944 "core";
2945
2946 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2947
2948 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2949 interrupt-controller;
2950 #interrupt-cells = <1>;
2951
2952 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
2953 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2954 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
2955 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2956 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
2957 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
2958 interconnect-names = "mdp0-mem",
2959 "mdp1-mem",
2960 "cpu-cfg";
2961
2962 iommus = <&apps_smmu 0x800 0x420>;
2963
2964 #address-cells = <2>;
2965 #size-cells = <2>;
2966 ranges;
2967
2968 status = "disabled";
2969
2970 mdss_mdp: mdp@ae01000 {
2971 compatible = "qcom,sc8180x-dpu";
2972 reg = <0 0x0ae01000 0 0x8f000>,
2973 <0 0x0aeb0000 0 0x2008>;
2974 reg-names = "mdp", "vbif";
2975
2976 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2977 <&gcc GCC_DISP_HF_AXI_CLK>,
2978 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2979 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2980 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2981 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
2982 clock-names = "iface",
2983 "bus",
2984 "core",
2985 "vsync",
2986 "rot",
2987 "lut";
2988
2989 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2990 assigned-clock-rates = <19200000>;
2991
2992 operating-points-v2 = <&mdp_opp_table>;
2993 power-domains = <&rpmhpd SC8180X_MMCX>;
2994
2995 interrupt-parent = <&mdss>;
2996 interrupts = <0>;
2997
2998 ports {
2999 #address-cells = <1>;
3000 #size-cells = <0>;
3001
3002 port@0 {
3003 reg = <0>;
3004 dpu_intf0_out: endpoint {
3005 remote-endpoint = <&dp0_in>;
3006 };
3007 };
3008
3009 port@1 {
3010 reg = <1>;
3011 dpu_intf1_out: endpoint {
3012 remote-endpoint = <&mdss_dsi0_in>;
3013 };
3014 };
3015
3016 port@2 {
3017 reg = <2>;
3018 dpu_intf2_out: endpoint {
3019 remote-endpoint = <&mdss_dsi1_in>;
3020 };
3021 };
3022
3023 port@4 {
3024 reg = <4>;
3025 dpu_intf4_out: endpoint {
3026 remote-endpoint = <&dp1_in>;
3027 };
3028 };
3029
3030 port@5 {
3031 reg = <5>;
3032 dpu_intf5_out: endpoint {
3033 remote-endpoint = <&edp_in>;
3034 };
3035 };
3036 };
3037
3038 mdp_opp_table: opp-table {
3039 compatible = "operating-points-v2";
3040
3041 opp-200000000 {
3042 opp-hz = /bits/ 64 <200000000>;
3043 required-opps = <&rpmhpd_opp_low_svs>;
3044 };
3045
3046 opp-300000000 {
3047 opp-hz = /bits/ 64 <300000000>;
3048 required-opps = <&rpmhpd_opp_svs>;
3049 };
3050
3051 opp-345000000 {
3052 opp-hz = /bits/ 64 <345000000>;
3053 required-opps = <&rpmhpd_opp_svs_l1>;
3054 };
3055
3056 opp-460000000 {
3057 opp-hz = /bits/ 64 <460000000>;
3058 required-opps = <&rpmhpd_opp_nom>;
3059 };
3060 };
3061 };
3062
3063 mdss_dsi0: dsi@ae94000 {
3064 compatible = "qcom,mdss-dsi-ctrl";
3065 reg = <0 0x0ae94000 0 0x400>;
3066 reg-names = "dsi_ctrl";
3067
3068 interrupt-parent = <&mdss>;
3069 interrupts = <4>;
3070
3071 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3072 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3073 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3074 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3075 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3076 <&gcc GCC_DISP_HF_AXI_CLK>;
3077 clock-names = "byte",
3078 "byte_intf",
3079 "pixel",
3080 "core",
3081 "iface",
3082 "bus";
3083
3084 operating-points-v2 = <&dsi_opp_table>;
3085 power-domains = <&rpmhpd SC8180X_MMCX>;
3086
3087 phys = <&mdss_dsi0_phy>;
3088 phy-names = "dsi";
3089
3090 status = "disabled";
3091
3092 ports {
3093 #address-cells = <1>;
3094 #size-cells = <0>;
3095
3096 port@0 {
3097 reg = <0>;
3098 mdss_dsi0_in: endpoint {
3099 remote-endpoint = <&dpu_intf1_out>;
3100 };
3101 };
3102
3103 port@1 {
3104 reg = <1>;
3105 mdss_dsi0_out: endpoint {
3106 };
3107 };
3108 };
3109
3110 dsi_opp_table: opp-table {
3111 compatible = "operating-points-v2";
3112
3113 opp-187500000 {
3114 opp-hz = /bits/ 64 <187500000>;
3115 required-opps = <&rpmhpd_opp_low_svs>;
3116 };
3117
3118 opp-300000000 {
3119 opp-hz = /bits/ 64 <300000000>;
3120 required-opps = <&rpmhpd_opp_svs>;
3121 };
3122
3123 opp-358000000 {
3124 opp-hz = /bits/ 64 <358000000>;
3125 required-opps = <&rpmhpd_opp_svs_l1>;
3126 };
3127 };
3128 };
3129
3130 mdss_dsi0_phy: dsi-phy@ae94400 {
3131 compatible = "qcom,dsi-phy-7nm";
3132 reg = <0 0x0ae94400 0 0x200>,
3133 <0 0x0ae94600 0 0x280>,
3134 <0 0x0ae94900 0 0x260>;
3135 reg-names = "dsi_phy",
3136 "dsi_phy_lane",
3137 "dsi_pll";
3138
3139 #clock-cells = <1>;
3140 #phy-cells = <0>;
3141
3142 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3143 <&rpmhcc RPMH_CXO_CLK>;
3144 clock-names = "iface", "ref";
3145
3146 status = "disabled";
3147 };
3148
3149 mdss_dsi1: dsi@ae96000 {
3150 compatible = "qcom,mdss-dsi-ctrl";
3151 reg = <0 0x0ae96000 0 0x400>;
3152 reg-names = "dsi_ctrl";
3153
3154 interrupt-parent = <&mdss>;
3155 interrupts = <5>;
3156
3157 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3158 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3159 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3160 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3161 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3162 <&gcc GCC_DISP_HF_AXI_CLK>;
3163 clock-names = "byte",
3164 "byte_intf",
3165 "pixel",
3166 "core",
3167 "iface",
3168 "bus";
3169
3170 operating-points-v2 = <&dsi_opp_table>;
3171 power-domains = <&rpmhpd SC8180X_MMCX>;
3172
3173 phys = <&mdss_dsi1_phy>;
3174 phy-names = "dsi";
3175
3176 status = "disabled";
3177
3178 ports {
3179 #address-cells = <1>;
3180 #size-cells = <0>;
3181
3182 port@0 {
3183 reg = <0>;
3184 mdss_dsi1_in: endpoint {
3185 remote-endpoint = <&dpu_intf2_out>;
3186 };
3187 };
3188
3189 port@1 {
3190 reg = <1>;
3191 mdss_dsi1_out: endpoint {
3192 };
3193 };
3194 };
3195 };
3196
3197 mdss_dsi1_phy: dsi-phy@ae96400 {
3198 compatible = "qcom,dsi-phy-7nm";
3199 reg = <0 0x0ae96400 0 0x200>,
3200 <0 0x0ae96600 0 0x280>,
3201 <0 0x0ae96900 0 0x260>;
3202 reg-names = "dsi_phy",
3203 "dsi_phy_lane",
3204 "dsi_pll";
3205
3206 #clock-cells = <1>;
3207 #phy-cells = <0>;
3208
3209 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3210 <&rpmhcc RPMH_CXO_CLK>;
3211 clock-names = "iface", "ref";
3212
3213 status = "disabled";
3214 };
3215
3216 mdss_dp0: displayport-controller@ae90000 {
3217 compatible = "qcom,sc8180x-dp";
3218 reg = <0 0xae90000 0 0x200>,
3219 <0 0xae90200 0 0x200>,
3220 <0 0xae90400 0 0x600>,
3221 <0 0xae90a00 0 0x400>,
3222 <0 0xae91000 0 0x400>;
3223 interrupt-parent = <&mdss>;
3224 interrupts = <12>;
3225 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3226 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3227 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3228 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3229 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3230 clock-names = "core_iface",
3231 "core_aux",
3232 "ctrl_link",
3233 "ctrl_link_iface",
3234 "stream_pixel";
3235
3236 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3237 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3238 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3239 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3240
3241 phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
3242 phy-names = "dp";
3243
3244 #sound-dai-cells = <0>;
3245
3246 operating-points-v2 = <&dp0_opp_table>;
3247 power-domains = <&rpmhpd SC8180X_MMCX>;
3248
3249 status = "disabled";
3250
3251 ports {
3252 #address-cells = <1>;
3253 #size-cells = <0>;
3254
3255 port@0 {
3256 reg = <0>;
3257 dp0_in: endpoint {
3258 remote-endpoint = <&dpu_intf0_out>;
3259 };
3260 };
3261
3262 port@1 {
3263 reg = <1>;
3264 mdss_dp0_out: endpoint {
3265 };
3266 };
3267 };
3268
3269 dp0_opp_table: opp-table {
3270 compatible = "operating-points-v2";
3271
3272 opp-160000000 {
3273 opp-hz = /bits/ 64 <160000000>;
3274 required-opps = <&rpmhpd_opp_low_svs>;
3275 };
3276
3277 opp-270000000 {
3278 opp-hz = /bits/ 64 <270000000>;
3279 required-opps = <&rpmhpd_opp_svs>;
3280 };
3281
3282 opp-540000000 {
3283 opp-hz = /bits/ 64 <540000000>;
3284 required-opps = <&rpmhpd_opp_svs_l1>;
3285 };
3286
3287 opp-810000000 {
3288 opp-hz = /bits/ 64 <810000000>;
3289 required-opps = <&rpmhpd_opp_nom>;
3290 };
3291 };
3292 };
3293
3294 mdss_dp1: displayport-controller@ae98000 {
3295 compatible = "qcom,sc8180x-dp";
3296 reg = <0 0xae98000 0 0x200>,
3297 <0 0xae98200 0 0x200>,
3298 <0 0xae98400 0 0x600>,
3299 <0 0xae98a00 0 0x400>,
3300 <0 0xae99000 0 0x400>;
3301 interrupt-parent = <&mdss>;
3302 interrupts = <13>;
3303 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3304 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
3305 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
3306 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
3307 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
3308 clock-names = "core_iface",
3309 "core_aux",
3310 "ctrl_link",
3311 "ctrl_link_iface",
3312 "stream_pixel";
3313
3314 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3315 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
3316 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3317 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3318
3319 phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
3320 phy-names = "dp";
3321
3322 #sound-dai-cells = <0>;
3323
3324 operating-points-v2 = <&dp0_opp_table>;
3325 power-domains = <&rpmhpd SC8180X_MMCX>;
3326
3327 status = "disabled";
3328
3329 ports {
3330 #address-cells = <1>;
3331 #size-cells = <0>;
3332
3333 port@0 {
3334 reg = <0>;
3335 dp1_in: endpoint {
3336 remote-endpoint = <&dpu_intf4_out>;
3337 };
3338 };
3339
3340 port@1 {
3341 reg = <1>;
3342 mdss_dp1_out: endpoint {
3343 };
3344 };
3345 };
3346
3347 dp1_opp_table: opp-table {
3348 compatible = "operating-points-v2";
3349
3350 opp-160000000 {
3351 opp-hz = /bits/ 64 <160000000>;
3352 required-opps = <&rpmhpd_opp_low_svs>;
3353 };
3354
3355 opp-270000000 {
3356 opp-hz = /bits/ 64 <270000000>;
3357 required-opps = <&rpmhpd_opp_svs>;
3358 };
3359
3360 opp-540000000 {
3361 opp-hz = /bits/ 64 <540000000>;
3362 required-opps = <&rpmhpd_opp_svs_l1>;
3363 };
3364
3365 opp-810000000 {
3366 opp-hz = /bits/ 64 <810000000>;
3367 required-opps = <&rpmhpd_opp_nom>;
3368 };
3369 };
3370 };
3371
3372 mdss_edp: displayport-controller@ae9a000 {
3373 compatible = "qcom,sc8180x-edp";
3374 reg = <0 0xae9a000 0 0x200>,
3375 <0 0xae9a200 0 0x200>,
3376 <0 0xae9a400 0 0x600>,
3377 <0 0xae9aa00 0 0x400>;
3378 interrupt-parent = <&mdss>;
3379 interrupts = <14>;
3380 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3381 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3382 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
3383 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
3384 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
3385 clock-names = "core_iface",
3386 "core_aux",
3387 "ctrl_link",
3388 "ctrl_link_iface",
3389 "stream_pixel";
3390
3391 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3392 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
3393 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3394
3395 phys = <&edp_phy>;
3396 phy-names = "dp";
3397
3398 operating-points-v2 = <&edp_opp_table>;
3399 power-domains = <&rpmhpd SC8180X_MMCX>;
3400
3401 status = "disabled";
3402
3403 ports {
3404 #address-cells = <1>;
3405 #size-cells = <0>;
3406
3407 port@0 {
3408 reg = <0>;
3409 edp_in: endpoint {
3410 remote-endpoint = <&dpu_intf5_out>;
3411 };
3412 };
3413 };
3414
3415 edp_opp_table: opp-table {
3416 compatible = "operating-points-v2";
3417
3418 opp-160000000 {
3419 opp-hz = /bits/ 64 <160000000>;
3420 required-opps = <&rpmhpd_opp_low_svs>;
3421 };
3422
3423 opp-270000000 {
3424 opp-hz = /bits/ 64 <270000000>;
3425 required-opps = <&rpmhpd_opp_svs>;
3426 };
3427
3428 opp-540000000 {
3429 opp-hz = /bits/ 64 <540000000>;
3430 required-opps = <&rpmhpd_opp_svs_l1>;
3431 };
3432
3433 opp-810000000 {
3434 opp-hz = /bits/ 64 <810000000>;
3435 required-opps = <&rpmhpd_opp_nom>;
3436 };
3437 };
3438 };
3439 };
3440
3441 edp_phy: phy@aec2a00 {
3442 compatible = "qcom,sc8180x-edp-phy";
3443 reg = <0 0x0aec2a00 0 0x1c0>,
3444 <0 0x0aec2200 0 0xa0>,
3445 <0 0x0aec2600 0 0xa0>,
3446 <0 0x0aec2000 0 0x19c>;
3447
3448 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3449 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3450 clock-names = "aux", "cfg_ahb";
3451
3452 power-domains = <&rpmhpd SC8180X_MX>;
3453
3454 #clock-cells = <1>;
3455 #phy-cells = <0>;
3456 };
3457
3458 dispcc: clock-controller@af00000 {
3459 compatible = "qcom,sc8180x-dispcc";
3460 reg = <0 0x0af00000 0 0x20000>;
3461 clocks = <&rpmhcc RPMH_CXO_CLK>,
3462 <&mdss_dsi0_phy 0>,
3463 <&mdss_dsi0_phy 1>,
3464 <&mdss_dsi1_phy 0>,
3465 <&mdss_dsi1_phy 1>,
3466 <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3467 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3468 <&edp_phy 0>,
3469 <&edp_phy 1>,
3470 <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3471 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3472 clock-names = "bi_tcxo",
3473 "dsi0_phy_pll_out_byteclk",
3474 "dsi0_phy_pll_out_dsiclk",
3475 "dsi1_phy_pll_out_byteclk",
3476 "dsi1_phy_pll_out_dsiclk",
3477 "dp_phy_pll_link_clk",
3478 "dp_phy_pll_vco_div_clk",
3479 "edp_phy_pll_link_clk",
3480 "edp_phy_pll_vco_div_clk",
3481 "dptx1_phy_pll_link_clk",
3482 "dptx1_phy_pll_vco_div_clk";
3483 power-domains = <&rpmhpd SC8180X_MMCX>;
3484 required-opps = <&rpmhpd_opp_low_svs>;
3485 #clock-cells = <1>;
3486 #reset-cells = <1>;
3487 #power-domain-cells = <1>;
3488 };
3489
3490 pdc: interrupt-controller@b220000 {
3491 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3492 reg = <0 0x0b220000 0 0x30000>;
3493 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3494 #interrupt-cells = <2>;
3495 interrupt-parent = <&intc>;
3496 interrupt-controller;
3497 };
3498
3499 tsens0: thermal-sensor@c263000 {
3500 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3501 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3502 <0 0x0c222000 0 0x1ff>; /* SROT */
3503 #qcom,sensors = <16>;
3504 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3505 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3506 interrupt-names = "uplow", "critical";
3507 #thermal-sensor-cells = <1>;
3508 };
3509
3510 tsens1: thermal-sensor@c265000 {
3511 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3512 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3513 <0 0x0c223000 0 0x1ff>; /* SROT */
3514 #qcom,sensors = <9>;
3515 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3516 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3517 interrupt-names = "uplow", "critical";
3518 #thermal-sensor-cells = <1>;
3519 };
3520
3521 aoss_qmp: power-controller@c300000 {
3522 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3523 reg = <0x0 0x0c300000 0x0 0x400>;
3524 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3525 mboxes = <&apss_shared 0>;
3526
3527 #clock-cells = <0>;
3528 };
3529
3530 sram@c3f0000 {
3531 compatible = "qcom,rpmh-stats";
3532 reg = <0x0 0x0c3f0000 0x0 0x400>;
3533 };
3534
3535 spmi_bus: spmi@c440000 {
3536 compatible = "qcom,spmi-pmic-arb";
3537 reg = <0x0 0x0c440000 0x0 0x0001100>,
3538 <0x0 0x0c600000 0x0 0x2000000>,
3539 <0x0 0x0e600000 0x0 0x0100000>,
3540 <0x0 0x0e700000 0x0 0x00a0000>,
3541 <0x0 0x0c40a000 0x0 0x0026000>;
3542 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3543 interrupt-names = "periph_irq";
3544 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3545 qcom,ee = <0>;
3546 qcom,channel = <0>;
3547 #address-cells = <2>;
3548 #size-cells = <0>;
3549 interrupt-controller;
3550 #interrupt-cells = <4>;
3551 };
3552
3553 apps_smmu: iommu@15000000 {
3554 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3555 reg = <0 0x15000000 0 0x100000>;
3556 #iommu-cells = <2>;
3557 #global-interrupts = <1>;
3558 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3628 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3629 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3630 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3631 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3632 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3633 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3634 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3635 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3636 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3637 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3638 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3639 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3640 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3641 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3642 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3643 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3644 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3645 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3646 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3647 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3648 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3649 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3650 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3651 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3652 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3653 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
3654 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
3655 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
3656 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
3657 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
3658 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
3659 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
3660 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
3661 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
3662 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
3663 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
3664 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>;
3665
3666 };
3667
3668 remoteproc_adsp: remoteproc@17300000 {
3669 compatible = "qcom,sc8180x-adsp-pas";
3670 reg = <0x0 0x17300000 0x0 0x4040>;
3671
3672 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3673 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3674 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3675 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3676 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3677 interrupt-names = "wdog", "fatal", "ready",
3678 "handover", "stop-ack";
3679
3680 clocks = <&rpmhcc RPMH_CXO_CLK>;
3681 clock-names = "xo";
3682
3683 power-domains = <&rpmhpd SC8180X_CX>;
3684 power-domain-names = "cx";
3685
3686 qcom,qmp = <&aoss_qmp>;
3687
3688 qcom,smem-states = <&adsp_smp2p_out 0>;
3689 qcom,smem-state-names = "stop";
3690
3691 status = "disabled";
3692
3693 remoteproc_adsp_glink: glink-edge {
3694 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3695 label = "lpass";
3696 qcom,remote-pid = <2>;
3697 mboxes = <&apss_shared 8>;
3698 };
3699 };
3700
3701 intc: interrupt-controller@17a00000 {
3702 compatible = "arm,gic-v3";
3703 interrupt-controller;
3704 #interrupt-cells = <3>;
3705 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3706 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3707 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3708 #redistributor-regions = <1>;
3709 redistributor-stride = <0 0x20000>;
3710 };
3711
3712 apss_shared: mailbox@17c00000 {
3713 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3714 reg = <0x0 0x17c00000 0x0 0x1000>;
3715 #mbox-cells = <1>;
3716 };
3717
3718 timer@17c20000 {
3719 compatible = "arm,armv7-timer-mem";
3720 reg = <0x0 0x17c20000 0x0 0x1000>;
3721
3722 #address-cells = <1>;
3723 #size-cells = <1>;
3724 ranges = <0 0 0 0x20000000>;
3725
3726 frame@17c21000 {
3727 reg = <0x17c21000 0x1000>,
3728 <0x17c22000 0x1000>;
3729 frame-number = <0>;
3730 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3731 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3732 };
3733
3734 frame@17c23000 {
3735 reg = <0x17c23000 0x1000>;
3736 frame-number = <1>;
3737 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3738 status = "disabled";
3739 };
3740
3741 frame@17c25000 {
3742 reg = <0x17c25000 0x1000>;
3743 frame-number = <2>;
3744 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3745 status = "disabled";
3746 };
3747
3748 frame@17c27000 {
3749 reg = <0x17c26000 0x1000>;
3750 frame-number = <3>;
3751 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3752 status = "disabled";
3753 };
3754
3755 frame@17c29000 {
3756 reg = <0x17c29000 0x1000>;
3757 frame-number = <4>;
3758 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3759 status = "disabled";
3760 };
3761
3762 frame@17c2b000 {
3763 reg = <0x17c2b000 0x1000>;
3764 frame-number = <5>;
3765 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3766 status = "disabled";
3767 };
3768
3769 frame@17c2d000 {
3770 reg = <0x17c2d000 0x1000>;
3771 frame-number = <6>;
3772 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3773 status = "disabled";
3774 };
3775 };
3776
3777 apps_rsc: rsc@18200000 {
3778 compatible = "qcom,rpmh-rsc";
3779 reg = <0x0 0x18200000 0x0 0x10000>,
3780 <0x0 0x18210000 0x0 0x10000>,
3781 <0x0 0x18220000 0x0 0x10000>;
3782 reg-names = "drv-0", "drv-1", "drv-2";
3783 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3784 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3785 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3786 qcom,tcs-offset = <0xd00>;
3787 qcom,drv-id = <2>;
3788 qcom,tcs-config = <ACTIVE_TCS 2>,
3789 <SLEEP_TCS 1>,
3790 <WAKE_TCS 1>,
3791 <CONTROL_TCS 0>;
3792 label = "apps_rsc";
3793 power-domains = <&CLUSTER_PD>;
3794
3795 apps_bcm_voter: bcm-voter {
3796 compatible = "qcom,bcm-voter";
3797 };
3798
3799 rpmhcc: clock-controller {
3800 compatible = "qcom,sc8180x-rpmh-clk";
3801 #clock-cells = <1>;
3802 clock-names = "xo";
3803 clocks = <&xo_board_clk>;
3804 };
3805
3806 rpmhpd: power-controller {
3807 compatible = "qcom,sc8180x-rpmhpd";
3808 #power-domain-cells = <1>;
3809 operating-points-v2 = <&rpmhpd_opp_table>;
3810
3811 rpmhpd_opp_table: opp-table {
3812 compatible = "operating-points-v2";
3813
3814 rpmhpd_opp_ret: opp1 {
3815 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3816 };
3817
3818 rpmhpd_opp_min_svs: opp2 {
3819 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3820 };
3821
3822 rpmhpd_opp_low_svs: opp3 {
3823 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3824 };
3825
3826 rpmhpd_opp_svs: opp4 {
3827 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3828 };
3829
3830 rpmhpd_opp_svs_l1: opp5 {
3831 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3832 };
3833
3834 rpmhpd_opp_nom: opp6 {
3835 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3836 };
3837
3838 rpmhpd_opp_nom_l1: opp7 {
3839 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3840 };
3841
3842 rpmhpd_opp_nom_l2: opp8 {
3843 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3844 };
3845
3846 rpmhpd_opp_turbo: opp9 {
3847 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3848 };
3849
3850 rpmhpd_opp_turbo_l1: opp10 {
3851 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3852 };
3853 };
3854 };
3855 };
3856
3857 osm_l3: interconnect@18321000 {
3858 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3859 reg = <0 0x18321000 0 0x1400>;
3860
3861 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3862 clock-names = "xo", "alternate";
3863
3864 #interconnect-cells = <1>;
3865 };
3866
3867 lmh@18350800 {
3868 compatible = "qcom,sc8180x-lmh";
3869 reg = <0 0x18350800 0 0x400>;
3870 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3871 cpus = <&CPU4>;
3872 qcom,lmh-temp-arm-millicelsius = <65000>;
3873 qcom,lmh-temp-low-millicelsius = <94500>;
3874 qcom,lmh-temp-high-millicelsius = <95000>;
3875 interrupt-controller;
3876 #interrupt-cells = <1>;
3877 };
3878
3879 lmh@18358800 {
3880 compatible = "qcom,sc8180x-lmh";
3881 reg = <0 0x18358800 0 0x400>;
3882 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3883 cpus = <&CPU0>;
3884 qcom,lmh-temp-arm-millicelsius = <65000>;
3885 qcom,lmh-temp-low-millicelsius = <94500>;
3886 qcom,lmh-temp-high-millicelsius = <95000>;
3887 interrupt-controller;
3888 #interrupt-cells = <1>;
3889 };
3890
3891 cpufreq_hw: cpufreq@18323000 {
3892 compatible = "qcom,cpufreq-hw";
3893 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3894 reg-names = "freq-domain0", "freq-domain1";
3895
3896 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3897 clock-names = "xo", "alternate";
3898
3899 #freq-domain-cells = <1>;
3900 #clock-cells = <1>;
3901 };
3902
3903 wifi: wifi@18800000 {
3904 compatible = "qcom,wcn3990-wifi";
3905 reg = <0 0x18800000 0 0x800000>;
3906 reg-names = "membase";
3907 clock-names = "cxo_ref_clk_pin";
3908 clocks = <&rpmhcc RPMH_RF_CLK2>;
3909 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3910 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3911 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3912 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3913 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3914 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3915 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3916 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3917 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3918 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3919 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3920 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3921 iommus = <&apps_smmu 0x0640 0x1>;
3922 qcom,msa-fixed-perm;
3923 status = "disabled";
3924 };
3925 };
3926
3927 thermal-zones {
3928 cpu0-thermal {
3929 polling-delay-passive = <250>;
3930
3931 thermal-sensors = <&tsens0 1>;
3932
3933 trips {
3934 cpu-crit {
3935 temperature = <110000>;
3936 hysteresis = <1000>;
3937 type = "critical";
3938 };
3939 };
3940 };
3941
3942 cpu1-thermal {
3943 polling-delay-passive = <250>;
3944
3945 thermal-sensors = <&tsens0 2>;
3946
3947 trips {
3948 cpu-crit {
3949 temperature = <110000>;
3950 hysteresis = <1000>;
3951 type = "critical";
3952 };
3953 };
3954 };
3955
3956 cpu2-thermal {
3957 polling-delay-passive = <250>;
3958
3959 thermal-sensors = <&tsens0 3>;
3960
3961 trips {
3962 cpu-crit {
3963 temperature = <110000>;
3964 hysteresis = <1000>;
3965 type = "critical";
3966 };
3967 };
3968 };
3969
3970 cpu3-thermal {
3971 polling-delay-passive = <250>;
3972
3973 thermal-sensors = <&tsens0 4>;
3974
3975 trips {
3976 cpu-crit {
3977 temperature = <110000>;
3978 hysteresis = <1000>;
3979 type = "critical";
3980 };
3981 };
3982 };
3983
3984 cpu4-top-thermal {
3985 polling-delay-passive = <250>;
3986
3987 thermal-sensors = <&tsens0 7>;
3988
3989 trips {
3990 cpu-crit {
3991 temperature = <110000>;
3992 hysteresis = <1000>;
3993 type = "critical";
3994 };
3995 };
3996 };
3997
3998 cpu5-top-thermal {
3999 polling-delay-passive = <250>;
4000
4001 thermal-sensors = <&tsens0 8>;
4002
4003 trips {
4004 cpu-crit {
4005 temperature = <110000>;
4006 hysteresis = <1000>;
4007 type = "critical";
4008 };
4009 };
4010 };
4011
4012 cpu6-top-thermal {
4013 polling-delay-passive = <250>;
4014
4015 thermal-sensors = <&tsens0 9>;
4016
4017 trips {
4018 cpu-crit {
4019 temperature = <110000>;
4020 hysteresis = <1000>;
4021 type = "critical";
4022 };
4023 };
4024 };
4025
4026 cpu7-top-thermal {
4027 polling-delay-passive = <250>;
4028
4029 thermal-sensors = <&tsens0 10>;
4030
4031 trips {
4032 cpu-crit {
4033 temperature = <110000>;
4034 hysteresis = <1000>;
4035 type = "critical";
4036 };
4037 };
4038 };
4039
4040 cpu4-bottom-thermal {
4041 polling-delay-passive = <250>;
4042
4043 thermal-sensors = <&tsens0 11>;
4044
4045 trips {
4046 cpu-crit {
4047 temperature = <110000>;
4048 hysteresis = <1000>;
4049 type = "critical";
4050 };
4051 };
4052 };
4053
4054 cpu5-bottom-thermal {
4055 polling-delay-passive = <250>;
4056
4057 thermal-sensors = <&tsens0 12>;
4058
4059 trips {
4060 cpu-crit {
4061 temperature = <110000>;
4062 hysteresis = <1000>;
4063 type = "critical";
4064 };
4065 };
4066 };
4067
4068 cpu6-bottom-thermal {
4069 polling-delay-passive = <250>;
4070
4071 thermal-sensors = <&tsens0 13>;
4072
4073 trips {
4074 cpu-crit {
4075 temperature = <110000>;
4076 hysteresis = <1000>;
4077 type = "critical";
4078 };
4079 };
4080 };
4081
4082 cpu7-bottom-thermal {
4083 polling-delay-passive = <250>;
4084
4085 thermal-sensors = <&tsens0 14>;
4086
4087 trips {
4088 cpu-crit {
4089 temperature = <110000>;
4090 hysteresis = <1000>;
4091 type = "critical";
4092 };
4093 };
4094 };
4095
4096 aoss0-thermal {
4097 polling-delay-passive = <250>;
4098
4099 thermal-sensors = <&tsens0 0>;
4100
4101 trips {
4102 trip-point0 {
4103 temperature = <90000>;
4104 hysteresis = <2000>;
4105 type = "hot";
4106 };
4107 };
4108 };
4109
4110 cluster0-thermal {
4111 polling-delay-passive = <250>;
4112
4113 thermal-sensors = <&tsens0 5>;
4114
4115 trips {
4116 cluster-crit {
4117 temperature = <110000>;
4118 hysteresis = <2000>;
4119 type = "critical";
4120 };
4121 };
4122 };
4123
4124 cluster1-thermal {
4125 polling-delay-passive = <250>;
4126
4127 thermal-sensors = <&tsens0 6>;
4128
4129 trips {
4130 cluster-crit {
4131 temperature = <110000>;
4132 hysteresis = <2000>;
4133 type = "critical";
4134 };
4135 };
4136 };
4137
4138 gpu-top-thermal {
4139 polling-delay-passive = <250>;
4140
4141 thermal-sensors = <&tsens0 15>;
4142
4143 cooling-maps {
4144 map0 {
4145 trip = <&gpu_top_alert0>;
4146 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4147 };
4148 };
4149
4150 trips {
4151 gpu_top_alert0: trip-point0 {
4152 temperature = <85000>;
4153 hysteresis = <1000>;
4154 type = "passive";
4155 };
4156
4157 trip-point1 {
4158 temperature = <90000>;
4159 hysteresis = <1000>;
4160 type = "hot";
4161 };
4162
4163 trip-point2 {
4164 temperature = <110000>;
4165 hysteresis = <1000>;
4166 type = "critical";
4167 };
4168 };
4169 };
4170
4171 aoss1-thermal {
4172 polling-delay-passive = <250>;
4173
4174 thermal-sensors = <&tsens1 0>;
4175
4176 trips {
4177 trip-point0 {
4178 temperature = <90000>;
4179 hysteresis = <2000>;
4180 type = "hot";
4181 };
4182 };
4183 };
4184
4185 wlan-thermal {
4186 polling-delay-passive = <250>;
4187
4188 thermal-sensors = <&tsens1 1>;
4189
4190 trips {
4191 trip-point0 {
4192 temperature = <90000>;
4193 hysteresis = <2000>;
4194 type = "hot";
4195 };
4196 };
4197 };
4198
4199 video-thermal {
4200 polling-delay-passive = <250>;
4201
4202 thermal-sensors = <&tsens1 2>;
4203
4204 trips {
4205 trip-point0 {
4206 temperature = <90000>;
4207 hysteresis = <2000>;
4208 type = "hot";
4209 };
4210 };
4211 };
4212
4213 mem-thermal {
4214 polling-delay-passive = <250>;
4215
4216 thermal-sensors = <&tsens1 3>;
4217
4218 trips {
4219 trip-point0 {
4220 temperature = <90000>;
4221 hysteresis = <2000>;
4222 type = "hot";
4223 };
4224 };
4225 };
4226
4227 q6-hvx-thermal {
4228 polling-delay-passive = <250>;
4229
4230 thermal-sensors = <&tsens1 4>;
4231
4232 trips {
4233 trip-point0 {
4234 temperature = <90000>;
4235 hysteresis = <2000>;
4236 type = "hot";
4237 };
4238 };
4239 };
4240
4241 camera-thermal {
4242 polling-delay-passive = <250>;
4243
4244 thermal-sensors = <&tsens1 5>;
4245
4246 trips {
4247 trip-point0 {
4248 temperature = <90000>;
4249 hysteresis = <2000>;
4250 type = "hot";
4251 };
4252 };
4253 };
4254
4255 compute-thermal {
4256 polling-delay-passive = <250>;
4257
4258 thermal-sensors = <&tsens1 6>;
4259
4260 trips {
4261 trip-point0 {
4262 temperature = <90000>;
4263 hysteresis = <2000>;
4264 type = "hot";
4265 };
4266 };
4267 };
4268
4269 mdm-dsp-thermal {
4270 polling-delay-passive = <250>;
4271
4272 thermal-sensors = <&tsens1 7>;
4273
4274 trips {
4275 trip-point0 {
4276 temperature = <90000>;
4277 hysteresis = <2000>;
4278 type = "hot";
4279 };
4280 };
4281 };
4282
4283 npu-thermal {
4284 polling-delay-passive = <250>;
4285
4286 thermal-sensors = <&tsens1 8>;
4287
4288 trips {
4289 trip-point0 {
4290 temperature = <90000>;
4291 hysteresis = <2000>;
4292 type = "hot";
4293 };
4294 };
4295 };
4296
4297 gpu-bottom-thermal {
4298 polling-delay-passive = <250>;
4299
4300 thermal-sensors = <&tsens1 11>;
4301
4302 cooling-maps {
4303 map0 {
4304 trip = <&gpu_bottom_alert0>;
4305 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4306 };
4307 };
4308
4309 trips {
4310 gpu_bottom_alert0: trip-point0 {
4311 temperature = <85000>;
4312 hysteresis = <1000>;
4313 type = "passive";
4314 };
4315
4316 trip-point1 {
4317 temperature = <90000>;
4318 hysteresis = <1000>;
4319 type = "hot";
4320 };
4321
4322 trip-point2 {
4323 temperature = <110000>;
4324 hysteresis = <1000>;
4325 type = "critical";
4326 };
4327 };
4328 };
4329 };
4330
4331 timer {
4332 compatible = "arm,armv8-timer";
4333 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4334 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4335 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4336 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4337 };
4338 };
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