1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Google Cheza board device tree source
4 *
5 * Copyright 2018 Google LLC.
6 */
7
8 /dts-v1/;
9
10 #include "sdm845-cheza.dtsi"
11
12 / {
13 model = "Google Cheza (rev3+)";
14 compatible = "google,cheza", "qcom,sdm845";
15 };
16
17 /* PINCTRL - board-specific pinctrl */
18
19 &tlmm {
20 gpio-line-names = "AP_SPI_FP_MISO",
21 "AP_SPI_FP_MOSI",
22 "AP_SPI_FP_CLK",
23 "AP_SPI_FP_CS_L",
24 "UART_AP_TX_DBG_RX",
25 "UART_DBG_TX_AP_RX",
26 "BRIJ_SUSPEND",
27 "FP_RST_L",
28 "FCAM_EN",
29 "",
30 "EDP_BRIJ_IRQ",
31 "EC_IN_RW_ODL",
32 "",
33 "RCAM_MCLK",
34 "FCAM_MCLK",
35 "",
36 "RCAM_EN",
37 "CCI0_SDA",
38 "CCI0_SCL",
39 "CCI1_SDA",
40 "CCI1_SCL",
41 "FCAM_RST_L",
42 "FPMCU_BOOT0",
43 "PEN_RST_L",
44 "PEN_IRQ_L",
45 "FPMCU_SEL_OD",
46 "RCAM_VSYNC",
47 "ESIM_MISO",
48 "ESIM_MOSI",
49 "ESIM_CLK",
50 "ESIM_CS_L",
51 "AP_PEN_1V8_SDA",
52 "AP_PEN_1V8_SCL",
53 "AP_TS_I2C_SDA",
54 "AP_TS_I2C_SCL",
55 "RCAM_RST_L",
56 "",
57 "AP_EDP_BKLTEN",
58 "AP_BRD_ID0",
59 "BOOT_CONFIG_4",
60 "AMP_IRQ_L",
61 "EDP_BRIJ_I2C_SDA",
62 "EDP_BRIJ_I2C_SCL",
63 "EN_PP3300_DX_EDP",
64 "SD_CD_ODL",
65 "BT_UART_RTS",
66 "BT_UART_CTS",
67 "BT_UART_RXD",
68 "BT_UART_TXD",
69 "AMP_I2C_SDA",
70 "AMP_I2C_SCL",
71 "AP_BRD_ID2",
72 "",
73 "AP_EC_SPI_CLK",
74 "AP_EC_SPI_CS_L",
75 "AP_EC_SPI_MISO",
76 "AP_EC_SPI_MOSI",
77 "FORCED_USB_BOOT",
78 "AMP_BCLK",
79 "AMP_LRCLK",
80 "AMP_DOUT",
81 "AMP_DIN",
82 "AP_BRD_ID1",
83 "PEN_PDCT_L",
84 "HP_MCLK",
85 "HP_BCLK",
86 "HP_LRCLK",
87 "HP_DOUT",
88 "HP_DIN",
89 "",
90 "",
91 "",
92 "",
93 "BT_SLIMBUS_DATA",
94 "BT_SLIMBUS_CLK",
95 "AMP_RESET_L",
96 "",
97 "FCAM_VSYNC",
98 "",
99 "AP_SKU_ID0",
100 "EC_WOV_BCLK",
101 "EC_WOV_LRCLK",
102 "EC_WOV_DOUT",
103 "",
104 "",
105 "AP_H1_SPI_MISO",
106 "AP_H1_SPI_MOSI",
107 "AP_H1_SPI_CLK",
108 "AP_H1_SPI_CS_L",
109 "",
110 "AP_SPI_CS0_L",
111 "AP_SPI_MOSI",
112 "AP_SPI_MISO",
113 "",
114 "",
115 "AP_SPI_CLK",
116 "",
117 "RFFE6_CLK",
118 "RFFE6_DATA",
119 "BOOT_CONFIG_1",
120 "BOOT_CONFIG_2",
121 "BOOT_CONFIG_0",
122 "EDP_BRIJ_EN",
123 "",
124 "USB_HS_TX_EN",
125 "UIM2_DATA",
126 "UIM2_CLK",
127 "UIM2_RST",
128 "UIM2_PRESENT",
129 "UIM1_DATA",
130 "UIM1_CLK",
131 "UIM1_RST",
132 "",
133 "AP_SKU_ID1",
134 "SDM_GRFC_8",
135 "SDM_GRFC_9",
136 "AP_RST_REQ",
137 "HP_IRQ",
138 "TS_RESET_L",
139 "PEN_EJECT_ODL",
140 "HUB_RST_L",
141 "FP_TO_AP_IRQ",
142 "AP_EC_INT_L",
143 "",
144 "",
145 "TS_INT_L",
146 "AP_SUSPEND_L",
147 "SDM_GRFC_3",
148 /*
149 * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
150 * call it BIOS_FLASH_WP_R_L.
151 */
152 "AP_FLASH_WP_L",
153 "H1_AP_INT_ODL",
154 "QLINK_REQ",
155 "QLINK_EN",
156 "SDM_GRFC_2",
157 "BOOT_CONFIG_3",
158 "WMSS_RESET_L",
159 "SDM_GRFC_0",
160 "SDM_GRFC_1",
161 "RFFE3_DATA",
162 "RFFE3_CLK",
163 "RFFE4_DATA",
164 "RFFE4_CLK",
165 "RFFE5_DATA",
166 "RFFE5_CLK",
167 "GNSS_EN",
168 "WCI2_LTE_COEX_RXD",
169 "WCI2_LTE_COEX_TXD",
170 "AP_RAM_ID0",
171 "AP_RAM_ID1",
172 "RFFE1_DATA",
173 "RFFE1_CLK";
174 };
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