1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Samsung Galaxy Book2
4 *
5 * Copyright (c) 2022, Xilin Wu <strongtz@yeah.net>
6 */
7
8 /dts-v1/;
9
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 #include <dt-bindings/sound/qcom,q6afe.h>
15 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm850.dtsi"
17 #include "sdm845-wcd9340.dtsi"
18 #include "pm8998.dtsi"
19
20 /*
21 * Update following upstream (sdm845.dtsi) reserved
22 * memory mappings for firmware loading to succeed
23 */
24 /delete-node/ &qseecom_mem;
25 /delete-node/ &wlan_msa_mem;
26 /delete-node/ &slpi_mem;
27 /delete-node/ &ipa_fw_mem;
28 /delete-node/ &ipa_gsi_mem;
29 /delete-node/ &gpu_mem;
30 /delete-node/ &mpss_region;
31 /delete-node/ &adsp_mem;
32 /delete-node/ &cdsp_mem;
33 /delete-node/ &venus_mem;
34 /delete-node/ &mba_region;
35 /delete-node/ &spss_mem;
36
37 / {
38 model = "Samsung Galaxy Book2";
39 compatible = "samsung,w737", "qcom,sdm845";
40 chassis-type = "convertible";
41
42 chosen {
43 #address-cells = <2>;
44 #size-cells = <2>;
45 ranges;
46
47 /* Firmware initialized the display at 1280p instead of 1440p */
48 framebuffer0: framebuffer@80400000 {
49 compatible = "simple-framebuffer";
50 reg = <0 0x80400000 0 (1920 * 1280 * 4)>;
51 width = <1920>;
52 height = <1280>;
53 stride = <(1920 * 4)>;
54 format = "a8r8g8b8";
55 };
56 };
57
58 aliases {
59 serial1 = &uart6;
60 };
61
62 /* Reserved memory changes */
63 reserved-memory {
64 /* Bootloader display framebuffer region */
65 cont_splash_mem: memory@80400000 {
66 reg = <0x0 0x80400000 0x0 0x960000>;
67 no-map;
68 };
69
70 qseecom_mem: memory@8b500000 {
71 reg = <0 0x8b500000 0 0xa00000>;
72 no-map;
73 };
74
75 wlan_msa_mem: memory@8c400000 {
76 reg = <0 0x8c400000 0 0x100000>;
77 no-map;
78 };
79
80 slpi_mem: memory@8c500000 {
81 reg = <0 0x8c500000 0 0x1200000>;
82 no-map;
83 };
84
85 ipa_fw_mem: memory@8d700000 {
86 reg = <0 0x8d700000 0 0x100000>;
87 no-map;
88 };
89
90 gpu_mem: memory@8d800000 {
91 reg = <0 0x8d800000 0 0x5000>;
92 no-map;
93 };
94
95 mpss_region: memory@8e000000 {
96 reg = <0 0x8e000000 0 0x8000000>;
97 no-map;
98 };
99
100 adsp_mem: memory@96000000 {
101 reg = <0 0x96000000 0 0x2000000>;
102 no-map;
103 };
104
105 cdsp_mem: memory@98000000 {
106 reg = <0 0x98000000 0 0x800000>;
107 no-map;
108 };
109
110 venus_mem: memory@98800000 {
111 reg = <0 0x98800000 0 0x500000>;
112 no-map;
113 };
114
115 mba_region: memory@98d00000 {
116 reg = <0 0x98d00000 0 0x200000>;
117 no-map;
118 };
119
120 spss_mem: memory@98f00000 {
121 reg = <0 0x98f00000 0 0x100000>;
122 no-map;
123 };
124 };
125 };
126
127 &adsp_pas {
128 firmware-name = "qcom/sdm850/samsung/w737/qcadsp850.mbn";
129 status = "okay";
130 };
131
132 &apps_rsc {
133 regulators-0 {
134 compatible = "qcom,pm8998-rpmh-regulators";
135 qcom,pmic-id = "a";
136
137 vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
138 vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
139
140 vreg_s2a_1p125: smps2 {
141 };
142
143 vreg_s3a_1p35: smps3 {
144 regulator-min-microvolt = <1352000>;
145 regulator-max-microvolt = <1352000>;
146 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
147 };
148
149 vreg_s4a_1p8: smps4 {
150 regulator-min-microvolt = <1800000>;
151 regulator-max-microvolt = <1800000>;
152 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
153 };
154
155 vreg_s5a_2p04: smps5 {
156 regulator-min-microvolt = <2040000>;
157 regulator-max-microvolt = <2040000>;
158 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
159 };
160
161 vreg_s7a_1p025: smps7 {
162 };
163
164 vdd_qusb_hs0:
165 vdda_hp_pcie_core:
166 vdda_mipi_csi0_0p9:
167 vdda_mipi_csi1_0p9:
168 vdda_mipi_csi2_0p9:
169 vdda_mipi_dsi0_pll:
170 vdda_mipi_dsi1_pll:
171 vdda_qlink_lv:
172 vdda_qlink_lv_ck:
173 vdda_qrefs_0p875:
174 vdda_pcie_core:
175 vdda_pll_cc_ebi01:
176 vdda_pll_cc_ebi23:
177 vdda_sp_sensor:
178 vdda_ufs1_core:
179 vdda_ufs2_core:
180 vdda_usb1_ss_core:
181 vdda_usb2_ss_core:
182 vreg_l1a_0p875: ldo1 {
183 regulator-min-microvolt = <880000>;
184 regulator-max-microvolt = <880000>;
185 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
186 };
187
188 vddpx_10:
189 vreg_l2a_1p2: ldo2 {
190 regulator-min-microvolt = <1200000>;
191 regulator-max-microvolt = <1200000>;
192 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
193 regulator-always-on;
194 };
195
196 vreg_l3a_1p0: ldo3 {
197 };
198
199 vdd_wcss_cx:
200 vdd_wcss_mx:
201 vdda_wcss_pll:
202 vreg_l5a_0p8: ldo5 {
203 regulator-min-microvolt = <800000>;
204 regulator-max-microvolt = <800000>;
205 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
206 };
207
208 vddpx_13:
209 vreg_l6a_1p8: ldo6 {
210 regulator-min-microvolt = <1800000>;
211 regulator-max-microvolt = <1800000>;
212 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
213 };
214
215 vreg_l7a_1p8: ldo7 {
216 regulator-min-microvolt = <1800000>;
217 regulator-max-microvolt = <1800000>;
218 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
219 };
220
221 vreg_l8a_1p2: ldo8 {
222 };
223
224 vreg_l9a_1p8: ldo9 {
225 };
226
227 vreg_l10a_1p8: ldo10 {
228 };
229
230 vreg_l11a_1p0: ldo11 {
231 };
232
233 vdd_qfprom:
234 vdd_qfprom_sp:
235 vdda_apc1_cs_1p8:
236 vdda_gfx_cs_1p8:
237 vdda_qrefs_1p8:
238 vdda_qusb_hs0_1p8:
239 vddpx_11:
240 vreg_l12a_1p8: ldo12 {
241 regulator-min-microvolt = <1800000>;
242 regulator-max-microvolt = <1800000>;
243 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
244 };
245
246 vddpx_2:
247 vreg_l13a_2p95: ldo13 {
248 };
249
250 vreg_l14a_1p88: ldo14 {
251 regulator-min-microvolt = <1880000>;
252 regulator-max-microvolt = <1880000>;
253 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
254 regulator-always-on;
255 };
256
257 vreg_l15a_1p8: ldo15 {
258 };
259
260 vreg_l16a_2p7: ldo16 {
261 };
262
263 vreg_l17a_1p3: ldo17 {
264 regulator-min-microvolt = <1304000>;
265 regulator-max-microvolt = <1304000>;
266 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
267 };
268
269 vreg_l18a_1p8: ldo18 {
270 };
271
272 vreg_l19a_3p0: ldo19 {
273 regulator-min-microvolt = <3100000>;
274 regulator-max-microvolt = <3108000>;
275 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
276 };
277
278 vreg_l20a_2p95: ldo20 {
279 regulator-min-microvolt = <2960000>;
280 regulator-max-microvolt = <2960000>;
281 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
282 };
283
284 vreg_l21a_2p95: ldo21 {
285 };
286
287 vreg_l22a_2p85: ldo22 {
288 };
289
290 vreg_l23a_3p3: ldo23 {
291 regulator-min-microvolt = <3300000>;
292 regulator-max-microvolt = <3312000>;
293 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
294 };
295
296 vdda_qusb_hs0_3p1:
297 vreg_l24a_3p075: ldo24 {
298 regulator-min-microvolt = <3075000>;
299 regulator-max-microvolt = <3083000>;
300 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
301 };
302
303 vreg_l25a_3p3: ldo25 {
304 regulator-min-microvolt = <3104000>;
305 regulator-max-microvolt = <3112000>;
306 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
307 };
308
309 vdda_hp_pcie_1p2:
310 vdda_hv_ebi0:
311 vdda_hv_ebi1:
312 vdda_hv_ebi2:
313 vdda_hv_ebi3:
314 vdda_mipi_csi_1p25:
315 vdda_mipi_dsi0_1p2:
316 vdda_mipi_dsi1_1p2:
317 vdda_pcie_1p2:
318 vdda_ufs1_1p2:
319 vdda_ufs2_1p2:
320 vdda_usb1_ss_1p2:
321 vdda_usb2_ss_1p2:
322 vreg_l26a_1p2: ldo26 {
323 regulator-min-microvolt = <1200000>;
324 regulator-max-microvolt = <1208000>;
325 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
326 };
327
328 vreg_l28a_3p0: ldo28 {
329 };
330
331 vreg_lvs1a_1p8: lvs1 {
332 };
333
334 vreg_lvs2a_1p8: lvs2 {
335 };
336 };
337 };
338
339 &cdsp_pas {
340 firmware-name = "qcom/sdm850/samsung/w737/qccdsp850.mbn";
341 status = "okay";
342 };
343
344 &gcc {
345 protected-clocks = <GCC_QSPI_CORE_CLK>,
346 <GCC_QSPI_CORE_CLK_SRC>,
347 <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
348 <GCC_LPASS_Q6_AXI_CLK>,
349 <GCC_LPASS_SWAY_CLK>;
350 };
351
352 &i2c10 {
353 status = "okay";
354 clock-frequency = <400000>;
355
356 /* SN65DSI86 @ 0x2c */
357 /* The panel requires dual DSI, which is not supported by the bridge driver */
358 };
359
360 &i2c11 {
361 status = "okay";
362 clock-frequency = <400000>;
363
364 /* HID-I2C Touchscreen @ 0x20 */
365 };
366
367 &i2c15 {
368 status = "okay";
369 clock-frequency = <400000>;
370
371 digitizer@9 {
372 compatible = "wacom,w9013", "hid-over-i2c";
373 reg = <0x9>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;
376
377 post-power-on-delay-ms = <120>;
378
379 interrupt-parent = <&tlmm>;
380 interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
381
382 hid-descr-addr = <0x1>;
383 };
384 };
385
386 &ipa {
387 qcom,gsi-loader = "self";
388 memory-region = <&ipa_fw_mem>;
389 firmware-name = "qcom/sdm850/samsung/w737/ipa_fws.elf";
390 status = "okay";
391 };
392
393 /* No idea why it causes an SError when enabled */
394 &llcc {
395 status = "disabled";
396 };
397
398 &mss_pil {
399 status = "okay";
400 firmware-name = "qcom/sdm850/samsung/w737/qcdsp1v2850.mbn", "qcom/sdm850/samsung/w737/qcdsp2850.mbn";
401 };
402
403 &qup_i2c10_default {
404 drive-strength = <2>;
405 bias-disable;
406 };
407
408 &qup_i2c11_default {
409 drive-strength = <2>;
410 bias-disable;
411 };
412
413 &qup_i2c12_default {
414 drive-strength = <2>;
415 bias-disable;
416 };
417
418 &qupv3_id_0 {
419 status = "okay";
420 };
421
422 &qupv3_id_1 {
423 status = "okay";
424 };
425
426 &q6asmdai {
427 dai@0 {
428 reg = <0>;
429 };
430
431 dai@1 {
432 reg = <1>;
433 };
434
435 dai@2 {
436 reg = <2>;
437 };
438 };
439
440 &sound {
441 compatible = "qcom,sdm845-sndcard";
442 model = "Samsung-W737";
443
444 audio-routing =
445 "RX_BIAS", "MCLK",
446 "AMIC2", "MIC BIAS2",
447 "SpkrLeft IN", "SPK1 OUT",
448 "SpkrRight IN", "SPK2 OUT",
449 "MM_DL1", "MultiMedia1 Playback",
450 "MM_DL3", "MultiMedia3 Playback",
451 "MultiMedia2 Capture", "MM_UL2";
452
453 mm1-dai-link {
454 link-name = "MultiMedia1";
455 cpu {
456 sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
457 };
458 };
459
460 mm2-dai-link {
461 link-name = "MultiMedia2";
462 cpu {
463 sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
464 };
465 };
466
467 mm3-dai-link {
468 link-name = "MultiMedia3";
469 cpu {
470 sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
471 };
472 };
473
474 slim-dai-link {
475 link-name = "SLIM Playback";
476 cpu {
477 sound-dai = <&q6afedai SLIMBUS_0_RX>;
478 };
479
480 platform {
481 sound-dai = <&q6routing>;
482 };
483
484 codec {
485 sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
486 };
487 };
488
489 slimcap-dai-link {
490 link-name = "SLIM Capture";
491 cpu {
492 sound-dai = <&q6afedai SLIMBUS_0_TX>;
493 };
494
495 platform {
496 sound-dai = <&q6routing>;
497 };
498
499 codec {
500 sound-dai = <&wcd9340 1>;
501 };
502 };
503
504 slim-wcd-dai-link {
505 link-name = "SLIM WCD Playback";
506 cpu {
507 sound-dai = <&q6afedai SLIMBUS_1_RX>;
508 };
509
510 platform {
511 sound-dai = <&q6routing>;
512 };
513
514 codec {
515 sound-dai = <&wcd9340 2>;
516 };
517 };
518 };
519
520 &tlmm {
521 gpio-reserved-ranges = <0 6>, <85 4>;
522
523 pen_irq_l: pen-irq-l-state {
524 pins = "gpio119";
525 function = "gpio";
526 bias-disable;
527 };
528
529 pen_pdct_l: pen-pdct-l-state {
530 pins = "gpio124";
531 function = "gpio";
532 bias-disable;
533 drive-strength = <2>;
534 output-high;
535 };
536
537 pen_rst_l: pen-rst-l-state {
538 pins = "gpio21";
539 function = "gpio";
540 bias-disable;
541 drive-strength = <2>;
542
543 /*
544 * The pen driver doesn't currently support
545 * driving this reset line. By specifying
546 * output-high here we're relying on the fact
547 * that this pin has a default pulldown at boot
548 * (which makes sure the pen was in reset if it
549 * was powered) and then we set it high here to
550 * take it out of reset. Better would be if the
551 * pen driver could control this and we could
552 * remove "output-high" here.
553 */
554 output-high;
555 };
556 };
557
558 &uart6 {
559 pinctrl-names = "default";
560 pinctrl-0 = <&qup_uart6_4pin>;
561 status = "okay";
562
563 bluetooth {
564 compatible = "qcom,wcn3990-bt";
565
566 vddio-supply = <&vreg_s4a_1p8>;
567 vddxo-supply = <&vreg_l7a_1p8>;
568 vddrf-supply = <&vreg_l17a_1p3>;
569 vddch0-supply = <&vreg_l25a_3p3>;
570 vddch1-supply = <&vreg_l23a_3p3>;
571 max-speed = <3200000>;
572 };
573 };
574
575 &ufs_mem_hc {
576 status = "okay";
577
578 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
579
580 vcc-supply = <&vreg_l20a_2p95>;
581 vcc-max-microamp = <600000>;
582 };
583
584 &ufs_mem_phy {
585 status = "okay";
586
587 vdda-phy-supply = <&vdda_ufs1_core>;
588 vdda-pll-supply = <&vdda_ufs1_1p2>;
589 };
590
591 &usb_1 {
592 status = "okay";
593 };
594
595 &usb_1_dwc3 {
596 dr_mode = "host";
597 };
598
599 &usb_1_hsphy {
600 status = "okay";
601
602 vdd-supply = <&vdda_usb1_ss_core>;
603 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
604 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
605
606 qcom,imp-res-offset-value = <8>;
607 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
608 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
609 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
610 };
611
612 &usb_1_qmpphy {
613 status = "okay";
614
615 vdda-phy-supply = <&vdda_usb1_ss_1p2>;
616 vdda-pll-supply = <&vdda_usb1_ss_core>;
617 };
618
619 &usb_2 {
620 status = "okay";
621 };
622
623 &usb_2_dwc3 {
624 dr_mode = "host";
625 };
626
627 &usb_2_hsphy {
628 status = "okay";
629
630 vdd-supply = <&vdda_usb2_ss_core>;
631 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
632 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
633
634 qcom,imp-res-offset-value = <8>;
635 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
636 };
637
638 &usb_2_qmpphy {
639 status = "okay";
640
641 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
642 vdda-pll-supply = <&vdda_usb2_ss_core>;
643 };
644
645 &venus {
646 status = "okay";
647 firmware-name = "qcom/sdm850/samsung/w737/qcvss850.mbn";
648 };
649
650 &wcd9340 {
651 reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
652 vdd-buck-supply = <&vreg_s4a_1p8>;
653 vdd-buck-sido-supply = <&vreg_s4a_1p8>;
654 vdd-tx-supply = <&vreg_s4a_1p8>;
655 vdd-rx-supply = <&vreg_s4a_1p8>;
656 vdd-io-supply = <&vreg_s4a_1p8>;
657 qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
658 qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
659 qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
660
661 swm: soundwire@c85 {
662 left_spkr: speaker@0,3 {
663 compatible = "sdw10217211000";
664 reg = <0 3>;
665 powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>;
666 #thermal-sensor-cells = <0>;
667 sound-name-prefix = "SpkrLeft";
668 #sound-dai-cells = <0>;
669 };
670
671 right_spkr: speaker@0,4 {
672 compatible = "sdw10217211000";
673 powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>;
674 reg = <0 4>;
675 #thermal-sensor-cells = <0>;
676 sound-name-prefix = "SpkrRight";
677 #sound-dai-cells = <0>;
678 };
679 };
680 };
681
682 &wifi {
683 status = "okay";
684
685 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
686 vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
687 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
688 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
689 vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
690
691 qcom,snoc-host-cap-8bit-quirk;
692 };
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