1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SDX75 SoC device tree source
4 *
5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 */
8
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20
21 / {
22 #address-cells = <2>;
23 #size-cells = <2>;
24 interrupt-parent = <&intc>;
25
26 chosen: chosen { };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 clock-frequency = <76800000>;
32 #clock-cells = <0>;
33 };
34
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 clock-frequency = <32000>;
38 #clock-cells = <0>;
39 };
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
51 enable-method = "psci";
52 power-domains = <&CPU_PD0>;
53 power-domain-names = "psci";
54 qcom,freq-domain = <&cpufreq_hw 0>;
55 capacity-dmips-mhz = <1024>;
56 dynamic-power-coefficient = <100>;
57 next-level-cache = <&L2_0>;
58
59 L2_0: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
65 compatible = "cache";
66 cache-level = <3>;
67 cache-unified;
68 };
69 };
70 };
71
72 CPU1: cpu@100 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 0>;
77 enable-method = "psci";
78 power-domains = <&CPU_PD1>;
79 power-domain-names = "psci";
80 qcom,freq-domain = <&cpufreq_hw 0>;
81 capacity-dmips-mhz = <1024>;
82 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L2_100>;
84
85 L2_100: l2-cache {
86 compatible = "cache";
87 cache-level = <2>;
88 cache-unified;
89 next-level-cache = <&L3_0>;
90 };
91 };
92
93 CPU2: cpu@200 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a55";
96 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci";
99 power-domains = <&CPU_PD2>;
100 power-domain-names = "psci";
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 capacity-dmips-mhz = <1024>;
103 dynamic-power-coefficient = <100>;
104 next-level-cache = <&L2_200>;
105
106 L2_200: l2-cache {
107 compatible = "cache";
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&L3_0>;
111 };
112 };
113
114 CPU3: cpu@300 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a55";
117 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 0>;
119 enable-method = "psci";
120 power-domains = <&CPU_PD3>;
121 power-domain-names = "psci";
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 capacity-dmips-mhz = <1024>;
124 dynamic-power-coefficient = <100>;
125 next-level-cache = <&L2_300>;
126
127 L2_300: l2-cache {
128 compatible = "cache";
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
132 };
133 };
134
135 cpu-map {
136 cluster0 {
137 core0 {
138 cpu = <&CPU0>;
139 };
140
141 core1 {
142 cpu = <&CPU1>;
143 };
144
145 core2 {
146 cpu = <&CPU2>;
147 };
148
149 core3 {
150 cpu = <&CPU3>;
151 };
152 };
153 };
154
155 idle-states {
156 entry-method = "psci";
157
158 CPU_OFF: cpu-sleep-0 {
159 compatible = "arm,idle-state";
160 entry-latency-us = <235>;
161 exit-latency-us = <428>;
162 min-residency-us = <1774>;
163 arm,psci-suspend-param = <0x40000003>;
164 local-timer-stop;
165 };
166
167 CPU_RAIL_OFF: cpu-rail-sleep-1 {
168 compatible = "arm,idle-state";
169 entry-latency-us = <800>;
170 exit-latency-us = <750>;
171 min-residency-us = <4090>;
172 arm,psci-suspend-param = <0x40000004>;
173 local-timer-stop;
174 };
175
176 };
177
178 domain-idle-states {
179 CLUSTER_SLEEP_0: cluster-sleep-0 {
180 compatible = "domain-idle-state";
181 arm,psci-suspend-param = <0x41000044>;
182 entry-latency-us = <1050>;
183 exit-latency-us = <2500>;
184 min-residency-us = <5309>;
185 };
186
187 CLUSTER_SLEEP_1: cluster-sleep-1 {
188 compatible = "domain-idle-state";
189 arm,psci-suspend-param = <0x41001344>;
190 entry-latency-us = <2761>;
191 exit-latency-us = <3964>;
192 min-residency-us = <8467>;
193 };
194
195 CLUSTER_SLEEP_2: cluster-sleep-2 {
196 compatible = "domain-idle-state";
197 arm,psci-suspend-param = <0x4100b344>;
198 entry-latency-us = <2793>;
199 exit-latency-us = <4023>;
200 min-residency-us = <9826>;
201 };
202 };
203 };
204
205 firmware {
206 scm: scm {
207 compatible = "qcom,scm-sdx75", "qcom,scm";
208 };
209 };
210
211 clk_virt: interconnect-0 {
212 compatible = "qcom,sdx75-clk-virt";
213 #interconnect-cells = <2>;
214 qcom,bcm-voters = <&apps_bcm_voter>;
215 clocks = <&rpmhcc RPMH_QPIC_CLK>;
216 };
217
218 mc_virt: interconnect-1 {
219 compatible = "qcom,sdx75-mc-virt";
220 #interconnect-cells = <2>;
221 qcom,bcm-voters = <&apps_bcm_voter>;
222 };
223
224 memory@80000000 {
225 device_type = "memory";
226 reg = <0x0 0x80000000 0x0 0x0>;
227 };
228
229 pmu {
230 compatible = "arm,cortex-a55-pmu";
231 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 };
233
234 psci {
235 compatible = "arm,psci-1.0";
236 method = "smc";
237
238 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells = <0>;
240 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
242 };
243
244 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells = <0>;
246 power-domains = <&CLUSTER_PD>;
247 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
248 };
249
250 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells = <0>;
252 power-domains = <&CLUSTER_PD>;
253 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
254 };
255
256 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells = <0>;
258 power-domains = <&CLUSTER_PD>;
259 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
260 };
261
262 CLUSTER_PD: power-domain-cpu-cluster0 {
263 #power-domain-cells = <0>;
264 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
265 };
266 };
267
268 reserved-memory {
269 #address-cells = <2>;
270 #size-cells = <2>;
271 ranges;
272
273 gunyah_hyp_mem: gunyah-hyp@80000000 {
274 reg = <0x0 0x80000000 0x0 0x800000>;
275 no-map;
276 };
277
278 hyp_elf_package_mem: hyp-elf-package@80800000 {
279 reg = <0x0 0x80800000 0x0 0x200000>;
280 no-map;
281 };
282
283 access_control_db_mem: access-control-db@81380000 {
284 reg = <0x0 0x81380000 0x0 0x80000>;
285 no-map;
286 };
287
288 qteetz_mem: qteetz@814e0000 {
289 reg = <0x0 0x814e0000 0x0 0x2a0000>;
290 no-map;
291 };
292
293 trusted_apps_mem: trusted-apps@81780000 {
294 reg = <0x0 0x81780000 0x0 0xa00000>;
295 no-map;
296 };
297
298 xbl_ramdump_mem: xbl-ramdump@87a00000 {
299 reg = <0x0 0x87a00000 0x0 0x1c0000>;
300 no-map;
301 };
302
303 cpucp_fw_mem: cpucp-fw@87c00000 {
304 reg = <0x0 0x87c00000 0x0 0x100000>;
305 no-map;
306 };
307
308 xbl_dtlog_mem: xbl-dtlog@87d00000 {
309 reg = <0x0 0x87d00000 0x0 0x40000>;
310 no-map;
311 };
312
313 xbl_sc_mem: xbl-sc@87d40000 {
314 reg = <0x0 0x87d40000 0x0 0x40000>;
315 no-map;
316 };
317
318 modem_efs_shared_mem: modem-efs-shared@87d80000 {
319 reg = <0x0 0x87d80000 0x0 0x10000>;
320 no-map;
321 };
322
323 aop_image_mem: aop-image@87e00000 {
324 reg = <0x0 0x87e00000 0x0 0x20000>;
325 no-map;
326 };
327
328 smem_mem: smem@87e20000 {
329 reg = <0x0 0x87e20000 0x0 0xc0000>;
330 no-map;
331 };
332
333 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
334 compatible = "qcom,cmd-db";
335 reg = <0x0 0x87ee0000 0x0 0x20000>;
336 no-map;
337 };
338
339 aop_config_mem: aop-config@87f00000 {
340 reg = <0x0 0x87f00000 0x0 0x20000>;
341 no-map;
342 };
343
344 ipa_fw_mem: ipa-fw@87f20000 {
345 reg = <0x0 0x87f20000 0x0 0x10000>;
346 no-map;
347 };
348
349 secdata_mem: secdata@87f30000 {
350 reg = <0x0 0x87f30000 0x0 0x1000>;
351 no-map;
352 };
353
354 tme_crashdump_mem: tme-crashdump@87f31000 {
355 reg = <0x0 0x87f31000 0x0 0x40000>;
356 no-map;
357 };
358
359 tme_log_mem: tme-log@87f71000 {
360 reg = <0x0 0x87f71000 0x0 0x4000>;
361 no-map;
362 };
363
364 uefi_log_mem: uefi-log@87f75000 {
365 reg = <0x0 0x87f75000 0x0 0x10000>;
366 no-map;
367 };
368
369 qdss_mem: qdss@88500000 {
370 reg = <0x0 0x88500000 0x0 0x300000>;
371 no-map;
372 };
373
374 qlink_logging_mem: qlink-logging@88800000 {
375 reg = <0x0 0x88800000 0x0 0x300000>;
376 no-map;
377 };
378
379 audio_heap_mem: audio-heap@88b00000 {
380 compatible = "shared-dma-pool";
381 reg = <0x0 0x88b00000 0x0 0x400000>;
382 no-map;
383 };
384
385 mpss_dsm_mem_2: mpss-dsm-2@88f00000 {
386 reg = <0x0 0x88f00000 0x0 0x2500000>;
387 no-map;
388 };
389
390 mpss_dsm_mem: mpss-dsm@8b400000 {
391 reg = <0x0 0x8b400000 0x0 0x2b80000>;
392 no-map;
393 };
394
395 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
396 reg = <0x0 0x8df80000 0x0 0x80000>;
397 no-map;
398 };
399
400 mpssadsp_mem: mpssadsp@8e000000 {
401 reg = <0x0 0x8e000000 0x0 0xf100000>;
402 no-map;
403 };
404
405 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
406 reg = <0x0 0xbdb00000 0x0 0x2000000>;
407 no-map;
408 };
409
410 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
411 reg = <0x0 0xbfb00000 0x0 0x100000>;
412 no-map;
413 };
414
415 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
416 reg = <0x0 0xbfc00000 0x0 0x400000>;
417 no-map;
418 };
419 };
420
421 smp2p-modem {
422 compatible = "qcom,smp2p";
423 qcom,smem = <435>, <428>;
424 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
425 IPCC_MPROC_SIGNAL_SMP2P
426 IRQ_TYPE_EDGE_RISING>;
427 mboxes = <&ipcc IPCC_CLIENT_MPSS
428 IPCC_MPROC_SIGNAL_SMP2P>;
429
430 qcom,local-pid = <0>;
431 qcom,remote-pid = <1>;
432
433 smp2p_modem_out: master-kernel {
434 qcom,entry-name = "master-kernel";
435 #qcom,smem-state-cells = <1>;
436 };
437
438 smp2p_modem_in: slave-kernel {
439 qcom,entry-name = "slave-kernel";
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 };
443
444 ipa_smp2p_out: ipa-ap-to-modem {
445 qcom,entry-name = "ipa";
446 #qcom,smem-state-cells = <1>;
447 };
448
449 ipa_smp2p_in: ipa-modem-to-ap {
450 qcom,entry-name = "ipa";
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 };
454 };
455
456 smem: smem {
457 compatible = "qcom,smem";
458 memory-region = <&smem_mem>;
459 hwlocks = <&tcsr_mutex 3>;
460 };
461
462 soc: soc@0 {
463 compatible = "simple-bus";
464 #address-cells = <2>;
465 #size-cells = <2>;
466 ranges = <0 0 0 0 0x10 0>;
467 dma-ranges = <0 0 0 0 0x10 0>;
468
469 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx75-gcc";
471 reg = <0x0 0x0080000 0x0 0x1f7400>;
472 clocks = <&rpmhcc RPMH_CXO_CLK>,
473 <&sleep_clk>,
474 <0>,
475 <0>,
476 <0>,
477 <0>,
478 <0>,
479 <0>,
480 <0>,
481 <0>,
482 <0>,
483 <0>,
484 <0>,
485 <0>,
486 <0>;
487 #clock-cells = <1>;
488 #reset-cells = <1>;
489 #power-domain-cells = <1>;
490 };
491
492 ipcc: mailbox@408000 {
493 compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
494 reg = <0 0x00408000 0 0x1000>;
495 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-controller;
497 #interrupt-cells = <3>;
498 #mbox-cells = <2>;
499 };
500
501 gpi_dma: dma-controller@900000 {
502 compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
503 reg = <0x0 0x00900000 0x0 0x60000>;
504 #dma-cells = <3>;
505 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
517 dma-channels = <12>;
518 dma-channel-mask = <0x7f>;
519 iommus = <&apps_smmu 0xf6 0x0>;
520 status = "disabled";
521 };
522
523 qupv3_id_0: geniqup@9c0000 {
524 compatible = "qcom,geni-se-qup";
525 reg = <0x0 0x009c0000 0x0 0x2000>;
526 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
527 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
528 clock-names = "m-ahb",
529 "s-ahb";
530 iommus = <&apps_smmu 0xe3 0x0>;
531 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
532 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
533 interconnect-names = "qup-core";
534 #address-cells = <2>;
535 #size-cells = <2>;
536 ranges;
537 status = "disabled";
538
539 i2c0: i2c@980000 {
540 compatible = "qcom,geni-i2c";
541 reg = <0x0 0x00980000 0x0 0x4000>;
542 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
543 clock-names = "se";
544 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 pinctrl-0 = <&qup_i2c0_data_clk>;
548 pinctrl-names = "default";
549 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
550 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
552 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
553 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
555 interconnect-names = "qup-core", "qup-config", "qup-memory";
556 dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
557 <&gpi_dma 1 0 QCOM_GPI_I2C>;
558 dma-names = "tx", "rx";
559 status = "disabled";
560 };
561
562 spi0: spi@980000 {
563 compatible = "qcom,geni-spi";
564 reg = <0x0 0x00980000 0x0 0x4000>;
565 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
566 clock-names = "se";
567 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
568 #address-cells = <1>;
569 #size-cells = <0>;
570 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
571 pinctrl-names = "default";
572 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
573 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
574 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
575 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
576 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
577 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
578 interconnect-names = "qup-core", "qup-config", "qup-memory";
579 dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
580 <&gpi_dma 1 0 QCOM_GPI_SPI>;
581 dma-names = "tx", "rx";
582 status = "disabled";
583 };
584
585 uart1: serial@984000 {
586 compatible = "qcom,geni-debug-uart";
587 reg = <0x0 0x00984000 0x0 0x4000>;
588 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
589 clock-names = "se";
590 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
591 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
592 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
593 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
594 interconnect-names = "qup-core",
595 "qup-config";
596 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-0 = <&qupv3_se1_2uart_active>;
598 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
599 pinctrl-names = "default",
600 "sleep";
601 status = "disabled";
602 };
603
604 i2c2: i2c@988000 {
605 compatible = "qcom,geni-i2c";
606 reg = <0x0 0x00988000 0x0 0x4000>;
607 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
608 clock-names = "se";
609 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
610 #address-cells = <1>;
611 #size-cells = <0>;
612 pinctrl-0 = <&qup_i2c2_data_clk>;
613 pinctrl-names = "default";
614 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
615 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
616 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
617 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
618 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
619 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
620 interconnect-names = "qup-core", "qup-config", "qup-memory";
621 dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
622 <&gpi_dma 1 2 QCOM_GPI_I2C>;
623 dma-names = "tx", "rx";
624 status = "disabled";
625 };
626
627 spi2: spi@988000 {
628 compatible = "qcom,geni-spi";
629 reg = <0x0 0x00988000 0x0 0x4000>;
630 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
631 clock-names = "se";
632 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
636 pinctrl-names = "default";
637 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
638 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
639 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
640 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
641 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
643 interconnect-names = "qup-core", "qup-config", "qup-memory";
644 dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
645 <&gpi_dma 1 2 QCOM_GPI_SPI>;
646 dma-names = "tx", "rx";
647 status = "disabled";
648 };
649
650 i2c3: i2c@98c000 {
651 compatible = "qcom,geni-i2c";
652 reg = <0x0 0x0098c000 0x0 0x4000>;
653 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
654 clock-names = "se";
655 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
656 #address-cells = <1>;
657 #size-cells = <0>;
658 pinctrl-0 = <&qup_i2c3_data_clk>;
659 pinctrl-names = "default";
660 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
661 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
662 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
663 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
664 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
665 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
666 interconnect-names = "qup-core", "qup-config", "qup-memory";
667 dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
668 <&gpi_dma 1 3 QCOM_GPI_I2C>;
669 dma-names = "tx", "rx";
670 status = "disabled";
671 };
672
673 spi3: spi@98c000 {
674 compatible = "qcom,geni-spi";
675 reg = <0x0 0x0098c000 0x0 0x4000>;
676 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
677 clock-names = "se";
678 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
679 #address-cells = <1>;
680 #size-cells = <0>;
681 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
682 pinctrl-names = "default";
683 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
684 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
685 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
686 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
687 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
688 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
689 interconnect-names = "qup-core", "qup-config", "qup-memory";
690 dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
691 <&gpi_dma 1 3 QCOM_GPI_SPI>;
692 dma-names = "tx", "rx";
693 status = "disabled";
694 };
695
696 uart4: serial@990000 {
697 compatible = "qcom,geni-uart";
698 reg = <0x0 0x00990000 0x0 0x4000>;
699 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
700 clock-names = "se";
701 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
702 pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
703 pinctrl-names = "default";
704 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
705 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
706 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
707 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
708 interconnect-names = "qup-core", "qup-config";
709 status = "disabled";
710 };
711
712 i2c5: i2c@994000 {
713 compatible = "qcom,geni-i2c";
714 reg = <0x0 0x00994000 0x0 0x4000>;
715 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
716 clock-names = "se";
717 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 pinctrl-0 = <&qup_i2c5_data_clk>;
721 pinctrl-names = "default";
722 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
723 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
724 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
725 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
726 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
727 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
728 interconnect-names = "qup-core", "qup-config", "qup-memory";
729 dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
730 <&gpi_dma 1 5 QCOM_GPI_I2C>;
731 dma-names = "tx", "rx";
732 status = "disabled";
733 };
734
735 i2c6: i2c@998000 {
736 compatible = "qcom,geni-i2c";
737 reg = <0x0 0x00998000 0x0 0x4000>;
738 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
739 clock-names = "se";
740 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
741 #address-cells = <1>;
742 #size-cells = <0>;
743 pinctrl-0 = <&qup_i2c6_data_clk>;
744 pinctrl-names = "default";
745 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
746 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
747 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
748 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
749 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
750 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
751 interconnect-names = "qup-core", "qup-config", "qup-memory";
752 dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
753 <&gpi_dma 1 6 QCOM_GPI_I2C>;
754 dma-names = "tx", "rx";
755 status = "disabled";
756 };
757
758 spi6: spi@998000 {
759 compatible = "qcom,geni-spi";
760 reg = <0x0 0x00998000 0x0 0x4000>;
761 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
762 clock-names = "se";
763 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
764 #address-cells = <1>;
765 #size-cells = <0>;
766 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
767 pinctrl-names = "default";
768 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
769 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
770 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
771 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
772 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
773 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
774 interconnect-names = "qup-core", "qup-config", "qup-memory";
775 dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
776 <&gpi_dma 1 6 QCOM_GPI_SPI>;
777 dma-names = "tx", "rx";
778 status = "disabled";
779 };
780
781 i2c7: i2c@99c000 {
782 compatible = "qcom,geni-i2c";
783 reg = <0x0 0x0099c000 0x0 0x4000>;
784 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
785 clock-names = "se";
786 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells = <1>;
788 #size-cells = <0>;
789 pinctrl-0 = <&qup_i2c7_data_clk>;
790 pinctrl-names = "default";
791 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
792 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
793 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
794 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
795 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
796 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
797 interconnect-names = "qup-core", "qup-config", "qup-memory";
798 dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
799 <&gpi_dma 1 7 QCOM_GPI_I2C>;
800 dma-names = "tx", "rx";
801 status = "disabled";
802 };
803
804 spi7: spi@99c000 {
805 compatible = "qcom,geni-spi";
806 reg = <0x0 0x0099c000 0x0 0x4000>;
807 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
808 clock-names = "se";
809 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
810 #address-cells = <1>;
811 #size-cells = <0>;
812 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
813 pinctrl-names = "default";
814 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
815 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
816 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
817 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
818 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
820 interconnect-names = "qup-core", "qup-config", "qup-memory";
821 dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
822 <&gpi_dma 1 7 QCOM_GPI_SPI>;
823 dma-names = "tx", "rx";
824 status = "disabled";
825 };
826 };
827
828 usb_hsphy: phy@ff4000 {
829 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
830 reg = <0x0 0x00ff4000 0x0 0x154>;
831 #phy-cells = <0>;
832
833 clocks = <&rpmhcc RPMH_CXO_CLK>;
834 clock-names = "ref";
835
836 resets = <&gcc GCC_QUSB2PHY_BCR>;
837
838 status = "disabled";
839 };
840
841 usb_qmpphy: phy@ff6000 {
842 compatible = "qcom,sdx75-qmp-usb3-uni-phy";
843 reg = <0x0 0x00ff6000 0x0 0x2000>;
844
845 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
846 <&gcc GCC_USB2_CLKREF_EN>,
847 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
848 <&gcc GCC_USB3_PHY_PIPE_CLK>;
849 clock-names = "aux",
850 "ref",
851 "cfg_ahb",
852 "pipe";
853
854 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
855
856 resets = <&gcc GCC_USB3_PHY_BCR>,
857 <&gcc GCC_USB3PHY_PHY_BCR>;
858 reset-names = "phy",
859 "phy_phy";
860
861 #clock-cells = <0>;
862 clock-output-names = "usb3_uni_phy_pipe_clk_src";
863
864 #phy-cells = <0>;
865
866 status = "disabled";
867 };
868
869 system_noc: interconnect@1640000 {
870 compatible = "qcom,sdx75-system-noc";
871 reg = <0x0 0x01640000 0x0 0x4b400>;
872 #interconnect-cells = <2>;
873 qcom,bcm-voters = <&apps_bcm_voter>;
874 };
875
876 pcie_anoc: interconnect@16c0000 {
877 compatible = "qcom,sdx75-pcie-anoc";
878 reg = <0x0 0x016c0000 0x0 0x14200>;
879 #interconnect-cells = <2>;
880 qcom,bcm-voters = <&apps_bcm_voter>;
881 };
882
883 tcsr_mutex: hwlock@1f40000 {
884 compatible = "qcom,tcsr-mutex";
885 reg = <0x0 0x01f40000 0x0 0x40000>;
886 #hwlock-cells = <1>;
887 };
888
889 tcsr: syscon@1fc0000 {
890 compatible = "qcom,sdx75-tcsr", "syscon";
891 reg = <0x0 0x01fc0000 0x0 0x30000>;
892 };
893
894 remoteproc_mpss: remoteproc@4080000 {
895 compatible = "qcom,sdx75-mpss-pas";
896 reg = <0 0x04080000 0 0x4040>;
897
898 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
899 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
900 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
901 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
902 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
903 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
904 interrupt-names = "wdog",
905 "fatal",
906 "ready",
907 "handover",
908 "stop-ack",
909 "shutdown-ack";
910
911 clocks = <&rpmhcc RPMH_CXO_CLK>;
912 clock-names = "xo";
913
914 power-domains = <&rpmhpd RPMHPD_CX>,
915 <&rpmhpd RPMHPD_MSS>;
916 power-domain-names = "cx",
917 "mss";
918
919 memory-region = <&mpssadsp_mem>, <&q6_mpss_dtb_mem>,
920 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
921 <&qlink_logging_mem>;
922
923 qcom,qmp = <&aoss_qmp>;
924
925 qcom,smem-states = <&smp2p_modem_out 0>;
926 qcom,smem-state-names = "stop";
927
928 status = "disabled";
929
930 glink-edge {
931 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
932 IPCC_MPROC_SIGNAL_PING
933 IRQ_TYPE_EDGE_RISING>;
934 mboxes = <&ipcc IPCC_CLIENT_MPSS
935 IPCC_MPROC_SIGNAL_PING>;
936 label = "mpss";
937 qcom,remote-pid = <1>;
938 };
939 };
940
941 sdhc: mmc@8804000 {
942 compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
943 reg = <0x0 0x08804000 0x0 0x1000>;
944
945 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
947 interrupt-names = "hc_irq",
948 "pwr_irq";
949
950 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
951 <&gcc GCC_SDCC1_APPS_CLK>,
952 <&rpmhcc RPMH_CXO_CLK>;
953 clock-names = "iface",
954 "core",
955 "xo";
956 iommus = <&apps_smmu 0x00a0 0x0>;
957 qcom,dll-config = <0x0007442c>;
958 qcom,ddr-config = <0x80040868>;
959 power-domains = <&rpmhpd RPMHPD_CX>;
960 operating-points-v2 = <&sdhc1_opp_table>;
961
962 interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
963 <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
964 interconnect-names = "sdhc-ddr",
965 "cpu-sdhc";
966 bus-width = <4>;
967 dma-coherent;
968
969 /* Forbid SDR104/SDR50 - broken hw! */
970 sdhci-caps-mask = <0x3 0>;
971
972 status = "disabled";
973
974 sdhc1_opp_table: opp-table {
975 compatible = "operating-points-v2";
976
977 opp-100000000 {
978 opp-hz = /bits/ 64 <100000000>;
979 required-opps = <&rpmhpd_opp_low_svs>;
980 };
981
982 opp-384000000 {
983 opp-hz = /bits/ 64 <384000000>;
984 required-opps = <&rpmhpd_opp_nom>;
985 };
986 };
987 };
988
989 usb: usb@a6f8800 {
990 compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
991 reg = <0x0 0x0a6f8800 0x0 0x400>;
992 #address-cells = <2>;
993 #size-cells = <2>;
994 ranges;
995
996 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
997 <&gcc GCC_USB30_MASTER_CLK>,
998 <&gcc GCC_USB30_MSTR_AXI_CLK>,
999 <&gcc GCC_USB30_SLEEP_CLK>,
1000 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1001 clock-names = "cfg_noc",
1002 "core",
1003 "iface",
1004 "sleep",
1005 "mock_utmi";
1006
1007 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1008 <&gcc GCC_USB30_MASTER_CLK>;
1009 assigned-clock-rates = <19200000>, <200000000>;
1010
1011 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1012 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
1013 <&pdc 9 IRQ_TYPE_EDGE_RISING>,
1014 <&pdc 10 IRQ_TYPE_EDGE_RISING>;
1015 interrupt-names = "hs_phy_irq",
1016 "ss_phy_irq",
1017 "dm_hs_phy_irq",
1018 "dp_hs_phy_irq";
1019
1020 power-domains = <&gcc GCC_USB30_GDSC>;
1021
1022 resets = <&gcc GCC_USB30_BCR>;
1023
1024 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
1025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1026 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1027 &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
1028 interconnect-names = "usb-ddr",
1029 "apps-usb";
1030
1031 status = "disabled";
1032
1033 usb_dwc3: usb@a600000 {
1034 compatible = "snps,dwc3";
1035 reg = <0x0 0x0a600000 0x0 0xcd00>;
1036 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1037 iommus = <&apps_smmu 0x80 0x0>;
1038 snps,dis_u2_susphy_quirk;
1039 snps,dis_enblslpm_quirk;
1040 phys = <&usb_hsphy>,
1041 <&usb_qmpphy>;
1042 phy-names = "usb2-phy",
1043 "usb3-phy";
1044
1045 ports {
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1048
1049 port@0 {
1050 reg = <0>;
1051
1052 usb_1_dwc3_hs: endpoint {
1053 };
1054 };
1055
1056 port@1 {
1057 reg = <1>;
1058
1059 usb_1_dwc3_ss: endpoint {
1060 };
1061 };
1062 };
1063 };
1064 };
1065
1066 pdc: interrupt-controller@b220000 {
1067 compatible = "qcom,sdx75-pdc", "qcom,pdc";
1068 reg = <0x0 0xb220000 0x0 0x30000>,
1069 <0x0 0x174000f0 0x0 0x64>;
1070 qcom,pdc-ranges = <0 147 52>,
1071 <52 266 32>,
1072 <84 500 59>;
1073 #interrupt-cells = <2>;
1074 interrupt-parent = <&intc>;
1075 interrupt-controller;
1076 };
1077
1078 aoss_qmp: power-controller@c310000 {
1079 compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
1080 reg = <0 0x0c310000 0 0x1000>;
1081 interrupt-parent = <&ipcc>;
1082 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1083 IRQ_TYPE_EDGE_RISING>;
1084 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1085
1086 #clock-cells = <0>;
1087 };
1088
1089 spmi_bus: spmi@c400000 {
1090 compatible = "qcom,spmi-pmic-arb";
1091 reg = <0x0 0x0c400000 0x0 0x3000>,
1092 <0x0 0x0c500000 0x0 0x400000>,
1093 <0x0 0x0c440000 0x0 0x80000>,
1094 <0x0 0x0c4c0000 0x0 0x10000>,
1095 <0x0 0x0c42d000 0x0 0x4000>;
1096 reg-names = "core",
1097 "chnls",
1098 "obsrvr",
1099 "intr",
1100 "cnfg";
1101 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1102 interrupt-names = "periph_irq";
1103 qcom,ee = <0>;
1104 qcom,channel = <0>;
1105 qcom,bus-id = <0>;
1106 #address-cells = <2>;
1107 #size-cells = <0>;
1108 interrupt-controller;
1109 #interrupt-cells = <4>;
1110 };
1111
1112 tlmm: pinctrl@f000000 {
1113 compatible = "qcom,sdx75-tlmm";
1114 reg = <0x0 0x0f000000 0x0 0x400000>;
1115 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1116 gpio-controller;
1117 #gpio-cells = <2>;
1118 gpio-ranges = <&tlmm 0 0 133>;
1119 interrupt-controller;
1120 #interrupt-cells = <2>;
1121 wakeup-parent = <&pdc>;
1122
1123 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
1124 /* SDA, SCL */
1125 pins = "gpio8", "gpio9";
1126 function = "qup_se0";
1127 drive-strength = <2>;
1128 bias-pull-up;
1129 };
1130
1131 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1132 /* SDA, SCL */
1133 pins = "gpio14", "gpio15";
1134 function = "qup_se2";
1135 drive-strength = <2>;
1136 bias-pull-up;
1137 };
1138
1139 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1140 /* SDA, SCL */
1141 pins = "gpio52", "gpio53";
1142 function = "qup_se3";
1143 drive-strength = <2>;
1144 bias-pull-up;
1145 };
1146
1147 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1148 /* SDA, SCL */
1149 pins = "gpio110", "gpio111";
1150 function = "qup_se5";
1151 drive-strength = <2>;
1152 bias-pull-up;
1153 };
1154
1155 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1156 /* SDA, SCL */
1157 pins = "gpio112", "gpio113";
1158 function = "qup_se6";
1159 drive-strength = <2>;
1160 bias-pull-up;
1161 };
1162
1163 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1164 /* SDA, SCL */
1165 pins = "gpio116", "gpio117";
1166 function = "qup_se7";
1167 drive-strength = <2>;
1168 bias-pull-up;
1169 };
1170
1171 qup_spi0_cs: qup-spi0-cs-state {
1172 pins = "gpio11";
1173 function = "qup_se0";
1174 drive-strength = <6>;
1175 bias-pull-down;
1176 };
1177
1178 qup_spi0_data_clk: qup-spi0-data-clk-state {
1179 /* MISO, MOSI, CLK */
1180 pins = "gpio8", "gpio9", "gpio10";
1181 function = "qup_se0";
1182 drive-strength = <6>;
1183 bias-pull-down;
1184 };
1185
1186 qup_spi2_cs: qup-spi2-cs-state {
1187 pins = "gpio17";
1188 function = "qup_se2";
1189 drive-strength = <6>;
1190 bias-pull-down;
1191 };
1192
1193 qup_spi2_data_clk: qup-spi2-data-clk-state {
1194 /* MISO, MOSI, CLK */
1195 pins = "gpio14", "gpio15", "gpio16";
1196 function = "qup_se2";
1197 drive-strength = <6>;
1198 bias-pull-down;
1199 };
1200
1201 qup_spi3_cs: qup-spi3-cs-state {
1202 pins = "gpio55";
1203 function = "qup_se3";
1204 drive-strength = <6>;
1205 bias-pull-down;
1206 };
1207
1208 qup_spi3_data_clk: qup-spi3-data-clk-state {
1209 /* MISO, MOSI, CLK */
1210 pins = "gpio52", "gpio53", "gpio54";
1211 function = "qup_se3";
1212 drive-strength = <6>;
1213 bias-pull-down;
1214 };
1215
1216 qup_spi6_cs: qup-spi6-cs-state {
1217 pins = "gpio115";
1218 function = "qup_se6";
1219 drive-strength = <6>;
1220 bias-pull-down;
1221 };
1222
1223 qup_spi6_data_clk: qup-spi6-data-clk-state {
1224 /* MISO, MOSI, CLK */
1225 pins = "gpio112", "gpio113", "gpio114";
1226 function = "qup_se6";
1227 drive-strength = <6>;
1228 bias-pull-down;
1229 };
1230
1231 qup_spi7_cs: qup-spi7-cs-state {
1232 pins = "gpio119";
1233 function = "qup_se7";
1234 drive-strength = <6>;
1235 bias-pull-down;
1236 };
1237
1238 qup_spi7_data_clk: qup-spi7-data-clk-state {
1239 /* MISO, MOSI, CLK */
1240 pins = "gpio116", "gpio117", "gpio118";
1241 function = "qup_se7";
1242 drive-strength = <6>;
1243 bias-pull-down;
1244 };
1245
1246 qup_uart4_cts_rts: qup-uart4-cts-rts-state {
1247 /* CTS, RTS */
1248 pins = "gpio52", "gpio53";
1249 function = "qup_se3";
1250 drive-strength = <2>;
1251 bias-pull-down;
1252 };
1253
1254 qup_uart4_default: qup-uart4-default-state {
1255 /* TX, RX */
1256 pins = "gpio54", "gpio55";
1257 function = "qup_se3";
1258 drive-strength = <2>;
1259 bias-pull-up;
1260 };
1261
1262 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1263 tx-pins {
1264 pins = "gpio12";
1265 function = "qup_se1_l2_mira";
1266 drive-strength = <2>;
1267 bias-disable;
1268 };
1269
1270 rx-pins {
1271 pins = "gpio13";
1272 function = "qup_se1_l3_mira";
1273 drive-strength = <2>;
1274 bias-disable;
1275 };
1276 };
1277
1278 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1279 pins = "gpio12", "gpio13";
1280 function = "gpio";
1281 drive-strength = <2>;
1282 bias-pull-down;
1283 };
1284
1285 sdc1_default: sdc1-default-state {
1286 clk-pins {
1287 pins = "sdc1_clk";
1288 drive-strength = <16>;
1289 bias-disable;
1290 };
1291
1292 cmd-pins {
1293 pins = "sdc1_cmd";
1294 drive-strength = <10>;
1295 bias-pull-up;
1296 };
1297
1298 data-pins {
1299 pins = "sdc1_data";
1300 drive-strength = <10>;
1301 bias-pull-up;
1302 };
1303 };
1304
1305 sdc1_sleep: sdc1-sleep-state {
1306 clk-pins {
1307 pins = "sdc1_clk";
1308 drive-strength = <2>;
1309 bias-disable;
1310 };
1311
1312 cmd-pins {
1313 pins = "sdc1_cmd";
1314 drive-strength = <2>;
1315 bias-pull-up;
1316 };
1317
1318 data-pins {
1319 pins = "sdc1_data";
1320 drive-strength = <2>;
1321 bias-pull-up;
1322 };
1323 };
1324 };
1325
1326 apps_smmu: iommu@15000000 {
1327 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1328 reg = <0x0 0x15000000 0x0 0x40000>;
1329 #iommu-cells = <2>;
1330 #global-interrupts = <2>;
1331 dma-coherent;
1332 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1365 };
1366
1367 intc: interrupt-controller@17200000 {
1368 compatible = "arm,gic-v3";
1369 #interrupt-cells = <3>;
1370 interrupt-controller;
1371 #redistributor-regions = <1>;
1372 redistributor-stride = <0x0 0x20000>;
1373 reg = <0x0 0x17200000 0x0 0x10000>,
1374 <0x0 0x17260000 0x0 0x80000>;
1375 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1376 };
1377
1378 timer@17420000 {
1379 compatible = "arm,armv7-timer-mem";
1380 reg = <0x0 0x17420000 0x0 0x1000>;
1381 #address-cells = <1>;
1382 #size-cells = <1>;
1383 ranges = <0 0 0 0x20000000>;
1384
1385 frame@17421000 {
1386 reg = <0x17421000 0x1000>,
1387 <0x17422000 0x1000>;
1388 frame-number = <0>;
1389 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1391 };
1392
1393 frame@17423000 {
1394 reg = <0x17423000 0x1000>;
1395 frame-number = <1>;
1396 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1397 status = "disabled";
1398 };
1399
1400 frame@17425000 {
1401 reg = <0x17425000 0x1000>;
1402 frame-number = <2>;
1403 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1404 status = "disabled";
1405 };
1406
1407 frame@17427000 {
1408 reg = <0x17427000 0x1000>;
1409 frame-number = <3>;
1410 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1411 status = "disabled";
1412 };
1413
1414 frame@17429000 {
1415 reg = <0x17429000 0x1000>;
1416 frame-number = <4>;
1417 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1418 status = "disabled";
1419 };
1420
1421 frame@1742b000 {
1422 reg = <0x1742b000 0x1000>;
1423 frame-number = <5>;
1424 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1425 status = "disabled";
1426 };
1427
1428 frame@1742d000 {
1429 reg = <0x1742d000 0x1000>;
1430 frame-number = <6>;
1431 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1432 status = "disabled";
1433 };
1434 };
1435
1436 apps_rsc: rsc@17a00000 {
1437 label = "apps_rsc";
1438 compatible = "qcom,rpmh-rsc";
1439 reg = <0x0 0x17a00000 0x0 0x10000>,
1440 <0x0 0x17a10000 0x0 0x10000>,
1441 <0x0 0x17a20000 0x0 0x10000>;
1442 reg-names = "drv-0", "drv-1", "drv-2";
1443 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1446
1447 power-domains = <&CLUSTER_PD>;
1448 qcom,tcs-offset = <0xd00>;
1449 qcom,drv-id = <2>;
1450 qcom,tcs-config = <ACTIVE_TCS 3>,
1451 <SLEEP_TCS 2>,
1452 <WAKE_TCS 2>,
1453 <CONTROL_TCS 0>;
1454
1455 apps_bcm_voter: bcm-voter {
1456 compatible = "qcom,bcm-voter";
1457 };
1458
1459 rpmhcc: clock-controller {
1460 compatible = "qcom,sdx75-rpmh-clk";
1461 clocks = <&xo_board>;
1462 clock-names = "xo";
1463 #clock-cells = <1>;
1464 };
1465
1466 rpmhpd: power-controller {
1467 compatible = "qcom,sdx75-rpmhpd";
1468 #power-domain-cells = <1>;
1469 operating-points-v2 = <&rpmhpd_opp_table>;
1470
1471 rpmhpd_opp_table: opp-table {
1472 compatible = "operating-points-v2";
1473
1474 rpmhpd_opp_ret: opp-16 {
1475 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1476 };
1477
1478 rpmhpd_opp_min_svs: opp-48 {
1479 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1480 };
1481
1482 rpmhpd_opp_low_svs: opp-64 {
1483 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1484 };
1485
1486 rpmhpd_opp_svs: opp-128 {
1487 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1488 };
1489
1490 rpmhpd_opp_svs_l1: opp-192 {
1491 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1492 };
1493
1494 rpmhpd_opp_nom: opp-256 {
1495 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1496 };
1497
1498 rpmhpd_opp_nom_l1: opp-320 {
1499 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1500 };
1501
1502 rpmhpd_opp_nom_l2: opp-336 {
1503 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1504 };
1505
1506 rpmhpd_opp_turbo: opp-384 {
1507 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1508 };
1509
1510 rpmhpd_opp_turbo_l1: opp-416 {
1511 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1512 };
1513 };
1514 };
1515 };
1516
1517 cpufreq_hw: cpufreq@17d91000 {
1518 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1519 reg = <0x0 0x17d91000 0x0 0x1000>;
1520 reg-names = "freq-domain0";
1521 clocks = <&rpmhcc RPMH_CXO_CLK>,
1522 <&gcc GPLL0>;
1523 clock-names = "xo",
1524 "alternate";
1525 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1526 interrupt-names = "dcvsh-irq-0";
1527 #freq-domain-cells = <1>;
1528 #clock-cells = <1>;
1529 };
1530
1531 dc_noc: interconnect@190e0000 {
1532 compatible = "qcom,sdx75-dc-noc";
1533 reg = <0x0 0x190e0000 0x0 0x8200>;
1534 #interconnect-cells = <2>;
1535 qcom,bcm-voters = <&apps_bcm_voter>;
1536 };
1537
1538 gem_noc: interconnect@19100000 {
1539 compatible = "qcom,sdx75-gem-noc";
1540 reg = <0x0 0x19100000 0x0 0x34080>;
1541 #interconnect-cells = <2>;
1542 qcom,bcm-voters = <&apps_bcm_voter>;
1543 };
1544 };
1545
1546 timer {
1547 compatible = "arm,armv8-timer";
1548 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1549 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1550 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1551 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1552 };
1553 };
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