1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
4 */
5
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15
16 / {
17 interrupt-parent = <&intc>;
18
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 chosen { };
23
24 clocks {
25 xo_board_clk: xo-board-clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 };
29
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
33 #clock-cells = <0>;
34 };
35 };
36
37 cpus {
38 #address-cells = <2>;
39 #size-cells = <0>;
40
41 CPU0: cpu@0 {
42 device_type = "cpu";
43 compatible = "qcom,kryo660";
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
49 operating-points-v2 = <&cpu0_opp_table>;
50 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
51 power-domains = <&CPU_PD0>;
52 power-domain-names = "psci";
53 #cooling-cells = <2>;
54 L2_0: l2-cache {
55 compatible = "cache";
56 cache-level = <2>;
57 cache-unified;
58 next-level-cache = <&L3_0>;
59 L3_0: l3-cache {
60 compatible = "cache";
61 cache-level = <3>;
62 cache-unified;
63 };
64 };
65 };
66
67 CPU1: cpu@100 {
68 device_type = "cpu";
69 compatible = "qcom,kryo660";
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
72 enable-method = "psci";
73 next-level-cache = <&L2_100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
75 operating-points-v2 = <&cpu0_opp_table>;
76 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
77 power-domains = <&CPU_PD1>;
78 power-domain-names = "psci";
79 #cooling-cells = <2>;
80 L2_100: l2-cache {
81 compatible = "cache";
82 cache-level = <2>;
83 cache-unified;
84 next-level-cache = <&L3_0>;
85 };
86 };
87
88 CPU2: cpu@200 {
89 device_type = "cpu";
90 compatible = "qcom,kryo660";
91 reg = <0x0 0x200>;
92 clocks = <&cpufreq_hw 0>;
93 enable-method = "psci";
94 next-level-cache = <&L2_200>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
96 operating-points-v2 = <&cpu0_opp_table>;
97 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
98 power-domains = <&CPU_PD2>;
99 power-domain-names = "psci";
100 #cooling-cells = <2>;
101 L2_200: l2-cache {
102 compatible = "cache";
103 cache-level = <2>;
104 cache-unified;
105 next-level-cache = <&L3_0>;
106 };
107 };
108
109 CPU3: cpu@300 {
110 device_type = "cpu";
111 compatible = "qcom,kryo660";
112 reg = <0x0 0x300>;
113 clocks = <&cpufreq_hw 0>;
114 enable-method = "psci";
115 next-level-cache = <&L2_300>;
116 qcom,freq-domain = <&cpufreq_hw 0>;
117 operating-points-v2 = <&cpu0_opp_table>;
118 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
119 power-domains = <&CPU_PD3>;
120 power-domain-names = "psci";
121 #cooling-cells = <2>;
122 L2_300: l2-cache {
123 compatible = "cache";
124 cache-level = <2>;
125 cache-unified;
126 next-level-cache = <&L3_0>;
127 };
128 };
129
130 CPU4: cpu@400 {
131 device_type = "cpu";
132 compatible = "qcom,kryo660";
133 reg = <0x0 0x400>;
134 clocks = <&cpufreq_hw 0>;
135 enable-method = "psci";
136 next-level-cache = <&L2_400>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
140 power-domains = <&CPU_PD4>;
141 power-domain-names = "psci";
142 #cooling-cells = <2>;
143 L2_400: l2-cache {
144 compatible = "cache";
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
148 };
149 };
150
151 CPU5: cpu@500 {
152 device_type = "cpu";
153 compatible = "qcom,kryo660";
154 reg = <0x0 0x500>;
155 clocks = <&cpufreq_hw 0>;
156 enable-method = "psci";
157 next-level-cache = <&L2_500>;
158 qcom,freq-domain = <&cpufreq_hw 0>;
159 operating-points-v2 = <&cpu0_opp_table>;
160 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
161 power-domains = <&CPU_PD5>;
162 power-domain-names = "psci";
163 #cooling-cells = <2>;
164 L2_500: l2-cache {
165 compatible = "cache";
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
169 };
170 };
171
172 CPU6: cpu@600 {
173 device_type = "cpu";
174 compatible = "qcom,kryo660";
175 reg = <0x0 0x600>;
176 clocks = <&cpufreq_hw 1>;
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 operating-points-v2 = <&cpu6_opp_table>;
181 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
182 power-domains = <&CPU_PD6>;
183 power-domain-names = "psci";
184 #cooling-cells = <2>;
185 L2_600: l2-cache {
186 compatible = "cache";
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&L3_0>;
190 };
191 };
192
193 CPU7: cpu@700 {
194 device_type = "cpu";
195 compatible = "qcom,kryo660";
196 reg = <0x0 0x700>;
197 clocks = <&cpufreq_hw 1>;
198 enable-method = "psci";
199 next-level-cache = <&L2_700>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu6_opp_table>;
202 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
203 power-domains = <&CPU_PD7>;
204 power-domain-names = "psci";
205 #cooling-cells = <2>;
206 L2_700: l2-cache {
207 compatible = "cache";
208 cache-level = <2>;
209 cache-unified;
210 next-level-cache = <&L3_0>;
211 };
212 };
213
214 cpu-map {
215 cluster0 {
216 core0 {
217 cpu = <&CPU0>;
218 };
219
220 core1 {
221 cpu = <&CPU1>;
222 };
223
224 core2 {
225 cpu = <&CPU2>;
226 };
227
228 core3 {
229 cpu = <&CPU3>;
230 };
231
232 core4 {
233 cpu = <&CPU4>;
234 };
235
236 core5 {
237 cpu = <&CPU5>;
238 };
239
240 core6 {
241 cpu = <&CPU6>;
242 };
243
244 core7 {
245 cpu = <&CPU7>;
246 };
247 };
248 };
249
250 idle-states {
251 entry-method = "psci";
252
253 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
254 compatible = "arm,idle-state";
255 idle-state-name = "silver-power-collapse";
256 arm,psci-suspend-param = <0x40000003>;
257 entry-latency-us = <549>;
258 exit-latency-us = <901>;
259 min-residency-us = <1774>;
260 local-timer-stop;
261 };
262
263 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
264 compatible = "arm,idle-state";
265 idle-state-name = "silver-rail-power-collapse";
266 arm,psci-suspend-param = <0x40000004>;
267 entry-latency-us = <702>;
268 exit-latency-us = <915>;
269 min-residency-us = <4001>;
270 local-timer-stop;
271 };
272
273 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
274 compatible = "arm,idle-state";
275 idle-state-name = "gold-power-collapse";
276 arm,psci-suspend-param = <0x40000003>;
277 entry-latency-us = <523>;
278 exit-latency-us = <1244>;
279 min-residency-us = <2207>;
280 local-timer-stop;
281 };
282
283 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
284 compatible = "arm,idle-state";
285 idle-state-name = "gold-rail-power-collapse";
286 arm,psci-suspend-param = <0x40000004>;
287 entry-latency-us = <526>;
288 exit-latency-us = <1854>;
289 min-residency-us = <5555>;
290 local-timer-stop;
291 };
292 };
293
294 domain-idle-states {
295 CLUSTER_SLEEP_0: cluster-sleep-0 {
296 compatible = "domain-idle-state";
297 arm,psci-suspend-param = <0x41000044>;
298 entry-latency-us = <2752>;
299 exit-latency-us = <3048>;
300 min-residency-us = <6118>;
301 };
302 };
303 };
304
305 firmware {
306 scm {
307 compatible = "qcom,scm-sm6375", "qcom,scm";
308 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
309 clock-names = "core";
310 #reset-cells = <1>;
311 };
312 };
313
314 mpm: interrupt-controller {
315 compatible = "qcom,mpm";
316 qcom,rpm-msg-ram = <&apss_mpm>;
317 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
318 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 #power-domain-cells = <0>;
322 interrupt-parent = <&intc>;
323 qcom,mpm-pin-count = <96>;
324 qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */
325 <12 422>, /* DWC3 ss_phy_irq */
326 <86 183>, /* MPM wake, SPMI */
327 <89 314>, /* TSENS0 0C */
328 <90 315>, /* TSENS1 0C */
329 <93 164>, /* DWC3 dm_hs_phy_irq */
330 <94 165>; /* DWC3 dp_hs_phy_irq */
331 };
332
333 memory@80000000 {
334 device_type = "memory";
335 /* We expect the bootloader to fill in the size */
336 reg = <0x0 0x80000000 0x0 0x0>;
337 };
338
339 cpu0_opp_table: opp-table-cpu0 {
340 compatible = "operating-points-v2";
341 opp-shared;
342
343 opp-300000000 {
344 opp-hz = /bits/ 64 <300000000>;
345 opp-peak-kBps = <(300000 * 32)>;
346 };
347
348 opp-576000000 {
349 opp-hz = /bits/ 64 <576000000>;
350 opp-peak-kBps = <(556800 * 32)>;
351 };
352
353 opp-691200000 {
354 opp-hz = /bits/ 64 <691200000>;
355 opp-peak-kBps = <(652800 * 32)>;
356 };
357
358 opp-940800000 {
359 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <(921600 * 32)>;
361 };
362
363 opp-1113600000 {
364 opp-hz = /bits/ 64 <1113600000>;
365 opp-peak-kBps = <(921600 * 32)>;
366 };
367
368 opp-1324800000 {
369 opp-hz = /bits/ 64 <1324800000>;
370 opp-peak-kBps = <(1171200 * 32)>;
371 };
372
373 opp-1516800000 {
374 opp-hz = /bits/ 64 <1516800000>;
375 opp-peak-kBps = <(1497600 * 32)>;
376 };
377
378 opp-1651200000 {
379 opp-hz = /bits/ 64 <1651200000>;
380 opp-peak-kBps = <(1497600 * 32)>;
381 };
382
383 opp-1708800000 {
384 opp-hz = /bits/ 64 <1708800000>;
385 opp-peak-kBps = <(1497600 * 32)>;
386 };
387
388 opp-1804800000 {
389 opp-hz = /bits/ 64 <1804800000>;
390 opp-peak-kBps = <(1497600 * 32)>;
391 };
392 };
393
394 cpu6_opp_table: opp-table-cpu6 {
395 compatible = "operating-points-v2";
396 opp-shared;
397
398 opp-691200000 {
399 opp-hz = /bits/ 64 <691200000>;
400 opp-peak-kBps = <(556800 * 32)>;
401 };
402
403 opp-940800000 {
404 opp-hz = /bits/ 64 <940800000>;
405 opp-peak-kBps = <(921600 * 32)>;
406 };
407
408 opp-1228800000 {
409 opp-hz = /bits/ 64 <1228800000>;
410 opp-peak-kBps = <(1171200 * 32)>;
411 };
412
413 opp-1401600000 {
414 opp-hz = /bits/ 64 <1401600000>;
415 opp-peak-kBps = <(1382400 * 32)>;
416 };
417
418 opp-1516800000 {
419 opp-hz = /bits/ 64 <1516800000>;
420 opp-peak-kBps = <(1497600 * 32)>;
421 };
422
423 opp-1651200000 {
424 opp-hz = /bits/ 64 <1651200000>;
425 opp-peak-kBps = <(1497600 * 32)>;
426 };
427
428 opp-1804800000 {
429 opp-hz = /bits/ 64 <1804800000>;
430 opp-peak-kBps = <(1497600 * 32)>;
431 };
432
433 opp-1900800000 {
434 opp-hz = /bits/ 64 <1900800000>;
435 opp-peak-kBps = <(1497600 * 32)>;
436 };
437
438 opp-2054400000 {
439 opp-hz = /bits/ 64 <2054400000>;
440 opp-peak-kBps = <(1497600 * 32)>;
441 };
442
443 opp-2208000000 {
444 opp-hz = /bits/ 64 <2208000000>;
445 opp-peak-kBps = <(1497600 * 32)>;
446 };
447 };
448
449 pmu {
450 compatible = "arm,armv8-pmuv3";
451 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
452 };
453
454 psci {
455 compatible = "arm,psci-1.0";
456 method = "smc";
457
458 CPU_PD0: power-domain-cpu0 {
459 #power-domain-cells = <0>;
460 power-domains = <&CLUSTER_PD>;
461 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
462 };
463
464 CPU_PD1: power-domain-cpu1 {
465 #power-domain-cells = <0>;
466 power-domains = <&CLUSTER_PD>;
467 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
468 };
469
470 CPU_PD2: power-domain-cpu2 {
471 #power-domain-cells = <0>;
472 power-domains = <&CLUSTER_PD>;
473 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
474 };
475
476 CPU_PD3: power-domain-cpu3 {
477 #power-domain-cells = <0>;
478 power-domains = <&CLUSTER_PD>;
479 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
480 };
481
482 CPU_PD4: power-domain-cpu4 {
483 #power-domain-cells = <0>;
484 power-domains = <&CLUSTER_PD>;
485 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
486 };
487
488 CPU_PD5: power-domain-cpu5 {
489 #power-domain-cells = <0>;
490 power-domains = <&CLUSTER_PD>;
491 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
492 };
493
494 CPU_PD6: power-domain-cpu6 {
495 #power-domain-cells = <0>;
496 power-domains = <&CLUSTER_PD>;
497 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
498 };
499
500 CPU_PD7: power-domain-cpu7 {
501 #power-domain-cells = <0>;
502 power-domains = <&CLUSTER_PD>;
503 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
504 };
505
506 CLUSTER_PD: power-domain-cpu-cluster0 {
507 #power-domain-cells = <0>;
508 power-domains = <&mpm>;
509 domain-idle-states = <&CLUSTER_SLEEP_0>;
510 };
511 };
512
513 qup_opp_table: opp-table-qup {
514 compatible = "operating-points-v2";
515
516 opp-75000000 {
517 opp-hz = /bits/ 64 <75000000>;
518 required-opps = <&rpmpd_opp_low_svs>;
519 };
520
521 opp-100000000 {
522 opp-hz = /bits/ 64 <100000000>;
523 required-opps = <&rpmpd_opp_svs>;
524 };
525
526 opp-128000000 {
527 opp-hz = /bits/ 64 <128000000>;
528 required-opps = <&rpmpd_opp_nom>;
529 };
530 };
531
532 reserved_memory: reserved-memory {
533 #address-cells = <2>;
534 #size-cells = <2>;
535 ranges;
536
537 hyp_mem: hypervisor@80000000 {
538 reg = <0 0x80000000 0 0x600000>;
539 no-map;
540 };
541
542 xbl_aop_mem: xbl-aop@80700000 {
543 reg = <0 0x80700000 0 0x100000>;
544 no-map;
545 };
546
547 reserved_xbl_uefi: xbl-uefi-res@80880000 {
548 reg = <0 0x80880000 0 0x14000>;
549 no-map;
550 };
551
552 smem_mem: smem@80900000 {
553 compatible = "qcom,smem";
554 reg = <0 0x80900000 0 0x200000>;
555 hwlocks = <&tcsr_mutex 3>;
556 no-map;
557 };
558
559 fw_mem: fw@80b00000 {
560 reg = <0 0x80b00000 0 0x100000>;
561 no-map;
562 };
563
564 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 {
565 reg = <0 0x80c00000 0 0x1e00000>;
566 no-map;
567 };
568
569 dfps_data_mem: dpfs-data@85e00000 {
570 reg = <0 0x85e00000 0 0x100000>;
571 no-map;
572 };
573
574 pil_wlan_mem: pil-wlan@86500000 {
575 reg = <0 0x86500000 0 0x200000>;
576 no-map;
577 };
578
579 pil_adsp_mem: pil-adsp@86700000 {
580 reg = <0 0x86700000 0 0x2000000>;
581 no-map;
582 };
583
584 pil_cdsp_mem: pil-cdsp@88700000 {
585 reg = <0 0x88700000 0 0x1e00000>;
586 no-map;
587 };
588
589 pil_video_mem: pil-video@8a500000 {
590 reg = <0 0x8a500000 0 0x500000>;
591 no-map;
592 };
593
594 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 {
595 reg = <0 0x8aa00000 0 0x10000>;
596 no-map;
597 };
598
599 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 {
600 reg = <0 0x8aa10000 0 0xa000>;
601 no-map;
602 };
603
604 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 {
605 reg = <0 0x8aa1a000 0 0x2000>;
606 no-map;
607 };
608
609 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 {
610 reg = <0 0x8b800000 0 0x10000000>;
611 no-map;
612 };
613
614 removed_mem: removed@c0000000 {
615 reg = <0 0xc0000000 0 0x5100000>;
616 no-map;
617 };
618
619 rmtfs_mem: rmtfs@f3900000 {
620 compatible = "qcom,rmtfs-mem";
621 reg = <0 0xf3900000 0 0x280000>;
622 no-map;
623
624 qcom,client-id = <1>;
625 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
626 };
627
628 debug_mem: debug@ffb00000 {
629 reg = <0 0xffb00000 0 0xc0000>;
630 no-map;
631 };
632
633 last_log_mem: lastlog@ffbc0000 {
634 reg = <0 0xffbc0000 0 0x80000>;
635 no-map;
636 };
637
638 cmdline_region: cmdline@ffd00000 {
639 reg = <0 0xffd00000 0 0x1000>;
640 no-map;
641 };
642 };
643
644 rpm: remoteproc {
645 compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc";
646
647 glink-edge {
648 compatible = "qcom,glink-rpm";
649 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
650 IPCC_MPROC_SIGNAL_GLINK_QMP
651 IRQ_TYPE_EDGE_RISING>;
652 qcom,rpm-msg-ram = <&rpm_msg_ram>;
653 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
654
655 rpm_requests: rpm-requests {
656 compatible = "qcom,rpm-sm6375", "qcom,glink-smd-rpm";
657 qcom,glink-channels = "rpm_requests";
658
659 rpmcc: clock-controller {
660 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
661 clocks = <&xo_board_clk>;
662 clock-names = "xo";
663 #clock-cells = <1>;
664 };
665
666 rpmpd: power-controller {
667 compatible = "qcom,sm6375-rpmpd";
668 #power-domain-cells = <1>;
669 operating-points-v2 = <&rpmpd_opp_table>;
670
671 rpmpd_opp_table: opp-table {
672 compatible = "operating-points-v2";
673
674 rpmpd_opp_ret: opp1 {
675 opp-level = <RPM_SMD_LEVEL_RETENTION>;
676 };
677
678 rpmpd_opp_min_svs: opp2 {
679 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
680 };
681
682 rpmpd_opp_low_svs: opp3 {
683 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
684 };
685
686 rpmpd_opp_svs: opp4 {
687 opp-level = <RPM_SMD_LEVEL_SVS>;
688 };
689
690 rpmpd_opp_svs_plus: opp5 {
691 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
692 };
693
694 rpmpd_opp_nom: opp6 {
695 opp-level = <RPM_SMD_LEVEL_NOM>;
696 };
697
698 rpmpd_opp_nom_plus: opp7 {
699 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
700 };
701
702 rpmpd_opp_turbo: opp8 {
703 opp-level = <RPM_SMD_LEVEL_TURBO>;
704 };
705
706 rpmpd_opp_turbo_no_cpr: opp9 {
707 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
708 };
709 };
710 };
711 };
712 };
713 };
714
715 smp2p-adsp {
716 compatible = "qcom,smp2p";
717 qcom,smem = <443>, <429>;
718 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
719 IPCC_MPROC_SIGNAL_SMP2P
720 IRQ_TYPE_EDGE_RISING>;
721 mboxes = <&ipcc IPCC_CLIENT_LPASS
722 IPCC_MPROC_SIGNAL_SMP2P>;
723
724 qcom,local-pid = <0>;
725 qcom,remote-pid = <2>;
726
727 smp2p_adsp_out: master-kernel {
728 qcom,entry-name = "master-kernel";
729 #qcom,smem-state-cells = <1>;
730 };
731
732 smp2p_adsp_in: slave-kernel {
733 qcom,entry-name = "slave-kernel";
734 interrupt-controller;
735 #interrupt-cells = <2>;
736 };
737 };
738
739 smp2p-cdsp {
740 compatible = "qcom,smp2p";
741 qcom,smem = <94>, <432>;
742 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
743 IPCC_MPROC_SIGNAL_SMP2P
744 IRQ_TYPE_EDGE_RISING>;
745 mboxes = <&ipcc IPCC_CLIENT_CDSP
746 IPCC_MPROC_SIGNAL_SMP2P>;
747
748 qcom,local-pid = <0>;
749 qcom,remote-pid = <5>;
750
751 smp2p_cdsp_out: master-kernel {
752 qcom,entry-name = "master-kernel";
753 #qcom,smem-state-cells = <1>;
754 };
755
756 smp2p_cdsp_in: slave-kernel {
757 qcom,entry-name = "slave-kernel";
758 interrupt-controller;
759 #interrupt-cells = <2>;
760 };
761 };
762
763 smp2p-modem {
764 compatible = "qcom,smp2p";
765 qcom,smem = <435>, <428>;
766 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
767 IPCC_MPROC_SIGNAL_SMP2P
768 IRQ_TYPE_EDGE_RISING>;
769 mboxes = <&ipcc IPCC_CLIENT_MPSS
770 IPCC_MPROC_SIGNAL_SMP2P>;
771
772 qcom,local-pid = <0>;
773 qcom,remote-pid = <1>;
774
775 smp2p_modem_out: master-kernel {
776 qcom,entry-name = "master-kernel";
777 #qcom,smem-state-cells = <1>;
778 };
779
780 smp2p_modem_in: slave-kernel {
781 qcom,entry-name = "slave-kernel";
782 interrupt-controller;
783 #interrupt-cells = <2>;
784 };
785
786 ipa_smp2p_out: ipa-ap-to-modem {
787 qcom,entry-name = "ipa";
788 #qcom,smem-state-cells = <1>;
789 };
790
791 ipa_smp2p_in: ipa-modem-to-ap {
792 qcom,entry-name = "ipa";
793 interrupt-controller;
794 #interrupt-cells = <2>;
795 };
796
797 wlan_smp2p_in: wlan-wpss-to-ap {
798 qcom,entry-name = "wlan";
799 interrupt-controller;
800 #interrupt-cells = <2>;
801 };
802 };
803
804 soc: soc@0 {
805 #address-cells = <2>;
806 #size-cells = <2>;
807 ranges = <0 0 0 0 0x10 0>;
808 dma-ranges = <0 0 0 0 0x10 0>;
809 compatible = "simple-bus";
810
811 ipcc: mailbox@208000 {
812 compatible = "qcom,sm6375-ipcc", "qcom,ipcc";
813 reg = <0 0x00208000 0 0x1000>;
814 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
815 interrupt-controller;
816 #interrupt-cells = <3>;
817 #mbox-cells = <2>;
818 };
819
820 tcsr_mutex: hwlock@340000 {
821 compatible = "qcom,tcsr-mutex";
822 reg = <0x0 0x00340000 0x0 0x40000>;
823 #hwlock-cells = <1>;
824 };
825
826 tlmm: pinctrl@500000 {
827 compatible = "qcom,sm6375-tlmm";
828 reg = <0 0x00500000 0 0x800000>;
829 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
830 gpio-ranges = <&tlmm 0 0 157>;
831 wakeup-parent = <&mpm>;
832 interrupt-controller;
833 gpio-controller;
834 #interrupt-cells = <2>;
835 #gpio-cells = <2>;
836
837 sdc2_off_state: sdc2-off-state {
838 clk-pins {
839 pins = "sdc2_clk";
840 drive-strength = <2>;
841 bias-disable;
842 };
843
844 cmd-pins {
845 pins = "sdc2_cmd";
846 drive-strength = <2>;
847 bias-pull-up;
848 };
849
850 data-pins {
851 pins = "sdc2_data";
852 drive-strength = <2>;
853 bias-pull-up;
854 };
855 };
856
857 sdc2_on_state: sdc2-on-state {
858 clk-pins {
859 pins = "sdc2_clk";
860 drive-strength = <16>;
861 bias-disable;
862 };
863
864 cmd-pins {
865 pins = "sdc2_cmd";
866 drive-strength = <10>;
867 bias-pull-up;
868 };
869
870 data-pins {
871 pins = "sdc2_data";
872 drive-strength = <10>;
873 bias-pull-up;
874 };
875 };
876
877 qup_i2c0_default: qup-i2c0-default-state {
878 pins = "gpio0", "gpio1";
879 function = "qup00";
880 drive-strength = <2>;
881 bias-pull-up;
882 };
883
884 qup_i2c1_default: qup-i2c1-default-state {
885 pins = "gpio61", "gpio62";
886 function = "qup01";
887 drive-strength = <2>;
888 bias-pull-up;
889 };
890
891 qup_i2c2_default: qup-i2c2-default-state {
892 pins = "gpio45", "gpio46";
893 function = "qup02";
894 drive-strength = <2>;
895 bias-pull-up;
896 };
897
898 qup_i2c8_default: qup-i2c8-default-state {
899 pins = "gpio19", "gpio20";
900 /* TLMM, GCC and vendor DT all have different indices.. */
901 function = "qup12";
902 drive-strength = <2>;
903 bias-pull-up;
904 };
905
906 qup_i2c10_default: qup-i2c10-default-state {
907 pins = "gpio4", "gpio5";
908 function = "qup10";
909 drive-strength = <2>;
910 bias-pull-up;
911 };
912
913 qup_spi0_default: qup-spi0-default-state {
914 pins = "gpio0", "gpio1", "gpio2", "gpio3";
915 function = "qup00";
916 drive-strength = <6>;
917 bias-disable;
918 };
919
920 qup_uart1_default: qup-uart1-default-state {
921 cts-pins {
922 pins = "gpio61";
923 function = "qup01";
924 drive-strength = <2>;
925 bias-pull-down;
926 };
927
928 rts-pins {
929 pins = "gpio62";
930 function = "qup01";
931 drive-strength = <2>;
932 bias-disable;
933 };
934
935 tx-pins {
936 pins = "gpio63";
937 function = "qup01";
938 drive-strength = <2>;
939 bias-disable;
940 };
941
942 rx-pins {
943 pins = "gpio64";
944 function = "qup01";
945 drive-strength = <2>;
946 bias-pull-up;
947 };
948 };
949 };
950
951 gcc: clock-controller@1400000 {
952 compatible = "qcom,sm6375-gcc";
953 reg = <0 0x01400000 0 0x1f0000>;
954 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
955 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
956 <&sleep_clk>;
957 #power-domain-cells = <1>;
958 #clock-cells = <1>;
959 #reset-cells = <1>;
960 };
961
962 usb_1_hsphy: phy@162b000 {
963 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
964 reg = <0 0x0162b000 0 0x400>;
965
966 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
967 clock-names = "ref";
968 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
969 #phy-cells = <0>;
970
971 status = "disabled";
972 };
973
974 spmi_bus: spmi@1c40000 {
975 compatible = "qcom,spmi-pmic-arb";
976 reg = <0 0x01c40000 0 0x1100>,
977 <0 0x01e00000 0 0x2000000>,
978 <0 0x03e00000 0 0x100000>,
979 <0 0x03f00000 0 0xa0000>,
980 <0 0x01c0a000 0 0x26000>;
981 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
982 interrupt-names = "periph_irq";
983 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
984 qcom,ee = <0>;
985 qcom,channel = <0>;
986 #address-cells = <2>;
987 #size-cells = <0>;
988 interrupt-controller;
989 #interrupt-cells = <4>;
990 };
991
992 tsens0: thermal-sensor@4411000 {
993 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
994 reg = <0 0x04411000 0 0x140>, /* TM */
995 <0 0x04410000 0 0x20>; /* SROT */
996 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
998 interrupt-names = "uplow", "critical";
999 #thermal-sensor-cells = <1>;
1000 #qcom,sensors = <15>;
1001 };
1002
1003 tsens1: thermal-sensor@4413000 {
1004 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
1005 reg = <0 0x04413000 0 0x140>, /* TM */
1006 <0 0x04412000 0 0x20>; /* SROT */
1007 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
1009 interrupt-names = "uplow", "critical";
1010 #thermal-sensor-cells = <1>;
1011 #qcom,sensors = <11>;
1012 };
1013
1014 rpm_msg_ram: sram@45f0000 {
1015 compatible = "qcom,rpm-msg-ram", "mmio-sram";
1016 reg = <0 0x045f0000 0 0x7000>;
1017 #address-cells = <1>;
1018 #size-cells = <1>;
1019 ranges = <0 0x0 0x045f0000 0x7000>;
1020
1021 apss_mpm: sram@1b8 {
1022 reg = <0x1b8 0x48>;
1023 };
1024 };
1025
1026 sram@4690000 {
1027 compatible = "qcom,rpm-stats";
1028 reg = <0 0x04690000 0 0x400>;
1029 };
1030
1031 sdhc_2: mmc@4784000 {
1032 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5";
1033 reg = <0 0x04784000 0 0x1000>;
1034
1035 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1037 interrupt-names = "hc_irq", "pwr_irq";
1038
1039 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1040 <&gcc GCC_SDCC2_APPS_CLK>,
1041 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1042 clock-names = "iface", "core", "xo";
1043 resets = <&gcc GCC_SDCC2_BCR>;
1044 iommus = <&apps_smmu 0x40 0x0>;
1045
1046 pinctrl-0 = <&sdc2_on_state>;
1047 pinctrl-1 = <&sdc2_off_state>;
1048 pinctrl-names = "default", "sleep";
1049
1050 qcom,dll-config = <0x0007642c>;
1051 qcom,ddr-config = <0x80040868>;
1052 power-domains = <&rpmpd SM6375_VDDCX>;
1053 operating-points-v2 = <&sdhc2_opp_table>;
1054 bus-width = <4>;
1055
1056 status = "disabled";
1057
1058 sdhc2_opp_table: opp-table {
1059 compatible = "operating-points-v2";
1060
1061 opp-100000000 {
1062 opp-hz = /bits/ 64 <100000000>;
1063 required-opps = <&rpmpd_opp_low_svs>;
1064 };
1065
1066 opp-202000000 {
1067 opp-hz = /bits/ 64 <202000000>;
1068 required-opps = <&rpmpd_opp_svs_plus>;
1069 };
1070 };
1071 };
1072
1073 gpi_dma0: dma-controller@4a00000 {
1074 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
1075 reg = <0 0x04a00000 0 0x60000>;
1076 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1077 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1078 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1079 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1081 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1082 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1083 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1084 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1085 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1086 dma-channels = <10>;
1087 dma-channel-mask = <0x1f>;
1088 iommus = <&apps_smmu 0x16 0x0>;
1089 #dma-cells = <3>;
1090 status = "disabled";
1091 };
1092
1093 qupv3_id_0: geniqup@4ac0000 {
1094 compatible = "qcom,geni-se-qup";
1095 reg = <0x0 0x04ac0000 0x0 0x2000>;
1096 clock-names = "m-ahb", "s-ahb";
1097 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1098 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1099 iommus = <&apps_smmu 0x3 0x0>;
1100 #address-cells = <2>;
1101 #size-cells = <2>;
1102 ranges;
1103 status = "disabled";
1104
1105 i2c0: i2c@4a80000 {
1106 compatible = "qcom,geni-i2c";
1107 reg = <0x0 0x04a80000 0x0 0x4000>;
1108 clock-names = "se";
1109 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1110 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1111 pinctrl-names = "default";
1112 pinctrl-0 = <&qup_i2c0_default>;
1113 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1114 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1115 dma-names = "tx", "rx";
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 status = "disabled";
1119 };
1120
1121 spi0: spi@4a80000 {
1122 compatible = "qcom,geni-spi";
1123 reg = <0x0 0x04a80000 0x0 0x4000>;
1124 clock-names = "se";
1125 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1126 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&qup_spi0_default>;
1129 power-domains = <&rpmpd SM6375_VDDCX>;
1130 operating-points-v2 = <&qup_opp_table>;
1131 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1132 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1133 dma-names = "tx", "rx";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 status = "disabled";
1137 };
1138
1139 i2c1: i2c@4a84000 {
1140 compatible = "qcom,geni-i2c";
1141 reg = <0x0 0x04a84000 0x0 0x4000>;
1142 clock-names = "se";
1143 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1144 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&qup_i2c1_default>;
1147 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1148 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1149 dma-names = "tx", "rx";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152 status = "disabled";
1153 };
1154
1155 spi1: spi@4a84000 {
1156 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x04a84000 0x0 0x4000>;
1158 clock-names = "se";
1159 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1160 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1161 power-domains = <&rpmpd SM6375_VDDCX>;
1162 operating-points-v2 = <&qup_opp_table>;
1163 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1164 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1165 dma-names = "tx", "rx";
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 status = "disabled";
1169 };
1170
1171 uart1: serial@4a84000 {
1172 compatible = "qcom,geni-uart";
1173 reg = <0x0 0x04a84000 0x0 0x4000>;
1174 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1175 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1176 clock-names = "se";
1177 power-domains = <&rpmpd SM6375_VDDCX>;
1178 operating-points-v2 = <&qup_opp_table>;
1179 pinctrl-0 = <&qup_uart1_default>;
1180 pinctrl-names = "default";
1181 status = "disabled";
1182 };
1183
1184 i2c2: i2c@4a88000 {
1185 compatible = "qcom,geni-i2c";
1186 reg = <0x0 0x04a88000 0x0 0x4000>;
1187 clock-names = "se";
1188 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1189 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1190 pinctrl-names = "default";
1191 pinctrl-0 = <&qup_i2c2_default>;
1192 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1193 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1194 dma-names = "tx", "rx";
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1197 status = "disabled";
1198 };
1199
1200 spi2: spi@4a88000 {
1201 compatible = "qcom,geni-spi";
1202 reg = <0x0 0x04a88000 0x0 0x4000>;
1203 clock-names = "se";
1204 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1205 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1206 power-domains = <&rpmpd SM6375_VDDCX>;
1207 operating-points-v2 = <&qup_opp_table>;
1208 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1209 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1210 dma-names = "tx", "rx";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 status = "disabled";
1214 };
1215
1216 /*
1217 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream.
1218 * There is a comment in the included DTSI of another SoC saying that they
1219 * are not "bolled out" (probably meaning not routed to solder balls)
1220 * TLMM driver however, suggests there are as many as 15 QUPs in total!
1221 * Most of which don't even have pin configurations for.. Sad stuff!
1222 */
1223 };
1224
1225 gpi_dma1: dma-controller@4c00000 {
1226 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
1227 reg = <0 0x04c00000 0 0x60000>;
1228 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
1238 dma-channels = <10>;
1239 dma-channel-mask = <0x1f>;
1240 iommus = <&apps_smmu 0xd6 0x0>;
1241 #dma-cells = <3>;
1242 status = "disabled";
1243 };
1244
1245 qupv3_id_1: geniqup@4cc0000 {
1246 compatible = "qcom,geni-se-qup";
1247 reg = <0x0 0x04cc0000 0x0 0x2000>;
1248 clock-names = "m-ahb", "s-ahb";
1249 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1250 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1251 iommus = <&apps_smmu 0xc3 0x0>;
1252 #address-cells = <2>;
1253 #size-cells = <2>;
1254 ranges;
1255 status = "disabled";
1256
1257 i2c6: i2c@4c80000 {
1258 compatible = "qcom,geni-i2c";
1259 reg = <0x0 0x04c80000 0x0 0x4000>;
1260 clock-names = "se";
1261 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1262 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
1263 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1264 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1265 dma-names = "tx", "rx";
1266 #address-cells = <1>;
1267 #size-cells = <0>;
1268 status = "disabled";
1269 };
1270
1271 spi6: spi@4c80000 {
1272 compatible = "qcom,geni-spi";
1273 reg = <0x0 0x04c80000 0x0 0x4000>;
1274 clock-names = "se";
1275 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1276 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
1277 power-domains = <&rpmpd SM6375_VDDCX>;
1278 operating-points-v2 = <&qup_opp_table>;
1279 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1280 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1281 dma-names = "tx", "rx";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 status = "disabled";
1285 };
1286
1287 i2c7: i2c@4c84000 {
1288 compatible = "qcom,geni-i2c";
1289 reg = <0x0 0x04c84000 0x0 0x4000>;
1290 clock-names = "se";
1291 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1292 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1293 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1294 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1295 dma-names = "tx", "rx";
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1298 status = "disabled";
1299 };
1300
1301 spi7: spi@4c84000 {
1302 compatible = "qcom,geni-spi";
1303 reg = <0x0 0x04c84000 0x0 0x4000>;
1304 clock-names = "se";
1305 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1306 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1307 power-domains = <&rpmpd SM6375_VDDCX>;
1308 operating-points-v2 = <&qup_opp_table>;
1309 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1310 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1311 dma-names = "tx", "rx";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314 status = "disabled";
1315 };
1316
1317 i2c8: i2c@4c88000 {
1318 compatible = "qcom,geni-i2c";
1319 reg = <0x0 0x04c88000 0x0 0x4000>;
1320 clock-names = "se";
1321 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1322 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_i2c8_default>;
1325 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1326 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1327 dma-names = "tx", "rx";
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1330 status = "disabled";
1331 };
1332
1333 spi8: spi@4c88000 {
1334 compatible = "qcom,geni-spi";
1335 reg = <0x0 0x04c88000 0x0 0x4000>;
1336 clock-names = "se";
1337 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1338 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1339 power-domains = <&rpmpd SM6375_VDDCX>;
1340 operating-points-v2 = <&qup_opp_table>;
1341 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1342 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1343 dma-names = "tx", "rx";
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1346 status = "disabled";
1347 };
1348
1349 i2c9: i2c@4c8c000 {
1350 compatible = "qcom,geni-i2c";
1351 reg = <0x0 0x04c8c000 0x0 0x4000>;
1352 clock-names = "se";
1353 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1354 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
1355 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1356 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1357 dma-names = "tx", "rx";
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360 status = "disabled";
1361 };
1362
1363 spi9: spi@4c8c000 {
1364 compatible = "qcom,geni-spi";
1365 reg = <0x0 0x04c8c000 0x0 0x4000>;
1366 clock-names = "se";
1367 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1368 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
1369 power-domains = <&rpmpd SM6375_VDDCX>;
1370 operating-points-v2 = <&qup_opp_table>;
1371 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1372 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1373 dma-names = "tx", "rx";
1374 #address-cells = <1>;
1375 #size-cells = <0>;
1376 status = "disabled";
1377 };
1378
1379 i2c10: i2c@4c90000 {
1380 compatible = "qcom,geni-i2c";
1381 reg = <0x0 0x04c90000 0x0 0x4000>;
1382 clock-names = "se";
1383 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1384 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&qup_i2c10_default>;
1387 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1388 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1389 dma-names = "tx", "rx";
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392 status = "disabled";
1393 };
1394
1395 spi10: spi@4c90000 {
1396 compatible = "qcom,geni-spi";
1397 reg = <0x0 0x04c90000 0x0 0x4000>;
1398 clock-names = "se";
1399 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1400 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
1401 power-domains = <&rpmpd SM6375_VDDCX>;
1402 operating-points-v2 = <&qup_opp_table>;
1403 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1404 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1405 dma-names = "tx", "rx";
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1408 status = "disabled";
1409 };
1410 };
1411
1412 usb_1: usb@4ef8800 {
1413 compatible = "qcom,sm6375-dwc3", "qcom,dwc3";
1414 reg = <0 0x04ef8800 0 0x400>;
1415
1416 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1417 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1418 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1419 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1420 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1421 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1422 clock-names = "cfg_noc",
1423 "core",
1424 "iface",
1425 "sleep",
1426 "mock_utmi",
1427 "xo";
1428
1429 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1430 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1431 assigned-clock-rates = <19200000>, <133333333>;
1432
1433 interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1434 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1435 <&mpm 94 IRQ_TYPE_EDGE_BOTH>,
1436 <&mpm 93 IRQ_TYPE_EDGE_BOTH>,
1437 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
1438 interrupt-names = "pwr_event",
1439 "hs_phy_irq",
1440 "dp_hs_phy_irq",
1441 "dm_hs_phy_irq",
1442 "ss_phy_irq";
1443
1444 power-domains = <&gcc USB30_PRIM_GDSC>;
1445
1446 resets = <&gcc GCC_USB30_PRIM_BCR>;
1447
1448 /*
1449 * This property is there to allow USB2 to work, as
1450 * USB3 is not implemented yet - (re)move it when
1451 * proper support is in place.
1452 */
1453 qcom,select-utmi-as-pipe-clk;
1454
1455 #address-cells = <2>;
1456 #size-cells = <2>;
1457 ranges;
1458
1459 status = "disabled";
1460
1461 usb_1_dwc3: usb@4e00000 {
1462 compatible = "snps,dwc3";
1463 reg = <0 0x04e00000 0 0xcd00>;
1464 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1465 maximum-speed = "high-speed";
1466 phys = <&usb_1_hsphy>;
1467 phy-names = "usb2-phy";
1468 iommus = <&apps_smmu 0xe0 0x0>;
1469
1470 /* Yes, this impl *does* have an unfunny number of quirks.. */
1471 snps,hird-threshold = /bits/ 8 <0x10>;
1472 snps,usb2-gadget-lpm-disable;
1473 snps,dis_u2_susphy_quirk;
1474 snps,is-utmi-l1-suspend;
1475 snps,dis-u1-entry-quirk;
1476 snps,dis-u2-entry-quirk;
1477 snps,usb3_lpm_capable;
1478 snps,has-lpm-erratum;
1479 tx-fifo-resize;
1480 };
1481 };
1482
1483 adreno_smmu: iommu@5940000 {
1484 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2";
1485 reg = <0 0x05940000 0 0x10000>;
1486 #iommu-cells = <1>;
1487 #global-interrupts = <2>;
1488 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1498
1499 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1500 clock-names = "bus";
1501
1502 power-domains = <&gpucc GPU_CX_GDSC>;
1503 };
1504
1505 gpucc: clock-controller@5990000 {
1506 compatible = "qcom,sm6375-gpucc";
1507 reg = <0 0x05990000 0 0x9000>;
1508 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1509 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1510 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
1511 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1512 power-domains = <&rpmpd SM6375_VDDGX>;
1513 required-opps = <&rpmpd_opp_low_svs>;
1514 #clock-cells = <1>;
1515 #reset-cells = <1>;
1516 #power-domain-cells = <1>;
1517 };
1518
1519 remoteproc_mss: remoteproc@6000000 {
1520 compatible = "qcom,sm6375-mpss-pas";
1521 reg = <0 0x06000000 0 0x4040>;
1522
1523 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1524 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1525 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1526 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1527 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1528 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1529 interrupt-names = "wdog",
1530 "fatal",
1531 "ready",
1532 "handover",
1533 "stop-ack",
1534 "shutdown-ack";
1535
1536 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1537 clock-names = "xo";
1538
1539 power-domains = <&rpmpd SM6375_VDDCX>;
1540 power-domain-names = "cx";
1541
1542 memory-region = <&pil_mpss_wlan_mem>;
1543
1544 qcom,smem-states = <&smp2p_modem_out 0>;
1545 qcom,smem-state-names = "stop";
1546
1547 status = "disabled";
1548
1549 glink-edge {
1550 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1551 IPCC_MPROC_SIGNAL_GLINK_QMP
1552 IRQ_TYPE_EDGE_RISING>;
1553 mboxes = <&ipcc IPCC_CLIENT_MPSS
1554 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1555 label = "modem";
1556 qcom,remote-pid = <1>;
1557 };
1558 };
1559
1560 remoteproc_adsp: remoteproc@a400000 {
1561 compatible = "qcom,sm6375-adsp-pas";
1562 reg = <0 0x0a400000 0 0x100>;
1563
1564 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1565 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1566 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1567 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1568 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1569 interrupt-names = "wdog", "fatal", "ready",
1570 "handover", "stop-ack";
1571
1572 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1573 clock-names = "xo";
1574
1575 power-domains = <&rpmpd SM6375_VDD_LPI_CX>,
1576 <&rpmpd SM6375_VDD_LPI_MX>;
1577 power-domain-names = "lcx", "lmx";
1578
1579 memory-region = <&pil_adsp_mem>;
1580
1581 qcom,smem-states = <&smp2p_adsp_out 0>;
1582 qcom,smem-state-names = "stop";
1583
1584 status = "disabled";
1585
1586 glink-edge {
1587 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1588 IPCC_MPROC_SIGNAL_GLINK_QMP
1589 IRQ_TYPE_EDGE_RISING>;
1590 mboxes = <&ipcc IPCC_CLIENT_LPASS
1591 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1592
1593 label = "lpass";
1594 qcom,remote-pid = <2>;
1595 };
1596 };
1597
1598 remoteproc_cdsp: remoteproc@b000000 {
1599 compatible = "qcom,sm6375-cdsp-pas";
1600 reg = <0x0 0x0b000000 0x0 0x100000>;
1601
1602 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
1603 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1604 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1605 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1606 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1607 interrupt-names = "wdog", "fatal", "ready",
1608 "handover", "stop-ack";
1609
1610 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1611 clock-names = "xo";
1612
1613 power-domains = <&rpmpd SM6375_VDDCX>;
1614 power-domain-names = "cx";
1615
1616 memory-region = <&pil_cdsp_mem>;
1617
1618 qcom,smem-states = <&smp2p_cdsp_out 0>;
1619 qcom,smem-state-names = "stop";
1620
1621 status = "disabled";
1622
1623 glink-edge {
1624 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1625 IPCC_MPROC_SIGNAL_GLINK_QMP
1626 IRQ_TYPE_EDGE_RISING>;
1627 mboxes = <&ipcc IPCC_CLIENT_CDSP
1628 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1629 label = "cdsp";
1630 qcom,remote-pid = <5>;
1631 };
1632 };
1633
1634 sram@c125000 {
1635 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd";
1636 reg = <0 0x0c125000 0 0x1000>;
1637 ranges = <0 0 0x0c125000 0x1000>;
1638
1639 #address-cells = <1>;
1640 #size-cells = <1>;
1641
1642 pil-reloc@94c {
1643 compatible = "qcom,pil-reloc-info";
1644 reg = <0x94c 0xc8>;
1645 };
1646 };
1647
1648 apps_smmu: iommu@c600000 {
1649 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500";
1650 reg = <0 0x0c600000 0 0x100000>;
1651 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1652 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1656 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1657 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1658 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1659 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1660 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1661 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1662 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1663 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1664 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1665 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1666 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1667 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1668 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1669 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1670 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1671 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1672 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1673 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1674 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1675 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1676 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1677 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1678 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1680 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1681 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1682 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1683 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1684 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1685 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1686 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1687 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1688 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1689 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1690 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1691 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1692 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1693 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1694 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1695 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1696 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1699 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1713 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1714 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1715 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1716
1717 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>,
1718 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>,
1719 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
1720 #global-interrupts = <1>;
1721 #iommu-cells = <2>;
1722 };
1723
1724 wifi: wifi@c800000 {
1725 compatible = "qcom,wcn3990-wifi";
1726 reg = <0 0x0c800000 0 0x800000>;
1727 reg-names = "membase";
1728 memory-region = <&pil_wlan_mem>;
1729 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1741 iommus = <&apps_smmu 0x80 0x1>;
1742 qcom,msa-fixed-perm;
1743 status = "disabled";
1744 };
1745
1746 intc: interrupt-controller@f200000 {
1747 compatible = "arm,gic-v3";
1748 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */
1749 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */
1750 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
1751 #redistributor-regions = <1>;
1752 #interrupt-cells = <3>;
1753 redistributor-stride = <0 0x20000>;
1754 interrupt-controller;
1755 };
1756
1757 timer@f420000 {
1758 compatible = "arm,armv7-timer-mem";
1759 reg = <0 0x0f420000 0 0x1000>;
1760 ranges = <0 0 0 0x20000000>;
1761 #address-cells = <1>;
1762 #size-cells = <1>;
1763
1764 frame@f421000 {
1765 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>;
1766 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1768 frame-number = <0>;
1769 };
1770
1771 frame@f423000 {
1772 reg = <0x0f243000 0x1000>;
1773 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1774 frame-number = <1>;
1775 status = "disabled";
1776 };
1777
1778 frame@f425000 {
1779 reg = <0x0f425000 0x1000>;
1780 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1781 frame-number = <2>;
1782 status = "disabled";
1783 };
1784
1785 frame@f427000 {
1786 reg = <0x0f427000 0x1000>;
1787 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1788 frame-number = <3>;
1789 status = "disabled";
1790 };
1791
1792 frame@f429000 {
1793 reg = <0x0f429000 0x1000>;
1794 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1795 frame-number = <4>;
1796 status = "disabled";
1797 };
1798
1799 frame@f42b000 {
1800 reg = <0x0f42b000 0x1000>;
1801 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1802 frame-number = <5>;
1803 status = "disabled";
1804 };
1805
1806 frame@f42d000 {
1807 reg = <0x0f42d000 0x1000>;
1808 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1809 frame-number = <6>;
1810 status = "disabled";
1811 };
1812 };
1813
1814 cpucp_l3: interconnect@fd90000 {
1815 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
1816 reg = <0 0x0fd90000 0 0x1000>;
1817
1818 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
1819 clock-names = "xo", "alternate";
1820 #interconnect-cells = <1>;
1821 };
1822
1823 cpufreq_hw: cpufreq@fd91000 {
1824 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
1825 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
1826 reg-names = "freq-domain0", "freq-domain1";
1827
1828 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
1829 clock-names = "xo", "alternate";
1830 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1832 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
1833 #freq-domain-cells = <1>;
1834 #clock-cells = <1>;
1835 };
1836 };
1837
1838 thermal-zones {
1839 mapss0-thermal {
1840 thermal-sensors = <&tsens0 0>;
1841
1842 trips {
1843 mapss0_alert0: trip-point0 {
1844 temperature = <90000>;
1845 hysteresis = <2000>;
1846 type = "passive";
1847 };
1848
1849 mapss0_alert1: trip-point1 {
1850 temperature = <95000>;
1851 hysteresis = <2000>;
1852 type = "passive";
1853 };
1854
1855 mapss0_crit: mapss-crit {
1856 temperature = <110000>;
1857 hysteresis = <1000>;
1858 type = "critical";
1859 };
1860 };
1861 };
1862
1863 cpu0-thermal {
1864 thermal-sensors = <&tsens0 1>;
1865
1866 trips {
1867 cpu0_alert0: trip-point0 {
1868 temperature = <90000>;
1869 hysteresis = <2000>;
1870 type = "passive";
1871 };
1872
1873 cpu0_alert1: trip-point1 {
1874 temperature = <95000>;
1875 hysteresis = <2000>;
1876 type = "passive";
1877 };
1878
1879 cpu0_crit: cpu-crit {
1880 temperature = <110000>;
1881 hysteresis = <1000>;
1882 type = "critical";
1883 };
1884 };
1885 };
1886
1887 cpu1-thermal {
1888 thermal-sensors = <&tsens0 2>;
1889
1890 trips {
1891 cpu1_alert0: trip-point0 {
1892 temperature = <90000>;
1893 hysteresis = <2000>;
1894 type = "passive";
1895 };
1896
1897 cpu1_alert1: trip-point1 {
1898 temperature = <95000>;
1899 hysteresis = <2000>;
1900 type = "passive";
1901 };
1902
1903 cpu1_crit: cpu-crit {
1904 temperature = <110000>;
1905 hysteresis = <1000>;
1906 type = "critical";
1907 };
1908 };
1909 };
1910
1911 cpu2-thermal {
1912 thermal-sensors = <&tsens0 3>;
1913
1914 trips {
1915 cpu2_alert0: trip-point0 {
1916 temperature = <90000>;
1917 hysteresis = <2000>;
1918 type = "passive";
1919 };
1920
1921 cpu2_alert1: trip-point1 {
1922 temperature = <95000>;
1923 hysteresis = <2000>;
1924 type = "passive";
1925 };
1926
1927 cpu2_crit: cpu-crit {
1928 temperature = <110000>;
1929 hysteresis = <1000>;
1930 type = "critical";
1931 };
1932 };
1933 };
1934
1935 cpu3-thermal {
1936 thermal-sensors = <&tsens0 4>;
1937
1938 trips {
1939 cpu3_alert0: trip-point0 {
1940 temperature = <90000>;
1941 hysteresis = <2000>;
1942 type = "passive";
1943 };
1944
1945 cpu3_alert1: trip-point1 {
1946 temperature = <95000>;
1947 hysteresis = <2000>;
1948 type = "passive";
1949 };
1950
1951 cpu3_crit: cpu-crit {
1952 temperature = <110000>;
1953 hysteresis = <1000>;
1954 type = "critical";
1955 };
1956 };
1957 };
1958
1959 cpu4-thermal {
1960 thermal-sensors = <&tsens0 5>;
1961
1962 trips {
1963 cpu4_alert0: trip-point0 {
1964 temperature = <90000>;
1965 hysteresis = <2000>;
1966 type = "passive";
1967 };
1968
1969 cpu4_alert1: trip-point1 {
1970 temperature = <95000>;
1971 hysteresis = <2000>;
1972 type = "passive";
1973 };
1974
1975 cpu4_crit: cpu-crit {
1976 temperature = <110000>;
1977 hysteresis = <1000>;
1978 type = "critical";
1979 };
1980 };
1981 };
1982
1983 cpu5-thermal {
1984 thermal-sensors = <&tsens0 6>;
1985
1986 trips {
1987 cpu5_alert0: trip-point0 {
1988 temperature = <90000>;
1989 hysteresis = <2000>;
1990 type = "passive";
1991 };
1992
1993 cpu5_alert1: trip-point1 {
1994 temperature = <95000>;
1995 hysteresis = <2000>;
1996 type = "passive";
1997 };
1998
1999 cpu5_crit: cpu-crit {
2000 temperature = <110000>;
2001 hysteresis = <1000>;
2002 type = "critical";
2003 };
2004 };
2005 };
2006
2007 cluster0-thermal {
2008 thermal-sensors = <&tsens0 7>;
2009
2010 trips {
2011 cluster0_alert0: trip-point0 {
2012 temperature = <90000>;
2013 hysteresis = <2000>;
2014 type = "passive";
2015 };
2016
2017 cluster0_alert1: trip-point1 {
2018 temperature = <95000>;
2019 hysteresis = <2000>;
2020 type = "passive";
2021 };
2022
2023 cluster0_crit: cpu-crit {
2024 temperature = <110000>;
2025 hysteresis = <1000>;
2026 type = "critical";
2027 };
2028 };
2029 };
2030
2031 cluster1-thermal {
2032 thermal-sensors = <&tsens0 8>;
2033
2034 trips {
2035 cluster1_alert0: trip-point0 {
2036 temperature = <90000>;
2037 hysteresis = <2000>;
2038 type = "passive";
2039 };
2040
2041 cluster1_alert1: trip-point1 {
2042 temperature = <95000>;
2043 hysteresis = <2000>;
2044 type = "passive";
2045 };
2046
2047 cluster1_crit: cpu-crit {
2048 temperature = <110000>;
2049 hysteresis = <1000>;
2050 type = "critical";
2051 };
2052 };
2053 };
2054
2055 cpu6-thermal {
2056 thermal-sensors = <&tsens0 9>;
2057
2058 trips {
2059 cpu6_alert0: trip-point0 {
2060 temperature = <90000>;
2061 hysteresis = <2000>;
2062 type = "passive";
2063 };
2064
2065 cpu6_alert1: trip-point1 {
2066 temperature = <95000>;
2067 hysteresis = <2000>;
2068 type = "passive";
2069 };
2070
2071 cpu6_crit: cpu-crit {
2072 temperature = <110000>;
2073 hysteresis = <1000>;
2074 type = "critical";
2075 };
2076 };
2077 };
2078
2079 cpu7-thermal {
2080 thermal-sensors = <&tsens0 10>;
2081
2082 trips {
2083 cpu7_alert0: trip-point0 {
2084 temperature = <90000>;
2085 hysteresis = <2000>;
2086 type = "passive";
2087 };
2088
2089 cpu7_alert1: trip-point1 {
2090 temperature = <95000>;
2091 hysteresis = <2000>;
2092 type = "passive";
2093 };
2094
2095 cpu7_crit: cpu-crit {
2096 temperature = <110000>;
2097 hysteresis = <1000>;
2098 type = "critical";
2099 };
2100 };
2101 };
2102
2103 cpu-unk0-thermal {
2104 thermal-sensors = <&tsens0 11>;
2105
2106 trips {
2107 cpu_unk0_alert0: trip-point0 {
2108 temperature = <90000>;
2109 hysteresis = <2000>;
2110 type = "passive";
2111 };
2112
2113 cpu_unk0_alert1: trip-point1 {
2114 temperature = <95000>;
2115 hysteresis = <2000>;
2116 type = "passive";
2117 };
2118
2119 cpu_unk0_crit: cpu-crit {
2120 temperature = <110000>;
2121 hysteresis = <1000>;
2122 type = "critical";
2123 };
2124 };
2125 };
2126
2127 cpu-unk1-thermal {
2128 thermal-sensors = <&tsens0 12>;
2129
2130 trips {
2131 cpu_unk1_alert0: trip-point0 {
2132 temperature = <90000>;
2133 hysteresis = <2000>;
2134 type = "passive";
2135 };
2136
2137 cpu_unk1_alert1: trip-point1 {
2138 temperature = <95000>;
2139 hysteresis = <2000>;
2140 type = "passive";
2141 };
2142
2143 cpu_unk1_crit: cpu-crit {
2144 temperature = <110000>;
2145 hysteresis = <1000>;
2146 type = "critical";
2147 };
2148 };
2149 };
2150
2151 gpuss0-thermal {
2152 thermal-sensors = <&tsens0 13>;
2153
2154 trips {
2155 gpuss0_alert0: trip-point0 {
2156 temperature = <90000>;
2157 hysteresis = <2000>;
2158 type = "passive";
2159 };
2160
2161 gpuss0_alert1: trip-point1 {
2162 temperature = <95000>;
2163 hysteresis = <2000>;
2164 type = "passive";
2165 };
2166
2167 gpuss0_crit: gpu-crit {
2168 temperature = <110000>;
2169 hysteresis = <1000>;
2170 type = "critical";
2171 };
2172 };
2173 };
2174
2175 gpuss1-thermal {
2176 thermal-sensors = <&tsens0 14>;
2177
2178 trips {
2179 gpuss1_alert0: trip-point0 {
2180 temperature = <90000>;
2181 hysteresis = <2000>;
2182 type = "passive";
2183 };
2184
2185 gpuss1_alert1: trip-point1 {
2186 temperature = <95000>;
2187 hysteresis = <2000>;
2188 type = "passive";
2189 };
2190
2191 gpuss1_crit: gpu-crit {
2192 temperature = <110000>;
2193 hysteresis = <1000>;
2194 type = "critical";
2195 };
2196 };
2197 };
2198
2199 mapss1-thermal {
2200 thermal-sensors = <&tsens1 0>;
2201
2202 trips {
2203 mapss1_alert0: trip-point0 {
2204 temperature = <90000>;
2205 hysteresis = <2000>;
2206 type = "passive";
2207 };
2208
2209 mapss1_alert1: trip-point1 {
2210 temperature = <95000>;
2211 hysteresis = <2000>;
2212 type = "passive";
2213 };
2214
2215 mapss1_crit: mapss-crit {
2216 temperature = <110000>;
2217 hysteresis = <1000>;
2218 type = "critical";
2219 };
2220 };
2221 };
2222
2223 cwlan-thermal {
2224 thermal-sensors = <&tsens1 1>;
2225
2226 trips {
2227 cwlan_alert0: trip-point0 {
2228 temperature = <90000>;
2229 hysteresis = <2000>;
2230 type = "passive";
2231 };
2232
2233 cwlan_alert1: trip-point1 {
2234 temperature = <95000>;
2235 hysteresis = <2000>;
2236 type = "passive";
2237 };
2238
2239 cwlan_crit: cwlan-crit {
2240 temperature = <110000>;
2241 hysteresis = <1000>;
2242 type = "critical";
2243 };
2244 };
2245 };
2246
2247 audio-thermal {
2248 thermal-sensors = <&tsens1 2>;
2249
2250 trips {
2251 audio_alert0: trip-point0 {
2252 temperature = <90000>;
2253 hysteresis = <2000>;
2254 type = "passive";
2255 };
2256
2257 audio_alert1: trip-point1 {
2258 temperature = <95000>;
2259 hysteresis = <2000>;
2260 type = "passive";
2261 };
2262
2263 audio_crit: audio-crit {
2264 temperature = <110000>;
2265 hysteresis = <1000>;
2266 type = "critical";
2267 };
2268 };
2269 };
2270
2271 ddr-thermal {
2272 thermal-sensors = <&tsens1 3>;
2273
2274 trips {
2275 ddr_alert0: trip-point0 {
2276 temperature = <90000>;
2277 hysteresis = <2000>;
2278 type = "passive";
2279 };
2280
2281 ddr_alert1: trip-point1 {
2282 temperature = <95000>;
2283 hysteresis = <2000>;
2284 type = "passive";
2285 };
2286
2287 ddr_crit: ddr-crit {
2288 temperature = <110000>;
2289 hysteresis = <1000>;
2290 type = "critical";
2291 };
2292 };
2293 };
2294
2295 q6hvx-thermal {
2296 thermal-sensors = <&tsens1 4>;
2297
2298 trips {
2299 q6hvx_alert0: trip-point0 {
2300 temperature = <90000>;
2301 hysteresis = <2000>;
2302 type = "passive";
2303 };
2304
2305 q6hvx_alert1: trip-point1 {
2306 temperature = <95000>;
2307 hysteresis = <2000>;
2308 type = "passive";
2309 };
2310
2311 q6hvx_crit: q6hvx-crit {
2312 temperature = <110000>;
2313 hysteresis = <1000>;
2314 type = "critical";
2315 };
2316 };
2317 };
2318
2319 camera-thermal {
2320 thermal-sensors = <&tsens1 5>;
2321
2322 trips {
2323 camera_alert0: trip-point0 {
2324 temperature = <90000>;
2325 hysteresis = <2000>;
2326 type = "passive";
2327 };
2328
2329 camera_alert1: trip-point1 {
2330 temperature = <95000>;
2331 hysteresis = <2000>;
2332 type = "passive";
2333 };
2334
2335 camera_crit: camera-crit {
2336 temperature = <110000>;
2337 hysteresis = <1000>;
2338 type = "critical";
2339 };
2340 };
2341 };
2342
2343 mdm-core0-thermal {
2344 thermal-sensors = <&tsens1 6>;
2345
2346 trips {
2347 mdm_core0_alert0: trip-point0 {
2348 temperature = <90000>;
2349 hysteresis = <2000>;
2350 type = "passive";
2351 };
2352
2353 mdm_core0_alert1: trip-point1 {
2354 temperature = <95000>;
2355 hysteresis = <2000>;
2356 type = "passive";
2357 };
2358
2359 mdm_core0_crit: mdm-core0-crit {
2360 temperature = <110000>;
2361 hysteresis = <1000>;
2362 type = "critical";
2363 };
2364 };
2365 };
2366
2367 mdm-core1-thermal {
2368 thermal-sensors = <&tsens1 7>;
2369
2370 trips {
2371 mdm_core1_alert0: trip-point0 {
2372 temperature = <90000>;
2373 hysteresis = <2000>;
2374 type = "passive";
2375 };
2376
2377 mdm_core1_alert1: trip-point1 {
2378 temperature = <95000>;
2379 hysteresis = <2000>;
2380 type = "passive";
2381 };
2382
2383 mdm_core1_crit: mdm-core1-crit {
2384 temperature = <110000>;
2385 hysteresis = <1000>;
2386 type = "critical";
2387 };
2388 };
2389 };
2390
2391 mdm-vec-thermal {
2392 thermal-sensors = <&tsens1 8>;
2393
2394 trips {
2395 mdm_vec_alert0: trip-point0 {
2396 temperature = <90000>;
2397 hysteresis = <2000>;
2398 type = "passive";
2399 };
2400
2401 mdm_vec_alert1: trip-point1 {
2402 temperature = <95000>;
2403 hysteresis = <2000>;
2404 type = "passive";
2405 };
2406
2407 mdm_vec_crit: mdm-vec-crit {
2408 temperature = <110000>;
2409 hysteresis = <1000>;
2410 type = "critical";
2411 };
2412 };
2413 };
2414
2415 msm-scl-thermal {
2416 thermal-sensors = <&tsens1 9>;
2417
2418 trips {
2419 msm_scl_alert0: trip-point0 {
2420 temperature = <90000>;
2421 hysteresis = <2000>;
2422 type = "passive";
2423 };
2424
2425 msm_scl_alert1: trip-point1 {
2426 temperature = <95000>;
2427 hysteresis = <2000>;
2428 type = "passive";
2429 };
2430
2431 msm_scl_crit: msm-scl-crit {
2432 temperature = <110000>;
2433 hysteresis = <1000>;
2434 type = "critical";
2435 };
2436 };
2437 };
2438
2439 video-thermal {
2440 thermal-sensors = <&tsens1 10>;
2441
2442 trips {
2443 video_alert0: trip-point0 {
2444 temperature = <90000>;
2445 hysteresis = <2000>;
2446 type = "passive";
2447 };
2448
2449 video_alert1: trip-point1 {
2450 temperature = <95000>;
2451 hysteresis = <2000>;
2452 type = "passive";
2453 };
2454
2455 video_crit: video-crit {
2456 temperature = <110000>;
2457 hysteresis = <1000>;
2458 type = "critical";
2459 };
2460 };
2461 };
2462 };
2463
2464 timer {
2465 compatible = "arm,armv8-timer";
2466 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2467 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2468 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2469 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2470 };
2471 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.