1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited
5 */
6
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc.h>
21 #include <dt-bindings/thermal/thermal.h>
22
23 / {
24 interrupt-parent = <&intc>;
25
26 #address-cells = <2>;
27 #size-cells = <2>;
28
29 chosen { };
30
31 clocks {
32 xo_board: xo-board {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <38400000>;
36 clock-output-names = "xo_board";
37 };
38
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <32764>;
43 clock-output-names = "sleep_clk";
44 };
45 };
46
47 cpus {
48 #address-cells = <2>;
49 #size-cells = <0>;
50
51 CPU0: cpu@0 {
52 device_type = "cpu";
53 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
56 enable-method = "psci";
57 capacity-dmips-mhz = <488>;
58 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
63 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_PD0>;
65 power-domain-names = "psci";
66 #cooling-cells = <2>;
67 L2_0: l2-cache {
68 compatible = "cache";
69 cache-level = <2>;
70 cache-unified;
71 next-level-cache = <&L3_0>;
72 L3_0: l3-cache {
73 compatible = "cache";
74 cache-level = <3>;
75 cache-unified;
76 };
77 };
78 };
79
80 CPU1: cpu@100 {
81 device_type = "cpu";
82 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci";
86 capacity-dmips-mhz = <488>;
87 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
92 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_PD1>;
94 power-domain-names = "psci";
95 #cooling-cells = <2>;
96 L2_100: l2-cache {
97 compatible = "cache";
98 cache-level = <2>;
99 cache-unified;
100 next-level-cache = <&L3_0>;
101 };
102 };
103
104 CPU2: cpu@200 {
105 device_type = "cpu";
106 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw 0>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <488>;
111 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_PD2>;
118 power-domain-names = "psci";
119 #cooling-cells = <2>;
120 L2_200: l2-cache {
121 compatible = "cache";
122 cache-level = <2>;
123 cache-unified;
124 next-level-cache = <&L3_0>;
125 };
126 };
127
128 CPU3: cpu@300 {
129 device_type = "cpu";
130 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 0>;
133 enable-method = "psci";
134 capacity-dmips-mhz = <488>;
135 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
140 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_PD3>;
142 power-domain-names = "psci";
143 #cooling-cells = <2>;
144 L2_300: l2-cache {
145 compatible = "cache";
146 cache-level = <2>;
147 cache-unified;
148 next-level-cache = <&L3_0>;
149 };
150 };
151
152 CPU4: cpu@400 {
153 device_type = "cpu";
154 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw 1>;
157 enable-method = "psci";
158 capacity-dmips-mhz = <1024>;
159 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
164 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_PD4>;
166 power-domain-names = "psci";
167 #cooling-cells = <2>;
168 L2_400: l2-cache {
169 compatible = "cache";
170 cache-level = <2>;
171 cache-unified;
172 next-level-cache = <&L3_0>;
173 };
174 };
175
176 CPU5: cpu@500 {
177 device_type = "cpu";
178 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw 1>;
181 enable-method = "psci";
182 capacity-dmips-mhz = <1024>;
183 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
188 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_PD5>;
190 power-domain-names = "psci";
191 #cooling-cells = <2>;
192 L2_500: l2-cache {
193 compatible = "cache";
194 cache-level = <2>;
195 cache-unified;
196 next-level-cache = <&L3_0>;
197 };
198 };
199
200 CPU6: cpu@600 {
201 device_type = "cpu";
202 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw 1>;
205 enable-method = "psci";
206 capacity-dmips-mhz = <1024>;
207 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
212 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_PD6>;
214 power-domain-names = "psci";
215 #cooling-cells = <2>;
216 L2_600: l2-cache {
217 compatible = "cache";
218 cache-level = <2>;
219 cache-unified;
220 next-level-cache = <&L3_0>;
221 };
222 };
223
224 CPU7: cpu@700 {
225 device_type = "cpu";
226 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw 2>;
229 enable-method = "psci";
230 capacity-dmips-mhz = <1024>;
231 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
236 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_PD7>;
238 power-domain-names = "psci";
239 #cooling-cells = <2>;
240 L2_700: l2-cache {
241 compatible = "cache";
242 cache-level = <2>;
243 cache-unified;
244 next-level-cache = <&L3_0>;
245 };
246 };
247
248 cpu-map {
249 cluster0 {
250 core0 {
251 cpu = <&CPU0>;
252 };
253
254 core1 {
255 cpu = <&CPU1>;
256 };
257
258 core2 {
259 cpu = <&CPU2>;
260 };
261
262 core3 {
263 cpu = <&CPU3>;
264 };
265
266 core4 {
267 cpu = <&CPU4>;
268 };
269
270 core5 {
271 cpu = <&CPU5>;
272 };
273
274 core6 {
275 cpu = <&CPU6>;
276 };
277
278 core7 {
279 cpu = <&CPU7>;
280 };
281 };
282 };
283
284 idle-states {
285 entry-method = "psci";
286
287 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = "arm,idle-state";
289 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspend-param = <0x40000004>;
291 entry-latency-us = <355>;
292 exit-latency-us = <909>;
293 min-residency-us = <3934>;
294 local-timer-stop;
295 };
296
297 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = "arm,idle-state";
299 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspend-param = <0x40000004>;
301 entry-latency-us = <241>;
302 exit-latency-us = <1461>;
303 min-residency-us = <4488>;
304 local-timer-stop;
305 };
306 };
307
308 domain-idle-states {
309 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = "domain-idle-state";
311 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency-us = <3263>;
313 exit-latency-us = <6562>;
314 min-residency-us = <9987>;
315 };
316 };
317 };
318
319 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points-v2";
321 opp-shared;
322
323 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <800000 9600000>;
326 };
327
328 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <800000 9600000>;
331 };
332
333 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <800000 12902400>;
336 };
337
338 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <800000 12902400>;
341 };
342
343 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <800000 15974400>;
346 };
347
348 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <1804000 19660800>;
351 };
352
353 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <1804000 19660800>;
356 };
357
358 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <1804000 22732800>;
361 };
362
363 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <1804000 22732800>;
366 };
367
368 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <2188000 25804800>;
371 };
372
373 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <2188000 31948800>;
376 };
377
378 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <3072000 31948800>;
381 };
382
383 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <3072000 31948800>;
386 };
387
388 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <3072000 31948800>;
391 };
392
393 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <3072000 40550400>;
396 };
397
398 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <3072000 40550400>;
401 };
402
403 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <3072000 43008000>;
406 };
407
408 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <3072000 43008000>;
411 };
412 };
413
414 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points-v2";
416 opp-shared;
417
418 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <1804000 15974400>;
421 };
422
423 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <2188000 19660800>;
426 };
427
428 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <2188000 22732800>;
431 };
432
433 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <3072000 25804800>;
436 };
437
438 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <3072000 31948800>;
441 };
442
443 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <4068000 31948800>;
446 };
447
448 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <4068000 31948800>;
451 };
452
453 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <4068000 40550400>;
456 };
457
458 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <4068000 40550400>;
461 };
462
463 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <4068000 43008000>;
466 };
467
468 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <6220000 43008000>;
471 };
472
473 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <6220000 49152000>;
476 };
477
478 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <7216000 49152000>;
481 };
482
483 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <8368000 49152000>;
486 };
487
488 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <8368000 51609600>;
491 };
492
493 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <8368000 51609600>;
496 };
497
498 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <8368000 51609600>;
501 };
502 };
503
504 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points-v2";
506 opp-shared;
507
508 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <2188000 19660800>;
511 };
512
513 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <2188000 22732800>;
516 };
517
518 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <3072000 25804800>;
521 };
522
523 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <3072000 31948800>;
526 };
527
528 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <4068000 31948800>;
531 };
532
533 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <4068000 31948800>;
536 };
537
538 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <4068000 40550400>;
541 };
542
543 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <4068000 40550400>;
546 };
547
548 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <4068000 43008000>;
551 };
552
553 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <6220000 43008000>;
556 };
557
558 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <6220000 49152000>;
561 };
562
563 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <7216000 49152000>;
566 };
567
568 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <8368000 49152000>;
571 };
572
573 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <8368000 51609600>;
576 };
577
578 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <8368000 51609600>;
581 };
582
583 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <8368000 51609600>;
586 };
587
588 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <8368000 51609600>;
591 };
592
593 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <8368000 51609600>;
596 };
597
598 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <8368000 51609600>;
601 };
602
603 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <8368000 51609600>;
606 };
607 };
608
609 firmware {
610 scm: scm {
611 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>;
613 };
614 };
615
616 memory@80000000 {
617 device_type = "memory";
618 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0>;
620 };
621
622 pmu {
623 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 };
626
627 psci {
628 compatible = "arm,psci-1.0";
629 method = "smc";
630
631 CPU_PD0: power-domain-cpu0 {
632 #power-domain-cells = <0>;
633 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 };
636
637 CPU_PD1: power-domain-cpu1 {
638 #power-domain-cells = <0>;
639 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 };
642
643 CPU_PD2: power-domain-cpu2 {
644 #power-domain-cells = <0>;
645 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 };
648
649 CPU_PD3: power-domain-cpu3 {
650 #power-domain-cells = <0>;
651 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 };
654
655 CPU_PD4: power-domain-cpu4 {
656 #power-domain-cells = <0>;
657 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 };
660
661 CPU_PD5: power-domain-cpu5 {
662 #power-domain-cells = <0>;
663 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 };
666
667 CPU_PD6: power-domain-cpu6 {
668 #power-domain-cells = <0>;
669 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 };
672
673 CPU_PD7: power-domain-cpu7 {
674 #power-domain-cells = <0>;
675 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 };
678
679 CLUSTER_PD: power-domain-cpu-cluster0 {
680 #power-domain-cells = <0>;
681 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 };
683 };
684
685 reserved-memory {
686 #address-cells = <2>;
687 #size-cells = <2>;
688 ranges;
689
690 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map;
693 };
694
695 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map;
698 };
699
700 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map;
703 };
704
705 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map;
709 };
710
711 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map;
714 };
715
716 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map;
719 };
720
721 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map;
725
726 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
728 };
729
730 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map;
733 };
734
735 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map;
738 };
739
740 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map;
743 };
744
745 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map;
748 };
749
750 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map;
753 };
754
755 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map;
758 };
759
760 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map;
763 };
764
765 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map;
768 };
769
770 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map;
773 };
774
775 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map;
778 };
779
780 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map;
783 };
784
785 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map;
788 };
789
790 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map;
793 };
794 };
795
796 smem {
797 compatible = "qcom,smem";
798 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>;
800 };
801
802 smp2p-cdsp {
803 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>;
805
806 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807
808 mboxes = <&apss_shared 6>;
809
810 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>;
812
813 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells = <1>;
816 };
817
818 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "slave-kernel";
820
821 interrupt-controller;
822 #interrupt-cells = <2>;
823 };
824 };
825
826 smp2p-lpass {
827 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>;
829
830 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831
832 mboxes = <&apss_shared 10>;
833
834 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>;
836
837 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells = <1>;
840 };
841
842 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "slave-kernel";
844
845 interrupt-controller;
846 #interrupt-cells = <2>;
847 };
848 };
849
850 smp2p-mpss {
851 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>;
853
854 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855
856 mboxes = <&apss_shared 14>;
857
858 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>;
860
861 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells = <1>;
864 };
865
866 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "slave-kernel";
868
869 interrupt-controller;
870 #interrupt-cells = <2>;
871 };
872 };
873
874 smp2p-slpi {
875 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>;
877
878 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879
880 mboxes = <&apss_shared 26>;
881
882 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>;
884
885 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells = <1>;
888 };
889
890 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "slave-kernel";
892
893 interrupt-controller;
894 #interrupt-cells = <2>;
895 };
896 };
897
898 soc: soc@0 {
899 #address-cells = <2>;
900 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus";
904
905 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>;
909 #reset-cells = <1>;
910 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo",
912 "sleep_clk";
913 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>;
915 };
916
917 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
919 reg = <0 0x00800000 0 0x60000>;
920 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>;
934 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>;
937 status = "disabled";
938 };
939
940 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "macirq", "eth_lpi";
953
954 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMAC_BCR>;
956
957 iommus = <&apps_smmu 0x3c0 0x0>;
958
959 snps,tso;
960 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096>;
962
963 status = "disabled";
964 };
965
966 qfprom: efuse@784000 {
967 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
968 reg = <0 0x00784000 0 0x8ff>;
969 #address-cells = <1>;
970 #size-cells = <1>;
971
972 gpu_speed_bin: gpu-speed-bin@133 {
973 reg = <0x133 0x1>;
974 bits = <5 3>;
975 };
976 };
977
978 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>;
986 #size-cells = <2>;
987 ranges;
988 status = "disabled";
989
990 i2c0: i2c@880000 {
991 compatible = "qcom,geni-i2c";
992 reg = <0 0x00880000 0 0x4000>;
993 clock-names = "se";
994 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "tx", "rx";
998 pinctrl-names = "default";
999 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 status = "disabled";
1004 };
1005
1006 spi0: spi@880000 {
1007 compatible = "qcom,geni-spi";
1008 reg = <0 0x00880000 0 0x4000>;
1009 reg-names = "se";
1010 clock-names = "se";
1011 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = "tx", "rx";
1015 pinctrl-names = "default";
1016 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequency = <50000000>;
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 status = "disabled";
1022 };
1023
1024 i2c1: i2c@884000 {
1025 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = "se";
1028 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = "tx", "rx";
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 status = "disabled";
1038 };
1039
1040 spi1: spi@884000 {
1041 compatible = "qcom,geni-spi";
1042 reg = <0 0x00884000 0 0x4000>;
1043 reg-names = "se";
1044 clock-names = "se";
1045 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = "tx", "rx";
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequency = <50000000>;
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 status = "disabled";
1056 };
1057
1058 i2c2: i2c@888000 {
1059 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = "se";
1062 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = "tx", "rx";
1066 pinctrl-names = "default";
1067 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 status = "disabled";
1072 };
1073
1074 spi2: spi@888000 {
1075 compatible = "qcom,geni-spi";
1076 reg = <0 0x00888000 0 0x4000>;
1077 reg-names = "se";
1078 clock-names = "se";
1079 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = "tx", "rx";
1083 pinctrl-names = "default";
1084 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequency = <50000000>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089 status = "disabled";
1090 };
1091
1092 i2c3: i2c@88c000 {
1093 compatible = "qcom,geni-i2c";
1094 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = "se";
1096 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = "tx", "rx";
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 status = "disabled";
1106 };
1107
1108 spi3: spi@88c000 {
1109 compatible = "qcom,geni-spi";
1110 reg = <0 0x0088c000 0 0x4000>;
1111 reg-names = "se";
1112 clock-names = "se";
1113 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = "tx", "rx";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequency = <50000000>;
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 status = "disabled";
1124 };
1125
1126 i2c4: i2c@890000 {
1127 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = "se";
1130 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = "tx", "rx";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1139 status = "disabled";
1140 };
1141
1142 spi4: spi@890000 {
1143 compatible = "qcom,geni-spi";
1144 reg = <0 0x00890000 0 0x4000>;
1145 reg-names = "se";
1146 clock-names = "se";
1147 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = "tx", "rx";
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequency = <50000000>;
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1157 status = "disabled";
1158 };
1159
1160 i2c5: i2c@894000 {
1161 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = "se";
1164 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = "tx", "rx";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1173 status = "disabled";
1174 };
1175
1176 spi5: spi@894000 {
1177 compatible = "qcom,geni-spi";
1178 reg = <0 0x00894000 0 0x4000>;
1179 reg-names = "se";
1180 clock-names = "se";
1181 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = "tx", "rx";
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequency = <50000000>;
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1191 status = "disabled";
1192 };
1193
1194 i2c6: i2c@898000 {
1195 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = "se";
1198 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = "tx", "rx";
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1207 status = "disabled";
1208 };
1209
1210 spi6: spi@898000 {
1211 compatible = "qcom,geni-spi";
1212 reg = <0 0x00898000 0 0x4000>;
1213 reg-names = "se";
1214 clock-names = "se";
1215 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = "tx", "rx";
1219 pinctrl-names = "default";
1220 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequency = <50000000>;
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1225 status = "disabled";
1226 };
1227
1228 i2c7: i2c@89c000 {
1229 compatible = "qcom,geni-i2c";
1230 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = "se";
1232 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = "tx", "rx";
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1241 status = "disabled";
1242 };
1243
1244 spi7: spi@89c000 {
1245 compatible = "qcom,geni-spi";
1246 reg = <0 0x0089c000 0 0x4000>;
1247 reg-names = "se";
1248 clock-names = "se";
1249 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = "tx", "rx";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequency = <50000000>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1259 status = "disabled";
1260 };
1261 };
1262
1263 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1265 reg = <0 0x00a00000 0 0x60000>;
1266 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>;
1280 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>;
1283 status = "disabled";
1284 };
1285
1286 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>;
1294 #size-cells = <2>;
1295 ranges;
1296 status = "disabled";
1297
1298 i2c8: i2c@a80000 {
1299 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = "se";
1302 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = "tx", "rx";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1311 status = "disabled";
1312 };
1313
1314 spi8: spi@a80000 {
1315 compatible = "qcom,geni-spi";
1316 reg = <0 0x00a80000 0 0x4000>;
1317 reg-names = "se";
1318 clock-names = "se";
1319 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = "tx", "rx";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequency = <50000000>;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1329 status = "disabled";
1330 };
1331
1332 i2c9: i2c@a84000 {
1333 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = "se";
1336 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = "tx", "rx";
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cells = <1>;
1344 #size-cells = <0>;
1345 status = "disabled";
1346 };
1347
1348 spi9: spi@a84000 {
1349 compatible = "qcom,geni-spi";
1350 reg = <0 0x00a84000 0 0x4000>;
1351 reg-names = "se";
1352 clock-names = "se";
1353 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = "tx", "rx";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequency = <50000000>;
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1363 status = "disabled";
1364 };
1365
1366 uart9: serial@a84000 {
1367 compatible = "qcom,geni-uart";
1368 reg = <0x0 0x00a84000 0x0 0x4000>;
1369 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1370 clock-names = "se";
1371 pinctrl-0 = <&qup_uart9_default>;
1372 pinctrl-names = "default";
1373 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1374 status = "disabled";
1375 };
1376
1377 i2c10: i2c@a88000 {
1378 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = "se";
1381 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = "tx", "rx";
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cells = <1>;
1389 #size-cells = <0>;
1390 status = "disabled";
1391 };
1392
1393 spi10: spi@a88000 {
1394 compatible = "qcom,geni-spi";
1395 reg = <0 0x00a88000 0 0x4000>;
1396 reg-names = "se";
1397 clock-names = "se";
1398 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = "tx", "rx";
1402 pinctrl-names = "default";
1403 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequency = <50000000>;
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1408 status = "disabled";
1409 };
1410
1411 i2c11: i2c@a8c000 {
1412 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = "se";
1415 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = "tx", "rx";
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1424 status = "disabled";
1425 };
1426
1427 spi11: spi@a8c000 {
1428 compatible = "qcom,geni-spi";
1429 reg = <0 0x00a8c000 0 0x4000>;
1430 reg-names = "se";
1431 clock-names = "se";
1432 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = "tx", "rx";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequency = <50000000>;
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1442 status = "disabled";
1443 };
1444
1445 uart2: serial@a90000 {
1446 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = "se";
1449 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "disabled";
1452 };
1453
1454 i2c12: i2c@a90000 {
1455 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = "se";
1458 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = "tx", "rx";
1462 pinctrl-names = "default";
1463 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1467 status = "disabled";
1468 };
1469
1470 spi12: spi@a90000 {
1471 compatible = "qcom,geni-spi";
1472 reg = <0 0x00a90000 0 0x4000>;
1473 reg-names = "se";
1474 clock-names = "se";
1475 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = "tx", "rx";
1479 pinctrl-names = "default";
1480 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequency = <50000000>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 status = "disabled";
1486 };
1487
1488 i2c16: i2c@94000 {
1489 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00094000 0 0x4000>;
1491 clock-names = "se";
1492 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = "tx", "rx";
1496 pinctrl-names = "default";
1497 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1501 status = "disabled";
1502 };
1503
1504 spi16: spi@a94000 {
1505 compatible = "qcom,geni-spi";
1506 reg = <0 0x00a94000 0 0x4000>;
1507 reg-names = "se";
1508 clock-names = "se";
1509 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = "tx", "rx";
1513 pinctrl-names = "default";
1514 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequency = <50000000>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 status = "disabled";
1520 };
1521 };
1522
1523 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1525 reg = <0 0x00c00000 0 0x60000>;
1526 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>;
1540 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>;
1543 status = "disabled";
1544 };
1545
1546 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549
1550 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>;
1555 #size-cells = <2>;
1556 ranges;
1557 status = "disabled";
1558
1559 i2c17: i2c@c80000 {
1560 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = "se";
1563 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = "tx", "rx";
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1572 status = "disabled";
1573 };
1574
1575 spi17: spi@c80000 {
1576 compatible = "qcom,geni-spi";
1577 reg = <0 0x00c80000 0 0x4000>;
1578 reg-names = "se";
1579 clock-names = "se";
1580 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = "tx", "rx";
1584 pinctrl-names = "default";
1585 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequency = <50000000>;
1588 #address-cells = <1>;
1589 #size-cells = <0>;
1590 status = "disabled";
1591 };
1592
1593 i2c18: i2c@c84000 {
1594 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = "se";
1597 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = "tx", "rx";
1601 pinctrl-names = "default";
1602 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cells = <1>;
1605 #size-cells = <0>;
1606 status = "disabled";
1607 };
1608
1609 spi18: spi@c84000 {
1610 compatible = "qcom,geni-spi";
1611 reg = <0 0x00c84000 0 0x4000>;
1612 reg-names = "se";
1613 clock-names = "se";
1614 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = "tx", "rx";
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequency = <50000000>;
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1624 status = "disabled";
1625 };
1626
1627 i2c19: i2c@c88000 {
1628 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = "se";
1631 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = "tx", "rx";
1635 pinctrl-names = "default";
1636 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1640 status = "disabled";
1641 };
1642
1643 spi19: spi@c88000 {
1644 compatible = "qcom,geni-spi";
1645 reg = <0 0x00c88000 0 0x4000>;
1646 reg-names = "se";
1647 clock-names = "se";
1648 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = "tx", "rx";
1652 pinctrl-names = "default";
1653 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequency = <50000000>;
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1658 status = "disabled";
1659 };
1660
1661 i2c13: i2c@c8c000 {
1662 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = "se";
1665 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = "tx", "rx";
1669 pinctrl-names = "default";
1670 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cells = <1>;
1673 #size-cells = <0>;
1674 status = "disabled";
1675 };
1676
1677 spi13: spi@c8c000 {
1678 compatible = "qcom,geni-spi";
1679 reg = <0 0x00c8c000 0 0x4000>;
1680 reg-names = "se";
1681 clock-names = "se";
1682 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = "tx", "rx";
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequency = <50000000>;
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1692 status = "disabled";
1693 };
1694
1695 i2c14: i2c@c90000 {
1696 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = "se";
1699 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = "tx", "rx";
1703 pinctrl-names = "default";
1704 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1708 status = "disabled";
1709 };
1710
1711 spi14: spi@c90000 {
1712 compatible = "qcom,geni-spi";
1713 reg = <0 0x00c90000 0 0x4000>;
1714 reg-names = "se";
1715 clock-names = "se";
1716 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = "tx", "rx";
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequency = <50000000>;
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1726 status = "disabled";
1727 };
1728
1729 i2c15: i2c@c94000 {
1730 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = "se";
1733 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = "tx", "rx";
1737 pinctrl-names = "default";
1738 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1742 status = "disabled";
1743 };
1744
1745 spi15: spi@c94000 {
1746 compatible = "qcom,geni-spi";
1747 reg = <0 0x00c94000 0 0x4000>;
1748 reg-names = "se";
1749 clock-names = "se";
1750 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = "tx", "rx";
1754 pinctrl-names = "default";
1755 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequency = <50000000>;
1758 #address-cells = <1>;
1759 #size-cells = <0>;
1760 status = "disabled";
1761 };
1762 };
1763
1764 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = <2>;
1768 qcom,bcm-voters = <&apps_bcm_voter>;
1769 };
1770
1771 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = <2>;
1775 qcom,bcm-voters = <&apps_bcm_voter>;
1776 };
1777
1778 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = <2>;
1782 qcom,bcm-voters = <&apps_bcm_voter>;
1783 };
1784
1785 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = <2>;
1789 qcom,bcm-voters = <&apps_bcm_voter>;
1790 };
1791
1792 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = <2>;
1796 qcom,bcm-voters = <&apps_bcm_voter>;
1797 };
1798
1799 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = <2>;
1803 qcom,bcm-voters = <&apps_bcm_voter>;
1804 };
1805
1806 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = <2>;
1810 qcom,bcm-voters = <&apps_bcm_voter>;
1811 };
1812
1813 system-cache-controller@9200000 {
1814 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1816 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1817 <0 0x09600000 0 0x50000>;
1818 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1819 "llcc3_base", "llcc_broadcast_base";
1820 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 };
1822
1823 dma@10a2000 {
1824 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1825 reg = <0x0 0x010a2000 0x0 0x1000>,
1826 <0x0 0x010ad000 0x0 0x3000>;
1827 };
1828
1829 pcie0: pcie@1c00000 {
1830 compatible = "qcom,pcie-sm8150";
1831 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci";
1838 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xff>;
1840 num-lanes = <1>;
1841
1842 #address-cells = <3>;
1843 #size-cells = <2>;
1844
1845 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847
1848 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1856 interrupt-names = "msi0",
1857 "msi1",
1858 "msi2",
1859 "msi3",
1860 "msi4",
1861 "msi5",
1862 "msi6",
1863 "msi7";
1864 #interrupt-cells = <1>;
1865 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870
1871 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1878 <&rpmhcc RPMH_CXO_CLK>;
1879 clock-names = "pipe",
1880 "aux",
1881 "cfg",
1882 "bus_master",
1883 "bus_slave",
1884 "slave_q2a",
1885 "tbu",
1886 "ref";
1887
1888 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &apps_smmu 0x1d81 0x1>;
1890
1891 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci";
1893
1894 power-domains = <&gcc PCIE_0_GDSC>;
1895
1896 phys = <&pcie0_phy>;
1897 phy-names = "pciephy";
1898
1899 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901
1902 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_default_state>;
1904
1905 status = "disabled";
1906
1907 pcie@0 {
1908 device_type = "pci";
1909 reg = <0x0 0x0 0x0 0x0 0x0>;
1910 bus-range = <0x01 0xff>;
1911
1912 #address-cells = <3>;
1913 #size-cells = <2>;
1914 ranges;
1915 };
1916 };
1917
1918 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 0x1000>;
1921 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1924 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1925 <&gcc GCC_PCIE_0_PIPE_CLK>;
1926 clock-names = "aux",
1927 "cfg_ahb",
1928 "ref",
1929 "refgen",
1930 "pipe";
1931
1932 clock-output-names = "pcie_0_pipe_clk";
1933 #clock-cells = <0>;
1934
1935 #phy-cells = <0>;
1936
1937 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy";
1939
1940 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates = <100000000>;
1942
1943 status = "disabled";
1944 };
1945
1946 pcie1: pcie@1c08000 {
1947 compatible = "qcom,pcie-sm8150";
1948 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci";
1955 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xff>;
1957 num-lanes = <2>;
1958
1959 #address-cells = <3>;
1960 #size-cells = <2>;
1961
1962 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964
1965 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1972 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1973 interrupt-names = "msi0",
1974 "msi1",
1975 "msi2",
1976 "msi3",
1977 "msi4",
1978 "msi5",
1979 "msi6",
1980 "msi7";
1981 #interrupt-cells = <1>;
1982 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987
1988 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1995 <&rpmhcc RPMH_CXO_CLK>;
1996 clock-names = "pipe",
1997 "aux",
1998 "cfg",
1999 "bus_master",
2000 "bus_slave",
2001 "slave_q2a",
2002 "tbu",
2003 "ref";
2004
2005 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates = <19200000>;
2007
2008 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &apps_smmu 0x1e01 0x1>;
2010
2011 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci";
2013
2014 power-domains = <&gcc PCIE_1_GDSC>;
2015
2016 phys = <&pcie1_phy>;
2017 phy-names = "pciephy";
2018
2019 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021
2022 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_default_state>;
2024
2025 status = "disabled";
2026
2027 pcie@0 {
2028 device_type = "pci";
2029 reg = <0x0 0x0 0x0 0x0 0x0>;
2030 bus-range = <0x01 0xff>;
2031
2032 #address-cells = <3>;
2033 #size-cells = <2>;
2034 ranges;
2035 };
2036 };
2037
2038 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 0x1000>;
2041 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2044 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2045 <&gcc GCC_PCIE_1_PIPE_CLK>;
2046 clock-names = "aux",
2047 "cfg_ahb",
2048 "ref",
2049 "refgen",
2050 "pipe";
2051
2052 clock-output-names = "pcie_1_pipe_clk";
2053 #clock-cells = <0>;
2054
2055 #phy-cells = <0>;
2056
2057 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy";
2059
2060 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates = <100000000>;
2062
2063 status = "disabled";
2064 };
2065
2066 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy>;
2074 phy-names = "ufsphy";
2075 lanes-per-direction = <2>;
2076 #reset-cells = <1>;
2077 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst";
2079
2080 iommus = <&apps_smmu 0x300 0>;
2081
2082 clock-names =
2083 "core_clk",
2084 "bus_aggr_clk",
2085 "iface_clk",
2086 "core_clk_unipro",
2087 "ref_clk",
2088 "tx_lane0_sync_clk",
2089 "rx_lane0_sync_clk",
2090 "rx_lane1_sync_clk",
2091 "ice_core_clk";
2092 clocks =
2093 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz =
2103 <37500000 300000000>,
2104 <0 0>,
2105 <0 0>,
2106 <37500000 300000000>,
2107 <0 0>,
2108 <0 0>,
2109 <0 0>,
2110 <0 0>,
2111 <0 300000000>;
2112
2113 status = "disabled";
2114 };
2115
2116 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 0x1000>;
2119
2120 clocks = <&rpmhcc RPMH_CXO_CLK>,
2121 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2122 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
2123 clock-names = "ref",
2124 "ref_aux",
2125 "qref";
2126
2127 power-domains = <&gcc UFS_PHY_GDSC>;
2128
2129 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy";
2131
2132 #phy-cells = <0>;
2133
2134 status = "disabled";
2135 };
2136
2137 cryptobam: dma-controller@1dc4000 {
2138 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2139 reg = <0 0x01dc4000 0 0x24000>;
2140 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2141 #dma-cells = <1>;
2142 qcom,ee = <0>;
2143 qcom,controlled-remotely;
2144 num-channels = <8>;
2145 qcom,num-ees = <2>;
2146 iommus = <&apps_smmu 0x502 0x0641>,
2147 <&apps_smmu 0x504 0x0011>,
2148 <&apps_smmu 0x506 0x0011>,
2149 <&apps_smmu 0x508 0x0011>,
2150 <&apps_smmu 0x512 0x0000>;
2151 };
2152
2153 crypto: crypto@1dfa000 {
2154 compatible = "qcom,sm8150-qce", "qcom,qce";
2155 reg = <0 0x01dfa000 0 0x6000>;
2156 dmas = <&cryptobam 4>, <&cryptobam 5>;
2157 dma-names = "rx", "tx";
2158 iommus = <&apps_smmu 0x502 0x0641>,
2159 <&apps_smmu 0x504 0x0011>,
2160 <&apps_smmu 0x506 0x0011>,
2161 <&apps_smmu 0x508 0x0011>,
2162 <&apps_smmu 0x512 0x0000>;
2163 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2164 interconnect-names = "memory";
2165 };
2166
2167 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tcsr-mutex";
2169 reg = <0x0 0x01f40000 0x0 0x20000>;
2170 #hwlock-cells = <1>;
2171 };
2172
2173 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm8150-tcsr", "syscon";
2175 reg = <0x0 0x01f60000 0x0 0x20000>;
2176 };
2177
2178 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 0x0 0x4040>;
2181
2182 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wdog", "fatal", "ready",
2188 "handover", "stop-ack";
2189
2190 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo";
2192
2193 power-domains = <&rpmhpd SM8150_LCX>,
2194 <&rpmhpd SM8150_LMX>;
2195 power-domain-names = "lcx", "lmx";
2196
2197 memory-region = <&slpi_mem>;
2198
2199 qcom,qmp = <&aoss_qmp>;
2200
2201 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names = "stop";
2203
2204 status = "disabled";
2205
2206 glink-edge {
2207 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps";
2209 qcom,remote-pid = <3>;
2210 mboxes = <&apss_shared 24>;
2211
2212 fastrpc {
2213 compatible = "qcom,fastrpc";
2214 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label = "sdsp";
2216 qcom,non-secure-domain;
2217 #address-cells = <1>;
2218 #size-cells = <0>;
2219
2220 compute-cb@1 {
2221 compatible = "qcom,fastrpc-compute-cb";
2222 reg = <1>;
2223 iommus = <&apps_smmu 0x05a1 0x0>;
2224 };
2225
2226 compute-cb@2 {
2227 compatible = "qcom,fastrpc-compute-cb";
2228 reg = <2>;
2229 iommus = <&apps_smmu 0x05a2 0x0>;
2230 };
2231
2232 compute-cb@3 {
2233 compatible = "qcom,fastrpc-compute-cb";
2234 reg = <3>;
2235 iommus = <&apps_smmu 0x05a3 0x0>;
2236 /* note: shared-cb = <4> in downstream */
2237 };
2238 };
2239 };
2240 };
2241
2242 gpu: gpu@2c00000 {
2243 compatible = "qcom,adreno-640.1", "qcom,adreno";
2244 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0_reg_memory";
2246
2247 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248
2249 iommus = <&adreno_smmu 0 0x401>;
2250
2251 operating-points-v2 = <&gpu_opp_table>;
2252
2253 qcom,gmu = <&gmu>;
2254
2255 nvmem-cells = <&gpu_speed_bin>;
2256 nvmem-cell-names = "speed_bin";
2257 #cooling-cells = <2>;
2258
2259 status = "disabled";
2260
2261 zap-shader {
2262 memory-region = <&gpu_mem>;
2263 };
2264
2265 gpu_opp_table: opp-table {
2266 compatible = "operating-points-v2";
2267
2268 opp-675000000 {
2269 opp-hz = /bits/ 64 <675000000>;
2270 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-supported-hw = <0x2>;
2272 };
2273
2274 opp-585000000 {
2275 opp-hz = /bits/ 64 <585000000>;
2276 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-supported-hw = <0x3>;
2278 };
2279
2280 opp-499200000 {
2281 opp-hz = /bits/ 64 <499200000>;
2282 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-supported-hw = <0x3>;
2284 };
2285
2286 opp-427000000 {
2287 opp-hz = /bits/ 64 <427000000>;
2288 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-supported-hw = <0x3>;
2290 };
2291
2292 opp-345000000 {
2293 opp-hz = /bits/ 64 <345000000>;
2294 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-supported-hw = <0x3>;
2296 };
2297
2298 opp-257000000 {
2299 opp-hz = /bits/ 64 <257000000>;
2300 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-supported-hw = <0x3>;
2302 };
2303 };
2304 };
2305
2306 gmu: gmu@2c6a000 {
2307 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308
2309 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313
2314 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hfi", "gmu";
2317
2318 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324
2325 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = "cx", "gx";
2328
2329 iommus = <&adreno_smmu 5 0x400>;
2330
2331 operating-points-v2 = <&gmu_opp_table>;
2332
2333 status = "disabled";
2334
2335 gmu_opp_table: opp-table {
2336 compatible = "operating-points-v2";
2337
2338 opp-200000000 {
2339 opp-hz = /bits/ 64 <200000000>;
2340 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 };
2342 };
2343 };
2344
2345 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcxo",
2352 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>;
2355 #reset-cells = <1>;
2356 #power-domain-cells = <1>;
2357 };
2358
2359 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2361 "qcom,smmu-500", "arm,mmu-500";
2362 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>;
2364 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", "bus", "iface";
2378
2379 power-domains = <&gpucc GPU_CX_GDSC>;
2380 };
2381
2382 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller;
2392 #gpio-cells = <2>;
2393 interrupt-controller;
2394 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc>;
2396
2397 qup_i2c0_default: qup-i2c0-default-state {
2398 pins = "gpio0", "gpio1";
2399 function = "qup0";
2400 drive-strength = <0x02>;
2401 bias-disable;
2402 };
2403
2404 qup_spi0_default: qup-spi0-default-state {
2405 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "qup0";
2407 drive-strength = <6>;
2408 bias-disable;
2409 };
2410
2411 qup_i2c1_default: qup-i2c1-default-state {
2412 pins = "gpio114", "gpio115";
2413 function = "qup1";
2414 drive-strength = <2>;
2415 bias-disable;
2416 };
2417
2418 qup_spi1_default: qup-spi1-default-state {
2419 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "qup1";
2421 drive-strength = <6>;
2422 bias-disable;
2423 };
2424
2425 qup_i2c2_default: qup-i2c2-default-state {
2426 pins = "gpio126", "gpio127";
2427 function = "qup2";
2428 drive-strength = <2>;
2429 bias-disable;
2430 };
2431
2432 qup_spi2_default: qup-spi2-default-state {
2433 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "qup2";
2435 drive-strength = <6>;
2436 bias-disable;
2437 };
2438
2439 qup_i2c3_default: qup-i2c3-default-state {
2440 pins = "gpio144", "gpio145";
2441 function = "qup3";
2442 drive-strength = <2>;
2443 bias-disable;
2444 };
2445
2446 qup_spi3_default: qup-spi3-default-state {
2447 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "qup3";
2449 drive-strength = <6>;
2450 bias-disable;
2451 };
2452
2453 qup_i2c4_default: qup-i2c4-default-state {
2454 pins = "gpio51", "gpio52";
2455 function = "qup4";
2456 drive-strength = <2>;
2457 bias-disable;
2458 };
2459
2460 qup_spi4_default: qup-spi4-default-state {
2461 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "qup4";
2463 drive-strength = <6>;
2464 bias-disable;
2465 };
2466
2467 qup_i2c5_default: qup-i2c5-default-state {
2468 pins = "gpio121", "gpio122";
2469 function = "qup5";
2470 drive-strength = <2>;
2471 bias-disable;
2472 };
2473
2474 qup_spi5_default: qup-spi5-default-state {
2475 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "qup5";
2477 drive-strength = <6>;
2478 bias-disable;
2479 };
2480
2481 qup_i2c6_default: qup-i2c6-default-state {
2482 pins = "gpio6", "gpio7";
2483 function = "qup6";
2484 drive-strength = <2>;
2485 bias-disable;
2486 };
2487
2488 qup_spi6_default: qup-spi6-default-state {
2489 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "qup6";
2491 drive-strength = <6>;
2492 bias-disable;
2493 };
2494
2495 qup_i2c7_default: qup-i2c7-default-state {
2496 pins = "gpio98", "gpio99";
2497 function = "qup7";
2498 drive-strength = <2>;
2499 bias-disable;
2500 };
2501
2502 qup_spi7_default: qup-spi7-default-state {
2503 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "qup7";
2505 drive-strength = <6>;
2506 bias-disable;
2507 };
2508
2509 qup_i2c8_default: qup-i2c8-default-state {
2510 pins = "gpio88", "gpio89";
2511 function = "qup8";
2512 drive-strength = <2>;
2513 bias-disable;
2514 };
2515
2516 qup_spi8_default: qup-spi8-default-state {
2517 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "qup8";
2519 drive-strength = <6>;
2520 bias-disable;
2521 };
2522
2523 qup_i2c9_default: qup-i2c9-default-state {
2524 pins = "gpio39", "gpio40";
2525 function = "qup9";
2526 drive-strength = <2>;
2527 bias-disable;
2528 };
2529
2530 qup_spi9_default: qup-spi9-default-state {
2531 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "qup9";
2533 drive-strength = <6>;
2534 bias-disable;
2535 };
2536
2537 qup_uart9_default: qup-uart9-default-state {
2538 pins = "gpio41", "gpio42";
2539 function = "qup9";
2540 drive-strength = <2>;
2541 bias-disable;
2542 };
2543
2544 qup_i2c10_default: qup-i2c10-default-state {
2545 pins = "gpio9", "gpio10";
2546 function = "qup10";
2547 drive-strength = <2>;
2548 bias-disable;
2549 };
2550
2551 qup_spi10_default: qup-spi10-default-state {
2552 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "qup10";
2554 drive-strength = <6>;
2555 bias-disable;
2556 };
2557
2558 qup_i2c11_default: qup-i2c11-default-state {
2559 pins = "gpio94", "gpio95";
2560 function = "qup11";
2561 drive-strength = <2>;
2562 bias-disable;
2563 };
2564
2565 qup_spi11_default: qup-spi11-default-state {
2566 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "qup11";
2568 drive-strength = <6>;
2569 bias-disable;
2570 };
2571
2572 qup_i2c12_default: qup-i2c12-default-state {
2573 pins = "gpio83", "gpio84";
2574 function = "qup12";
2575 drive-strength = <2>;
2576 bias-disable;
2577 };
2578
2579 qup_spi12_default: qup-spi12-default-state {
2580 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "qup12";
2582 drive-strength = <6>;
2583 bias-disable;
2584 };
2585
2586 qup_i2c13_default: qup-i2c13-default-state {
2587 pins = "gpio43", "gpio44";
2588 function = "qup13";
2589 drive-strength = <2>;
2590 bias-disable;
2591 };
2592
2593 qup_spi13_default: qup-spi13-default-state {
2594 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "qup13";
2596 drive-strength = <6>;
2597 bias-disable;
2598 };
2599
2600 qup_i2c14_default: qup-i2c14-default-state {
2601 pins = "gpio47", "gpio48";
2602 function = "qup14";
2603 drive-strength = <2>;
2604 bias-disable;
2605 };
2606
2607 qup_spi14_default: qup-spi14-default-state {
2608 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "qup14";
2610 drive-strength = <6>;
2611 bias-disable;
2612 };
2613
2614 qup_i2c15_default: qup-i2c15-default-state {
2615 pins = "gpio27", "gpio28";
2616 function = "qup15";
2617 drive-strength = <2>;
2618 bias-disable;
2619 };
2620
2621 qup_spi15_default: qup-spi15-default-state {
2622 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "qup15";
2624 drive-strength = <6>;
2625 bias-disable;
2626 };
2627
2628 qup_i2c16_default: qup-i2c16-default-state {
2629 pins = "gpio86", "gpio85";
2630 function = "qup16";
2631 drive-strength = <2>;
2632 bias-disable;
2633 };
2634
2635 qup_spi16_default: qup-spi16-default-state {
2636 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "qup16";
2638 drive-strength = <6>;
2639 bias-disable;
2640 };
2641
2642 qup_i2c17_default: qup-i2c17-default-state {
2643 pins = "gpio55", "gpio56";
2644 function = "qup17";
2645 drive-strength = <2>;
2646 bias-disable;
2647 };
2648
2649 qup_spi17_default: qup-spi17-default-state {
2650 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "qup17";
2652 drive-strength = <6>;
2653 bias-disable;
2654 };
2655
2656 qup_i2c18_default: qup-i2c18-default-state {
2657 pins = "gpio23", "gpio24";
2658 function = "qup18";
2659 drive-strength = <2>;
2660 bias-disable;
2661 };
2662
2663 qup_spi18_default: qup-spi18-default-state {
2664 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "qup18";
2666 drive-strength = <6>;
2667 bias-disable;
2668 };
2669
2670 qup_i2c19_default: qup-i2c19-default-state {
2671 pins = "gpio57", "gpio58";
2672 function = "qup19";
2673 drive-strength = <2>;
2674 bias-disable;
2675 };
2676
2677 qup_spi19_default: qup-spi19-default-state {
2678 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "qup19";
2680 drive-strength = <6>;
2681 bias-disable;
2682 };
2683
2684 pcie0_default_state: pcie0-default-state {
2685 perst-pins {
2686 pins = "gpio35";
2687 function = "gpio";
2688 drive-strength = <2>;
2689 bias-pull-down;
2690 };
2691
2692 clkreq-pins {
2693 pins = "gpio36";
2694 function = "pci_e0";
2695 drive-strength = <2>;
2696 bias-pull-up;
2697 };
2698
2699 wake-pins {
2700 pins = "gpio37";
2701 function = "gpio";
2702 drive-strength = <2>;
2703 bias-pull-up;
2704 };
2705 };
2706
2707 pcie1_default_state: pcie1-default-state {
2708 perst-pins {
2709 pins = "gpio102";
2710 function = "gpio";
2711 drive-strength = <2>;
2712 bias-pull-down;
2713 };
2714
2715 clkreq-pins {
2716 pins = "gpio103";
2717 function = "pci_e1";
2718 drive-strength = <2>;
2719 bias-pull-up;
2720 };
2721
2722 wake-pins {
2723 pins = "gpio104";
2724 function = "gpio";
2725 drive-strength = <2>;
2726 bias-pull-up;
2727 };
2728 };
2729 };
2730
2731 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 0x0 0x4040>;
2734
2735 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "stop-ack", "shutdown-ack";
2743
2744 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo";
2746
2747 power-domains = <&rpmhpd SM8150_CX>,
2748 <&rpmhpd SM8150_MSS>;
2749 power-domain-names = "cx", "mss";
2750
2751 memory-region = <&mpss_mem>;
2752
2753 qcom,qmp = <&aoss_qmp>;
2754
2755 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names = "stop";
2757
2758 status = "disabled";
2759
2760 glink-edge {
2761 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "modem";
2763 qcom,remote-pid = <1>;
2764 mboxes = <&apss_shared 12>;
2765 };
2766 };
2767
2768 stm@6002000 {
2769 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base", "stm-stimulus-base";
2773
2774 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pclk";
2776
2777 out-ports {
2778 port {
2779 stm_out: endpoint {
2780 remote-endpoint = <&funnel0_in7>;
2781 };
2782 };
2783 };
2784 };
2785
2786 funnel@6041000 {
2787 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 0x1000>;
2789
2790 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pclk";
2792
2793 out-ports {
2794 port {
2795 funnel0_out: endpoint {
2796 remote-endpoint = <&merge_funnel_in0>;
2797 };
2798 };
2799 };
2800
2801 in-ports {
2802 #address-cells = <1>;
2803 #size-cells = <0>;
2804
2805 port@7 {
2806 reg = <7>;
2807 funnel0_in7: endpoint {
2808 remote-endpoint = <&stm_out>;
2809 };
2810 };
2811 };
2812 };
2813
2814 funnel@6042000 {
2815 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 0x1000>;
2817
2818 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pclk";
2820
2821 out-ports {
2822 port {
2823 funnel1_out: endpoint {
2824 remote-endpoint = <&merge_funnel_in1>;
2825 };
2826 };
2827 };
2828
2829 in-ports {
2830 #address-cells = <1>;
2831 #size-cells = <0>;
2832
2833 port@4 {
2834 reg = <4>;
2835 funnel1_in4: endpoint {
2836 remote-endpoint = <&swao_replicator_out>;
2837 };
2838 };
2839 };
2840 };
2841
2842 funnel@6043000 {
2843 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 0x1000>;
2845
2846 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pclk";
2848
2849 out-ports {
2850 port {
2851 funnel2_out: endpoint {
2852 remote-endpoint = <&merge_funnel_in2>;
2853 };
2854 };
2855 };
2856
2857 in-ports {
2858 #address-cells = <1>;
2859 #size-cells = <0>;
2860
2861 port@2 {
2862 reg = <2>;
2863 funnel2_in2: endpoint {
2864 remote-endpoint = <&apss_merge_funnel_out>;
2865 };
2866 };
2867 };
2868 };
2869
2870 funnel@6045000 {
2871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 0x1000>;
2873
2874 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pclk";
2876
2877 out-ports {
2878 port {
2879 merge_funnel_out: endpoint {
2880 remote-endpoint = <&etf_in>;
2881 };
2882 };
2883 };
2884
2885 in-ports {
2886 #address-cells = <1>;
2887 #size-cells = <0>;
2888
2889 port@0 {
2890 reg = <0>;
2891 merge_funnel_in0: endpoint {
2892 remote-endpoint = <&funnel0_out>;
2893 };
2894 };
2895
2896 port@1 {
2897 reg = <1>;
2898 merge_funnel_in1: endpoint {
2899 remote-endpoint = <&funnel1_out>;
2900 };
2901 };
2902
2903 port@2 {
2904 reg = <2>;
2905 merge_funnel_in2: endpoint {
2906 remote-endpoint = <&funnel2_out>;
2907 };
2908 };
2909 };
2910 };
2911
2912 replicator@6046000 {
2913 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 0x1000>;
2915
2916 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pclk";
2918
2919 out-ports {
2920 #address-cells = <1>;
2921 #size-cells = <0>;
2922
2923 port@0 {
2924 reg = <0>;
2925 replicator_out0: endpoint {
2926 remote-endpoint = <&etr_in>;
2927 };
2928 };
2929
2930 port@1 {
2931 reg = <1>;
2932 replicator_out1: endpoint {
2933 remote-endpoint = <&replicator1_in>;
2934 };
2935 };
2936 };
2937
2938 in-ports {
2939 port {
2940 replicator_in0: endpoint {
2941 remote-endpoint = <&etf_out>;
2942 };
2943 };
2944 };
2945 };
2946
2947 etf@6047000 {
2948 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 0x1000>;
2950
2951 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pclk";
2953
2954 out-ports {
2955 port {
2956 etf_out: endpoint {
2957 remote-endpoint = <&replicator_in0>;
2958 };
2959 };
2960 };
2961
2962 in-ports {
2963 port {
2964 etf_in: endpoint {
2965 remote-endpoint = <&merge_funnel_out>;
2966 };
2967 };
2968 };
2969 };
2970
2971 etr@6048000 {
2972 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 0x05e0 0x0>;
2975
2976 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pclk";
2978 arm,scatter-gather;
2979
2980 in-ports {
2981 port {
2982 etr_in: endpoint {
2983 remote-endpoint = <&replicator_out0>;
2984 };
2985 };
2986 };
2987 };
2988
2989 replicator@604a000 {
2990 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 0x1000>;
2992
2993 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pclk";
2995
2996 out-ports {
2997 #address-cells = <1>;
2998 #size-cells = <0>;
2999
3000 port@1 {
3001 reg = <1>;
3002 replicator1_out: endpoint {
3003 remote-endpoint = <&swao_funnel_in>;
3004 };
3005 };
3006 };
3007
3008 in-ports {
3009
3010 port {
3011 replicator1_in: endpoint {
3012 remote-endpoint = <&replicator_out1>;
3013 };
3014 };
3015 };
3016 };
3017
3018 funnel@6b08000 {
3019 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 0x1000>;
3021
3022 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pclk";
3024
3025 out-ports {
3026 port {
3027 swao_funnel_out: endpoint {
3028 remote-endpoint = <&swao_etf_in>;
3029 };
3030 };
3031 };
3032
3033 in-ports {
3034 #address-cells = <1>;
3035 #size-cells = <0>;
3036
3037 port@6 {
3038 reg = <6>;
3039 swao_funnel_in: endpoint {
3040 remote-endpoint = <&replicator1_out>;
3041 };
3042 };
3043 };
3044 };
3045
3046 etf@6b09000 {
3047 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 0x1000>;
3049
3050 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pclk";
3052
3053 out-ports {
3054 port {
3055 swao_etf_out: endpoint {
3056 remote-endpoint = <&swao_replicator_in>;
3057 };
3058 };
3059 };
3060
3061 in-ports {
3062 port {
3063 swao_etf_in: endpoint {
3064 remote-endpoint = <&swao_funnel_out>;
3065 };
3066 };
3067 };
3068 };
3069
3070 replicator@6b0a000 {
3071 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 0x1000>;
3073
3074 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pclk";
3076 qcom,replicator-loses-context;
3077
3078 out-ports {
3079 port {
3080 swao_replicator_out: endpoint {
3081 remote-endpoint = <&funnel1_in4>;
3082 };
3083 };
3084 };
3085
3086 in-ports {
3087 port {
3088 swao_replicator_in: endpoint {
3089 remote-endpoint = <&swao_etf_out>;
3090 };
3091 };
3092 };
3093 };
3094
3095 etm@7040000 {
3096 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 0x1000>;
3098
3099 cpu = <&CPU0>;
3100
3101 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pclk";
3103 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up;
3105
3106 out-ports {
3107 port {
3108 etm0_out: endpoint {
3109 remote-endpoint = <&apss_funnel_in0>;
3110 };
3111 };
3112 };
3113 };
3114
3115 etm@7140000 {
3116 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 0x1000>;
3118
3119 cpu = <&CPU1>;
3120
3121 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pclk";
3123 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up;
3125
3126 out-ports {
3127 port {
3128 etm1_out: endpoint {
3129 remote-endpoint = <&apss_funnel_in1>;
3130 };
3131 };
3132 };
3133 };
3134
3135 etm@7240000 {
3136 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 0x1000>;
3138
3139 cpu = <&CPU2>;
3140
3141 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pclk";
3143 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up;
3145
3146 out-ports {
3147 port {
3148 etm2_out: endpoint {
3149 remote-endpoint = <&apss_funnel_in2>;
3150 };
3151 };
3152 };
3153 };
3154
3155 etm@7340000 {
3156 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 0x1000>;
3158
3159 cpu = <&CPU3>;
3160
3161 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pclk";
3163 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up;
3165
3166 out-ports {
3167 port {
3168 etm3_out: endpoint {
3169 remote-endpoint = <&apss_funnel_in3>;
3170 };
3171 };
3172 };
3173 };
3174
3175 etm@7440000 {
3176 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 0x1000>;
3178
3179 cpu = <&CPU4>;
3180
3181 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pclk";
3183 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up;
3185
3186 out-ports {
3187 port {
3188 etm4_out: endpoint {
3189 remote-endpoint = <&apss_funnel_in4>;
3190 };
3191 };
3192 };
3193 };
3194
3195 etm@7540000 {
3196 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 0x1000>;
3198
3199 cpu = <&CPU5>;
3200
3201 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pclk";
3203 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up;
3205
3206 out-ports {
3207 port {
3208 etm5_out: endpoint {
3209 remote-endpoint = <&apss_funnel_in5>;
3210 };
3211 };
3212 };
3213 };
3214
3215 etm@7640000 {
3216 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 0x1000>;
3218
3219 cpu = <&CPU6>;
3220
3221 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pclk";
3223 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up;
3225
3226 out-ports {
3227 port {
3228 etm6_out: endpoint {
3229 remote-endpoint = <&apss_funnel_in6>;
3230 };
3231 };
3232 };
3233 };
3234
3235 etm@7740000 {
3236 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 0x1000>;
3238
3239 cpu = <&CPU7>;
3240
3241 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pclk";
3243 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up;
3245
3246 out-ports {
3247 port {
3248 etm7_out: endpoint {
3249 remote-endpoint = <&apss_funnel_in7>;
3250 };
3251 };
3252 };
3253 };
3254
3255 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 0x1000>;
3258
3259 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pclk";
3261
3262 out-ports {
3263 port {
3264 apss_funnel_out: endpoint {
3265 remote-endpoint = <&apss_merge_funnel_in>;
3266 };
3267 };
3268 };
3269
3270 in-ports {
3271 #address-cells = <1>;
3272 #size-cells = <0>;
3273
3274 port@0 {
3275 reg = <0>;
3276 apss_funnel_in0: endpoint {
3277 remote-endpoint = <&etm0_out>;
3278 };
3279 };
3280
3281 port@1 {
3282 reg = <1>;
3283 apss_funnel_in1: endpoint {
3284 remote-endpoint = <&etm1_out>;
3285 };
3286 };
3287
3288 port@2 {
3289 reg = <2>;
3290 apss_funnel_in2: endpoint {
3291 remote-endpoint = <&etm2_out>;
3292 };
3293 };
3294
3295 port@3 {
3296 reg = <3>;
3297 apss_funnel_in3: endpoint {
3298 remote-endpoint = <&etm3_out>;
3299 };
3300 };
3301
3302 port@4 {
3303 reg = <4>;
3304 apss_funnel_in4: endpoint {
3305 remote-endpoint = <&etm4_out>;
3306 };
3307 };
3308
3309 port@5 {
3310 reg = <5>;
3311 apss_funnel_in5: endpoint {
3312 remote-endpoint = <&etm5_out>;
3313 };
3314 };
3315
3316 port@6 {
3317 reg = <6>;
3318 apss_funnel_in6: endpoint {
3319 remote-endpoint = <&etm6_out>;
3320 };
3321 };
3322
3323 port@7 {
3324 reg = <7>;
3325 apss_funnel_in7: endpoint {
3326 remote-endpoint = <&etm7_out>;
3327 };
3328 };
3329 };
3330 };
3331
3332 funnel@7810000 {
3333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 0x1000>;
3335
3336 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pclk";
3338
3339 out-ports {
3340 port {
3341 apss_merge_funnel_out: endpoint {
3342 remote-endpoint = <&funnel2_in2>;
3343 };
3344 };
3345 };
3346
3347 in-ports {
3348 port {
3349 apss_merge_funnel_in: endpoint {
3350 remote-endpoint = <&apss_funnel_out>;
3351 };
3352 };
3353 };
3354 };
3355
3356 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 0x0 0x4040>;
3359
3360 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wdog", "fatal", "ready",
3366 "handover", "stop-ack";
3367
3368 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo";
3370
3371 power-domains = <&rpmhpd SM8150_CX>;
3372
3373 memory-region = <&cdsp_mem>;
3374
3375 qcom,qmp = <&aoss_qmp>;
3376
3377 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names = "stop";
3379
3380 status = "disabled";
3381
3382 glink-edge {
3383 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp";
3385 qcom,remote-pid = <5>;
3386 mboxes = <&apss_shared 4>;
3387
3388 fastrpc {
3389 compatible = "qcom,fastrpc";
3390 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label = "cdsp";
3392 qcom,non-secure-domain;
3393 #address-cells = <1>;
3394 #size-cells = <0>;
3395
3396 compute-cb@1 {
3397 compatible = "qcom,fastrpc-compute-cb";
3398 reg = <1>;
3399 iommus = <&apps_smmu 0x1001 0x0460>;
3400 };
3401
3402 compute-cb@2 {
3403 compatible = "qcom,fastrpc-compute-cb";
3404 reg = <2>;
3405 iommus = <&apps_smmu 0x1002 0x0460>;
3406 };
3407
3408 compute-cb@3 {
3409 compatible = "qcom,fastrpc-compute-cb";
3410 reg = <3>;
3411 iommus = <&apps_smmu 0x1003 0x0460>;
3412 };
3413
3414 compute-cb@4 {
3415 compatible = "qcom,fastrpc-compute-cb";
3416 reg = <4>;
3417 iommus = <&apps_smmu 0x1004 0x0460>;
3418 };
3419
3420 compute-cb@5 {
3421 compatible = "qcom,fastrpc-compute-cb";
3422 reg = <5>;
3423 iommus = <&apps_smmu 0x1005 0x0460>;
3424 };
3425
3426 compute-cb@6 {
3427 compatible = "qcom,fastrpc-compute-cb";
3428 reg = <6>;
3429 iommus = <&apps_smmu 0x1006 0x0460>;
3430 };
3431
3432 compute-cb@7 {
3433 compatible = "qcom,fastrpc-compute-cb";
3434 reg = <7>;
3435 iommus = <&apps_smmu 0x1007 0x0460>;
3436 };
3437
3438 compute-cb@8 {
3439 compatible = "qcom,fastrpc-compute-cb";
3440 reg = <8>;
3441 iommus = <&apps_smmu 0x1008 0x0460>;
3442 };
3443
3444 /* note: secure cb9 in downstream */
3445 };
3446 };
3447 };
3448
3449 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled";
3454 #phy-cells = <0>;
3455
3456 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref";
3458
3459 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 };
3461
3462 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled";
3467 #phy-cells = <0>;
3468
3469 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref";
3471
3472 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 };
3474
3475 usb_1_qmpphy: phy@88e8000 {
3476 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3477 reg = <0 0x088e8000 0 0x3000>;
3478
3479 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3480 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3482 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3483 clock-names = "aux",
3484 "ref",
3485 "com_aux",
3486 "usb3_pipe";
3487
3488 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", "common";
3491
3492 #clock-cells = <1>;
3493 #phy-cells = <1>;
3494
3495 status = "disabled";
3496
3497 ports {
3498 #address-cells = <1>;
3499 #size-cells = <0>;
3500
3501 port@0 {
3502 reg = <0>;
3503
3504 usb_1_qmpphy_out: endpoint {
3505 };
3506 };
3507
3508 port@1 {
3509 reg = <1>;
3510
3511 usb_1_qmpphy_usb_ss_in: endpoint {
3512 remote-endpoint = <&usb_1_dwc3_ss>;
3513 };
3514 };
3515
3516 port@2 {
3517 reg = <2>;
3518
3519 usb_1_qmpphy_dp_in: endpoint {
3520 remote-endpoint = <&mdss_dp_out>;
3521 };
3522 };
3523 };
3524 };
3525
3526 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 0x1000>;
3529
3530 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3531 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3533 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3534 clock-names = "aux",
3535 "ref",
3536 "com_aux",
3537 "pipe";
3538 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3539 #clock-cells = <0>;
3540 #phy-cells = <0>;
3541
3542 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3543 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3544 reset-names = "phy",
3545 "phy_phy";
3546
3547 status = "disabled";
3548 };
3549
3550 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 0x1000>;
3553
3554 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc_irq", "pwr_irq";
3557
3558 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = <&sdhc2_opp_table>;
3567
3568 status = "disabled";
3569
3570 sdhc2_opp_table: opp-table {
3571 compatible = "operating-points-v2";
3572
3573 opp-19200000 {
3574 opp-hz = /bits/ 64 <19200000>;
3575 required-opps = <&rpmhpd_opp_min_svs>;
3576 };
3577
3578 opp-50000000 {
3579 opp-hz = /bits/ 64 <50000000>;
3580 required-opps = <&rpmhpd_opp_low_svs>;
3581 };
3582
3583 opp-100000000 {
3584 opp-hz = /bits/ 64 <100000000>;
3585 required-opps = <&rpmhpd_opp_svs>;
3586 };
3587
3588 opp-202000000 {
3589 opp-hz = /bits/ 64 <202000000>;
3590 required-opps = <&rpmhpd_opp_svs_l1>;
3591 };
3592 };
3593 };
3594
3595 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = <2>;
3599 qcom,bcm-voters = <&apps_bcm_voter>;
3600 };
3601
3602 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = <2>;
3606 qcom,bcm-voters = <&apps_bcm_voter>;
3607 };
3608
3609 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled";
3613 #address-cells = <2>;
3614 #size-cells = <2>;
3615 ranges;
3616 dma-ranges;
3617
3618 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_noc",
3625 "core",
3626 "iface",
3627 "sleep",
3628 "mock_utmi",
3629 "xo";
3630
3631 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates = <19200000>, <200000000>;
3634
3635 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3636 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3637 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
3638 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3639 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
3640 interrupt-names = "pwr_event",
3641 "hs_phy_irq",
3642 "dp_hs_phy_irq",
3643 "dm_hs_phy_irq",
3644 "ss_phy_irq";
3645
3646 power-domains = <&gcc USB30_PRIM_GDSC>;
3647
3648 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649
3650 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3651 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3652 interconnect-names = "usb-ddr", "apps-usb";
3653
3654 usb_1_dwc3: usb@a600000 {
3655 compatible = "snps,dwc3";
3656 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_susphy_quirk;
3660 snps,dis_enblslpm_quirk;
3661 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3662 phy-names = "usb2-phy", "usb3-phy";
3663
3664 ports {
3665 #address-cells = <1>;
3666 #size-cells = <0>;
3667
3668 port@0 {
3669 reg = <0>;
3670
3671 usb_1_dwc3_hs: endpoint {
3672 };
3673 };
3674
3675 port@1 {
3676 reg = <1>;
3677
3678 usb_1_dwc3_ss: endpoint {
3679 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3680 };
3681 };
3682 };
3683 };
3684 };
3685
3686 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled";
3690 #address-cells = <2>;
3691 #size-cells = <2>;
3692 ranges;
3693 dma-ranges;
3694
3695 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_noc",
3702 "core",
3703 "iface",
3704 "sleep",
3705 "mock_utmi",
3706 "xo";
3707
3708 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates = <19200000>, <200000000>;
3711
3712 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3713 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3714 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
3715 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3716 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>;
3717 interrupt-names = "pwr_event",
3718 "hs_phy_irq",
3719 "dp_hs_phy_irq",
3720 "dm_hs_phy_irq",
3721 "ss_phy_irq";
3722
3723 power-domains = <&gcc USB30_SEC_GDSC>;
3724
3725 resets = <&gcc GCC_USB30_SEC_BCR>;
3726
3727 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3728 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3729 interconnect-names = "usb-ddr", "apps-usb";
3730
3731 usb_2_dwc3: usb@a800000 {
3732 compatible = "snps,dwc3";
3733 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_susphy_quirk;
3737 snps,dis_enblslpm_quirk;
3738 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
3739 phy-names = "usb2-phy", "usb3-phy";
3740 };
3741 };
3742
3743 videocc: clock-controller@ab00000 {
3744 compatible = "qcom,sm8150-videocc";
3745 reg = <0 0x0ab00000 0 0x10000>;
3746 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3747 <&rpmhcc RPMH_CXO_CLK>;
3748 clock-names = "iface", "bi_tcxo";
3749 power-domains = <&rpmhpd SM8150_MMCX>;
3750 required-opps = <&rpmhpd_opp_low_svs>;
3751 #clock-cells = <1>;
3752 #reset-cells = <1>;
3753 #power-domain-cells = <1>;
3754 };
3755
3756 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = <2>;
3760 qcom,bcm-voters = <&apps_bcm_voter>;
3761 };
3762
3763 camcc: clock-controller@ad00000 {
3764 compatible = "qcom,sm8150-camcc";
3765 reg = <0 0x0ad00000 0 0x10000>;
3766 clocks = <&rpmhcc RPMH_CXO_CLK>,
3767 <&gcc GCC_CAMERA_AHB_CLK>;
3768 power-domains = <&rpmhpd SM8150_MMCX>;
3769 required-opps = <&rpmhpd_opp_low_svs>;
3770 #clock-cells = <1>;
3771 #reset-cells = <1>;
3772 #power-domain-cells = <1>;
3773 };
3774
3775 mdss: display-subsystem@ae00000 {
3776 compatible = "qcom,sm8150-mdss";
3777 reg = <0 0x0ae00000 0 0x1000>;
3778 reg-names = "mdss";
3779
3780 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3781 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3782 interconnect-names = "mdp0-mem", "mdp1-mem";
3783
3784 power-domains = <&dispcc MDSS_GDSC>;
3785
3786 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3787 <&gcc GCC_DISP_HF_AXI_CLK>,
3788 <&gcc GCC_DISP_SF_AXI_CLK>,
3789 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3790 clock-names = "iface", "bus", "nrt_bus", "core";
3791
3792 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3793 interrupt-controller;
3794 #interrupt-cells = <1>;
3795
3796 iommus = <&apps_smmu 0x800 0x420>;
3797
3798 status = "disabled";
3799
3800 #address-cells = <2>;
3801 #size-cells = <2>;
3802 ranges;
3803
3804 mdss_mdp: display-controller@ae01000 {
3805 compatible = "qcom,sm8150-dpu";
3806 reg = <0 0x0ae01000 0 0x8f000>,
3807 <0 0x0aeb0000 0 0x2008>;
3808 reg-names = "mdp", "vbif";
3809
3810 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3811 <&gcc GCC_DISP_HF_AXI_CLK>,
3812 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3813 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3814 clock-names = "iface", "bus", "core", "vsync";
3815
3816 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3817 assigned-clock-rates = <19200000>;
3818
3819 operating-points-v2 = <&mdp_opp_table>;
3820 power-domains = <&rpmhpd SM8150_MMCX>;
3821
3822 interrupt-parent = <&mdss>;
3823 interrupts = <0>;
3824
3825 ports {
3826 #address-cells = <1>;
3827 #size-cells = <0>;
3828
3829 port@0 {
3830 reg = <0>;
3831 dpu_intf1_out: endpoint {
3832 remote-endpoint = <&mdss_dsi0_in>;
3833 };
3834 };
3835
3836 port@1 {
3837 reg = <1>;
3838 dpu_intf2_out: endpoint {
3839 remote-endpoint = <&mdss_dsi1_in>;
3840 };
3841 };
3842
3843 port@2 {
3844 reg = <2>;
3845 dpu_intf0_out: endpoint {
3846 remote-endpoint = <&mdss_dp_in>;
3847 };
3848 };
3849 };
3850
3851 mdp_opp_table: opp-table {
3852 compatible = "operating-points-v2";
3853
3854 opp-171428571 {
3855 opp-hz = /bits/ 64 <171428571>;
3856 required-opps = <&rpmhpd_opp_low_svs>;
3857 };
3858
3859 opp-300000000 {
3860 opp-hz = /bits/ 64 <300000000>;
3861 required-opps = <&rpmhpd_opp_svs>;
3862 };
3863
3864 opp-345000000 {
3865 opp-hz = /bits/ 64 <345000000>;
3866 required-opps = <&rpmhpd_opp_svs_l1>;
3867 };
3868
3869 opp-460000000 {
3870 opp-hz = /bits/ 64 <460000000>;
3871 required-opps = <&rpmhpd_opp_nom>;
3872 };
3873 };
3874 };
3875
3876 mdss_dp: displayport-controller@ae90000 {
3877 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3878 reg = <0 0xae90000 0 0x200>,
3879 <0 0xae90200 0 0x200>,
3880 <0 0xae90400 0 0x600>,
3881 <0 0x0ae90a00 0 0x600>,
3882 <0 0x0ae91000 0 0x600>;
3883
3884 interrupt-parent = <&mdss>;
3885 interrupts = <12>;
3886 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3887 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3888 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3889 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3890 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3891 clock-names = "core_iface",
3892 "core_aux",
3893 "ctrl_link",
3894 "ctrl_link_iface",
3895 "stream_pixel";
3896
3897 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3898 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3899 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3900 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3901
3902 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3903 phy-names = "dp";
3904
3905 #sound-dai-cells = <0>;
3906
3907 operating-points-v2 = <&dp_opp_table>;
3908 power-domains = <&rpmhpd SM8250_MMCX>;
3909
3910 status = "disabled";
3911
3912 ports {
3913 #address-cells = <1>;
3914 #size-cells = <0>;
3915
3916 port@0 {
3917 reg = <0>;
3918 mdss_dp_in: endpoint {
3919 remote-endpoint = <&dpu_intf0_out>;
3920 };
3921 };
3922
3923 port@1 {
3924 reg = <1>;
3925
3926 mdss_dp_out: endpoint {
3927 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3928 };
3929 };
3930 };
3931
3932 dp_opp_table: opp-table {
3933 compatible = "operating-points-v2";
3934
3935 opp-160000000 {
3936 opp-hz = /bits/ 64 <160000000>;
3937 required-opps = <&rpmhpd_opp_low_svs>;
3938 };
3939
3940 opp-270000000 {
3941 opp-hz = /bits/ 64 <270000000>;
3942 required-opps = <&rpmhpd_opp_svs>;
3943 };
3944
3945 opp-540000000 {
3946 opp-hz = /bits/ 64 <540000000>;
3947 required-opps = <&rpmhpd_opp_svs_l1>;
3948 };
3949
3950 opp-810000000 {
3951 opp-hz = /bits/ 64 <810000000>;
3952 required-opps = <&rpmhpd_opp_nom>;
3953 };
3954 };
3955 };
3956
3957 mdss_dsi0: dsi@ae94000 {
3958 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3959 reg = <0 0x0ae94000 0 0x400>;
3960 reg-names = "dsi_ctrl";
3961
3962 interrupt-parent = <&mdss>;
3963 interrupts = <4>;
3964
3965 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3966 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3967 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3968 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3969 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3970 <&gcc GCC_DISP_HF_AXI_CLK>;
3971 clock-names = "byte",
3972 "byte_intf",
3973 "pixel",
3974 "core",
3975 "iface",
3976 "bus";
3977
3978 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3979 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3980 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3981 <&mdss_dsi0_phy 1>;
3982
3983 operating-points-v2 = <&dsi_opp_table>;
3984 power-domains = <&rpmhpd SM8150_MMCX>;
3985
3986 phys = <&mdss_dsi0_phy>;
3987
3988 status = "disabled";
3989
3990 #address-cells = <1>;
3991 #size-cells = <0>;
3992
3993 ports {
3994 #address-cells = <1>;
3995 #size-cells = <0>;
3996
3997 port@0 {
3998 reg = <0>;
3999 mdss_dsi0_in: endpoint {
4000 remote-endpoint = <&dpu_intf1_out>;
4001 };
4002 };
4003
4004 port@1 {
4005 reg = <1>;
4006 mdss_dsi0_out: endpoint {
4007 };
4008 };
4009 };
4010
4011 dsi_opp_table: opp-table {
4012 compatible = "operating-points-v2";
4013
4014 opp-187500000 {
4015 opp-hz = /bits/ 64 <187500000>;
4016 required-opps = <&rpmhpd_opp_low_svs>;
4017 };
4018
4019 opp-300000000 {
4020 opp-hz = /bits/ 64 <300000000>;
4021 required-opps = <&rpmhpd_opp_svs>;
4022 };
4023
4024 opp-358000000 {
4025 opp-hz = /bits/ 64 <358000000>;
4026 required-opps = <&rpmhpd_opp_svs_l1>;
4027 };
4028 };
4029 };
4030
4031 mdss_dsi0_phy: phy@ae94400 {
4032 compatible = "qcom,dsi-phy-7nm-8150";
4033 reg = <0 0x0ae94400 0 0x200>,
4034 <0 0x0ae94600 0 0x280>,
4035 <0 0x0ae94900 0 0x260>;
4036 reg-names = "dsi_phy",
4037 "dsi_phy_lane",
4038 "dsi_pll";
4039
4040 #clock-cells = <1>;
4041 #phy-cells = <0>;
4042
4043 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4044 <&rpmhcc RPMH_CXO_CLK>;
4045 clock-names = "iface", "ref";
4046
4047 status = "disabled";
4048 };
4049
4050 mdss_dsi1: dsi@ae96000 {
4051 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4052 reg = <0 0x0ae96000 0 0x400>;
4053 reg-names = "dsi_ctrl";
4054
4055 interrupt-parent = <&mdss>;
4056 interrupts = <5>;
4057
4058 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4059 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4060 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4061 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4062 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4063 <&gcc GCC_DISP_HF_AXI_CLK>;
4064 clock-names = "byte",
4065 "byte_intf",
4066 "pixel",
4067 "core",
4068 "iface",
4069 "bus";
4070
4071 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4072 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4073 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4074 <&mdss_dsi1_phy 1>;
4075
4076 operating-points-v2 = <&dsi_opp_table>;
4077 power-domains = <&rpmhpd SM8150_MMCX>;
4078
4079 phys = <&mdss_dsi1_phy>;
4080
4081 status = "disabled";
4082
4083 #address-cells = <1>;
4084 #size-cells = <0>;
4085
4086 ports {
4087 #address-cells = <1>;
4088 #size-cells = <0>;
4089
4090 port@0 {
4091 reg = <0>;
4092 mdss_dsi1_in: endpoint {
4093 remote-endpoint = <&dpu_intf2_out>;
4094 };
4095 };
4096
4097 port@1 {
4098 reg = <1>;
4099 mdss_dsi1_out: endpoint {
4100 };
4101 };
4102 };
4103 };
4104
4105 mdss_dsi1_phy: phy@ae96400 {
4106 compatible = "qcom,dsi-phy-7nm-8150";
4107 reg = <0 0x0ae96400 0 0x200>,
4108 <0 0x0ae96600 0 0x280>,
4109 <0 0x0ae96900 0 0x260>;
4110 reg-names = "dsi_phy",
4111 "dsi_phy_lane",
4112 "dsi_pll";
4113
4114 #clock-cells = <1>;
4115 #phy-cells = <0>;
4116
4117 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4118 <&rpmhcc RPMH_CXO_CLK>;
4119 clock-names = "iface", "ref";
4120
4121 status = "disabled";
4122 };
4123 };
4124
4125 dispcc: clock-controller@af00000 {
4126 compatible = "qcom,sm8150-dispcc";
4127 reg = <0 0x0af00000 0 0x10000>;
4128 clocks = <&rpmhcc RPMH_CXO_CLK>,
4129 <&mdss_dsi0_phy 0>,
4130 <&mdss_dsi0_phy 1>,
4131 <&mdss_dsi1_phy 0>,
4132 <&mdss_dsi1_phy 1>,
4133 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4134 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4135 clock-names = "bi_tcxo",
4136 "dsi0_phy_pll_out_byteclk",
4137 "dsi0_phy_pll_out_dsiclk",
4138 "dsi1_phy_pll_out_byteclk",
4139 "dsi1_phy_pll_out_dsiclk",
4140 "dp_phy_pll_link_clk",
4141 "dp_phy_pll_vco_div_clk";
4142 power-domains = <&rpmhpd SM8150_MMCX>;
4143 required-opps = <&rpmhpd_opp_low_svs>;
4144 #clock-cells = <1>;
4145 #reset-cells = <1>;
4146 #power-domain-cells = <1>;
4147 };
4148
4149 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 0x30000>;
4152 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <125 63 1>;
4154 #interrupt-cells = <2>;
4155 interrupt-parent = <&intc>;
4156 interrupt-controller;
4157 };
4158
4159 aoss_qmp: power-management@c300000 {
4160 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_shared 0>;
4164
4165 #clock-cells = <0>;
4166 };
4167
4168 sram@c3f0000 {
4169 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 0x400>;
4171 };
4172
4173 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells = <1>;
4182 };
4183
4184 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells = <1>;
4193 };
4194
4195 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>;
4206 qcom,channel = <0>;
4207 #address-cells = <2>;
4208 #size-cells = <0>;
4209 interrupt-controller;
4210 #interrupt-cells = <4>;
4211 };
4212
4213 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>;
4217 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 };
4300
4301 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 0x0 0x4040>;
4304
4305 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wdog", "fatal", "ready",
4311 "handover", "stop-ack";
4312
4313 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo";
4315
4316 power-domains = <&rpmhpd SM8150_CX>;
4317
4318 memory-region = <&adsp_mem>;
4319
4320 qcom,qmp = <&aoss_qmp>;
4321
4322 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names = "stop";
4324
4325 status = "disabled";
4326
4327 glink-edge {
4328 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpass";
4330 qcom,remote-pid = <2>;
4331 mboxes = <&apss_shared 8>;
4332
4333 fastrpc {
4334 compatible = "qcom,fastrpc";
4335 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label = "adsp";
4337 qcom,non-secure-domain;
4338 #address-cells = <1>;
4339 #size-cells = <0>;
4340
4341 compute-cb@3 {
4342 compatible = "qcom,fastrpc-compute-cb";
4343 reg = <3>;
4344 iommus = <&apps_smmu 0x1b23 0x0>;
4345 };
4346
4347 compute-cb@4 {
4348 compatible = "qcom,fastrpc-compute-cb";
4349 reg = <4>;
4350 iommus = <&apps_smmu 0x1b24 0x0>;
4351 };
4352
4353 compute-cb@5 {
4354 compatible = "qcom,fastrpc-compute-cb";
4355 reg = <5>;
4356 iommus = <&apps_smmu 0x1b25 0x0>;
4357 };
4358 };
4359 };
4360 };
4361
4362 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic-v3";
4364 interrupt-controller;
4365 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 };
4370
4371 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm8150-apss-shared",
4373 "qcom,sdm845-apss-shared";
4374 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>;
4376 };
4377
4378 watchdog@17c10000 {
4379 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4383 };
4384
4385 timer@17c20000 {
4386 #address-cells = <1>;
4387 #size-cells = <1>;
4388 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19200000>;
4392
4393 frame@17c21000 {
4394 frame-number = <0>;
4395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c21000 0x1000>,
4398 <0x17c22000 0x1000>;
4399 };
4400
4401 frame@17c23000 {
4402 frame-number = <1>;
4403 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c23000 0x1000>;
4405 status = "disabled";
4406 };
4407
4408 frame@17c25000 {
4409 frame-number = <2>;
4410 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c25000 0x1000>;
4412 status = "disabled";
4413 };
4414
4415 frame@17c27000 {
4416 frame-number = <3>;
4417 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c26000 0x1000>;
4419 status = "disabled";
4420 };
4421
4422 frame@17c29000 {
4423 frame-number = <4>;
4424 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c29000 0x1000>;
4426 status = "disabled";
4427 };
4428
4429 frame@17c2b000 {
4430 frame-number = <5>;
4431 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2b000 0x1000>;
4433 status = "disabled";
4434 };
4435
4436 frame@17c2d000 {
4437 frame-number = <6>;
4438 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2d000 0x1000>;
4440 status = "disabled";
4441 };
4442 };
4443
4444 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc";
4446 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>;
4456 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SLEEP_TCS 3>,
4458 <WAKE_TCS 3>,
4459 <CONTROL_TCS 1>;
4460 power-domains = <&CLUSTER_PD>;
4461
4462 rpmhcc: clock-controller {
4463 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells = <1>;
4465 clock-names = "xo";
4466 clocks = <&xo_board>;
4467 };
4468
4469 rpmhpd: power-controller {
4470 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain-cells = <1>;
4472 operating-points-v2 = <&rpmhpd_opp_table>;
4473
4474 rpmhpd_opp_table: opp-table {
4475 compatible = "operating-points-v2";
4476
4477 rpmhpd_opp_ret: opp1 {
4478 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 };
4480
4481 rpmhpd_opp_min_svs: opp2 {
4482 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 };
4484
4485 rpmhpd_opp_low_svs: opp3 {
4486 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 };
4488
4489 rpmhpd_opp_svs: opp4 {
4490 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 };
4492
4493 rpmhpd_opp_svs_l1: opp5 {
4494 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 };
4496
4497 rpmhpd_opp_svs_l2: opp6 {
4498 opp-level = <224>;
4499 };
4500
4501 rpmhpd_opp_nom: opp7 {
4502 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 };
4504
4505 rpmhpd_opp_nom_l1: opp8 {
4506 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 };
4508
4509 rpmhpd_opp_nom_l2: opp9 {
4510 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 };
4512
4513 rpmhpd_opp_turbo: opp10 {
4514 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 };
4516
4517 rpmhpd_opp_turbo_l1: opp11 {
4518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 };
4520 };
4521 };
4522
4523 apps_bcm_voter: bcm-voter {
4524 compatible = "qcom,bcm-voter";
4525 };
4526 };
4527
4528 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4530 reg = <0 0x18321000 0 0x1400>;
4531
4532 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", "alternate";
4534
4535 #interconnect-cells = <1>;
4536 };
4537
4538 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-domain2";
4544
4545 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", "alternate";
4547
4548 #freq-domain-cells = <1>;
4549 #clock-cells = <1>;
4550 };
4551
4552 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller;
4561 #interrupt-cells = <1>;
4562 };
4563
4564 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller;
4573 #interrupt-cells = <1>;
4574 };
4575
4576 wifi: wifi@18800000 {
4577 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase";
4580 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled";
4597 };
4598 };
4599
4600 timer {
4601 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 };
4607
4608 thermal-zones {
4609 cpu0-thermal {
4610 polling-delay-passive = <250>;
4611
4612 thermal-sensors = <&tsens0 1>;
4613
4614 trips {
4615 cpu0_alert0: trip-point0 {
4616 temperature = <90000>;
4617 hysteresis = <2000>;
4618 type = "passive";
4619 };
4620
4621 cpu0_alert1: trip-point1 {
4622 temperature = <95000>;
4623 hysteresis = <2000>;
4624 type = "passive";
4625 };
4626
4627 cpu0_crit: cpu-crit {
4628 temperature = <110000>;
4629 hysteresis = <1000>;
4630 type = "critical";
4631 };
4632 };
4633
4634 cooling-maps {
4635 map0 {
4636 trip = <&cpu0_alert0>;
4637 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 };
4642 map1 {
4643 trip = <&cpu0_alert1>;
4644 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 };
4649 };
4650 };
4651
4652 cpu1-thermal {
4653 polling-delay-passive = <250>;
4654
4655 thermal-sensors = <&tsens0 2>;
4656
4657 trips {
4658 cpu1_alert0: trip-point0 {
4659 temperature = <90000>;
4660 hysteresis = <2000>;
4661 type = "passive";
4662 };
4663
4664 cpu1_alert1: trip-point1 {
4665 temperature = <95000>;
4666 hysteresis = <2000>;
4667 type = "passive";
4668 };
4669
4670 cpu1_crit: cpu-crit {
4671 temperature = <110000>;
4672 hysteresis = <1000>;
4673 type = "critical";
4674 };
4675 };
4676
4677 cooling-maps {
4678 map0 {
4679 trip = <&cpu1_alert0>;
4680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 };
4685 map1 {
4686 trip = <&cpu1_alert1>;
4687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 };
4692 };
4693 };
4694
4695 cpu2-thermal {
4696 polling-delay-passive = <250>;
4697
4698 thermal-sensors = <&tsens0 3>;
4699
4700 trips {
4701 cpu2_alert0: trip-point0 {
4702 temperature = <90000>;
4703 hysteresis = <2000>;
4704 type = "passive";
4705 };
4706
4707 cpu2_alert1: trip-point1 {
4708 temperature = <95000>;
4709 hysteresis = <2000>;
4710 type = "passive";
4711 };
4712
4713 cpu2_crit: cpu-crit {
4714 temperature = <110000>;
4715 hysteresis = <1000>;
4716 type = "critical";
4717 };
4718 };
4719
4720 cooling-maps {
4721 map0 {
4722 trip = <&cpu2_alert0>;
4723 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 };
4728 map1 {
4729 trip = <&cpu2_alert1>;
4730 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 };
4735 };
4736 };
4737
4738 cpu3-thermal {
4739 polling-delay-passive = <250>;
4740
4741 thermal-sensors = <&tsens0 4>;
4742
4743 trips {
4744 cpu3_alert0: trip-point0 {
4745 temperature = <90000>;
4746 hysteresis = <2000>;
4747 type = "passive";
4748 };
4749
4750 cpu3_alert1: trip-point1 {
4751 temperature = <95000>;
4752 hysteresis = <2000>;
4753 type = "passive";
4754 };
4755
4756 cpu3_crit: cpu-crit {
4757 temperature = <110000>;
4758 hysteresis = <1000>;
4759 type = "critical";
4760 };
4761 };
4762
4763 cooling-maps {
4764 map0 {
4765 trip = <&cpu3_alert0>;
4766 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 };
4771 map1 {
4772 trip = <&cpu3_alert1>;
4773 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 };
4778 };
4779 };
4780
4781 cpu4-top-thermal {
4782 polling-delay-passive = <250>;
4783
4784 thermal-sensors = <&tsens0 7>;
4785
4786 trips {
4787 cpu4_top_alert0: trip-point0 {
4788 temperature = <90000>;
4789 hysteresis = <2000>;
4790 type = "passive";
4791 };
4792
4793 cpu4_top_alert1: trip-point1 {
4794 temperature = <95000>;
4795 hysteresis = <2000>;
4796 type = "passive";
4797 };
4798
4799 cpu4_top_crit: cpu-crit {
4800 temperature = <110000>;
4801 hysteresis = <1000>;
4802 type = "critical";
4803 };
4804 };
4805
4806 cooling-maps {
4807 map0 {
4808 trip = <&cpu4_top_alert0>;
4809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 };
4814 map1 {
4815 trip = <&cpu4_top_alert1>;
4816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 };
4821 };
4822 };
4823
4824 cpu5-top-thermal {
4825 polling-delay-passive = <250>;
4826
4827 thermal-sensors = <&tsens0 8>;
4828
4829 trips {
4830 cpu5_top_alert0: trip-point0 {
4831 temperature = <90000>;
4832 hysteresis = <2000>;
4833 type = "passive";
4834 };
4835
4836 cpu5_top_alert1: trip-point1 {
4837 temperature = <95000>;
4838 hysteresis = <2000>;
4839 type = "passive";
4840 };
4841
4842 cpu5_top_crit: cpu-crit {
4843 temperature = <110000>;
4844 hysteresis = <1000>;
4845 type = "critical";
4846 };
4847 };
4848
4849 cooling-maps {
4850 map0 {
4851 trip = <&cpu5_top_alert0>;
4852 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 };
4857 map1 {
4858 trip = <&cpu5_top_alert1>;
4859 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 };
4864 };
4865 };
4866
4867 cpu6-top-thermal {
4868 polling-delay-passive = <250>;
4869
4870 thermal-sensors = <&tsens0 9>;
4871
4872 trips {
4873 cpu6_top_alert0: trip-point0 {
4874 temperature = <90000>;
4875 hysteresis = <2000>;
4876 type = "passive";
4877 };
4878
4879 cpu6_top_alert1: trip-point1 {
4880 temperature = <95000>;
4881 hysteresis = <2000>;
4882 type = "passive";
4883 };
4884
4885 cpu6_top_crit: cpu-crit {
4886 temperature = <110000>;
4887 hysteresis = <1000>;
4888 type = "critical";
4889 };
4890 };
4891
4892 cooling-maps {
4893 map0 {
4894 trip = <&cpu6_top_alert0>;
4895 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 };
4900 map1 {
4901 trip = <&cpu6_top_alert1>;
4902 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 };
4907 };
4908 };
4909
4910 cpu7-top-thermal {
4911 polling-delay-passive = <250>;
4912
4913 thermal-sensors = <&tsens0 10>;
4914
4915 trips {
4916 cpu7_top_alert0: trip-point0 {
4917 temperature = <90000>;
4918 hysteresis = <2000>;
4919 type = "passive";
4920 };
4921
4922 cpu7_top_alert1: trip-point1 {
4923 temperature = <95000>;
4924 hysteresis = <2000>;
4925 type = "passive";
4926 };
4927
4928 cpu7_top_crit: cpu-crit {
4929 temperature = <110000>;
4930 hysteresis = <1000>;
4931 type = "critical";
4932 };
4933 };
4934
4935 cooling-maps {
4936 map0 {
4937 trip = <&cpu7_top_alert0>;
4938 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 };
4943 map1 {
4944 trip = <&cpu7_top_alert1>;
4945 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 };
4950 };
4951 };
4952
4953 cpu4-bottom-thermal {
4954 polling-delay-passive = <250>;
4955
4956 thermal-sensors = <&tsens0 11>;
4957
4958 trips {
4959 cpu4_bottom_alert0: trip-point0 {
4960 temperature = <90000>;
4961 hysteresis = <2000>;
4962 type = "passive";
4963 };
4964
4965 cpu4_bottom_alert1: trip-point1 {
4966 temperature = <95000>;
4967 hysteresis = <2000>;
4968 type = "passive";
4969 };
4970
4971 cpu4_bottom_crit: cpu-crit {
4972 temperature = <110000>;
4973 hysteresis = <1000>;
4974 type = "critical";
4975 };
4976 };
4977
4978 cooling-maps {
4979 map0 {
4980 trip = <&cpu4_bottom_alert0>;
4981 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 };
4986 map1 {
4987 trip = <&cpu4_bottom_alert1>;
4988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 };
4993 };
4994 };
4995
4996 cpu5-bottom-thermal {
4997 polling-delay-passive = <250>;
4998
4999 thermal-sensors = <&tsens0 12>;
5000
5001 trips {
5002 cpu5_bottom_alert0: trip-point0 {
5003 temperature = <90000>;
5004 hysteresis = <2000>;
5005 type = "passive";
5006 };
5007
5008 cpu5_bottom_alert1: trip-point1 {
5009 temperature = <95000>;
5010 hysteresis = <2000>;
5011 type = "passive";
5012 };
5013
5014 cpu5_bottom_crit: cpu-crit {
5015 temperature = <110000>;
5016 hysteresis = <1000>;
5017 type = "critical";
5018 };
5019 };
5020
5021 cooling-maps {
5022 map0 {
5023 trip = <&cpu5_bottom_alert0>;
5024 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 };
5029 map1 {
5030 trip = <&cpu5_bottom_alert1>;
5031 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 };
5036 };
5037 };
5038
5039 cpu6-bottom-thermal {
5040 polling-delay-passive = <250>;
5041
5042 thermal-sensors = <&tsens0 13>;
5043
5044 trips {
5045 cpu6_bottom_alert0: trip-point0 {
5046 temperature = <90000>;
5047 hysteresis = <2000>;
5048 type = "passive";
5049 };
5050
5051 cpu6_bottom_alert1: trip-point1 {
5052 temperature = <95000>;
5053 hysteresis = <2000>;
5054 type = "passive";
5055 };
5056
5057 cpu6_bottom_crit: cpu-crit {
5058 temperature = <110000>;
5059 hysteresis = <1000>;
5060 type = "critical";
5061 };
5062 };
5063
5064 cooling-maps {
5065 map0 {
5066 trip = <&cpu6_bottom_alert0>;
5067 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 };
5072 map1 {
5073 trip = <&cpu6_bottom_alert1>;
5074 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 };
5079 };
5080 };
5081
5082 cpu7-bottom-thermal {
5083 polling-delay-passive = <250>;
5084
5085 thermal-sensors = <&tsens0 14>;
5086
5087 trips {
5088 cpu7_bottom_alert0: trip-point0 {
5089 temperature = <90000>;
5090 hysteresis = <2000>;
5091 type = "passive";
5092 };
5093
5094 cpu7_bottom_alert1: trip-point1 {
5095 temperature = <95000>;
5096 hysteresis = <2000>;
5097 type = "passive";
5098 };
5099
5100 cpu7_bottom_crit: cpu-crit {
5101 temperature = <110000>;
5102 hysteresis = <1000>;
5103 type = "critical";
5104 };
5105 };
5106
5107 cooling-maps {
5108 map0 {
5109 trip = <&cpu7_bottom_alert0>;
5110 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 };
5115 map1 {
5116 trip = <&cpu7_bottom_alert1>;
5117 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 };
5122 };
5123 };
5124
5125 aoss0-thermal {
5126 polling-delay-passive = <250>;
5127
5128 thermal-sensors = <&tsens0 0>;
5129
5130 trips {
5131 aoss0_alert0: trip-point0 {
5132 temperature = <90000>;
5133 hysteresis = <2000>;
5134 type = "hot";
5135 };
5136 };
5137 };
5138
5139 cluster0-thermal {
5140 polling-delay-passive = <250>;
5141
5142 thermal-sensors = <&tsens0 5>;
5143
5144 trips {
5145 cluster0_alert0: trip-point0 {
5146 temperature = <90000>;
5147 hysteresis = <2000>;
5148 type = "hot";
5149 };
5150 cluster0_crit: cluster0-crit {
5151 temperature = <110000>;
5152 hysteresis = <2000>;
5153 type = "critical";
5154 };
5155 };
5156 };
5157
5158 cluster1-thermal {
5159 polling-delay-passive = <250>;
5160
5161 thermal-sensors = <&tsens0 6>;
5162
5163 trips {
5164 cluster1_alert0: trip-point0 {
5165 temperature = <90000>;
5166 hysteresis = <2000>;
5167 type = "hot";
5168 };
5169 cluster1_crit: cluster1-crit {
5170 temperature = <110000>;
5171 hysteresis = <2000>;
5172 type = "critical";
5173 };
5174 };
5175 };
5176
5177 gpu-top-thermal {
5178 polling-delay-passive = <250>;
5179
5180 thermal-sensors = <&tsens0 15>;
5181
5182 cooling-maps {
5183 map0 {
5184 trip = <&gpu_top_alert0>;
5185 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5186 };
5187 };
5188
5189 trips {
5190 gpu_top_alert0: trip-point0 {
5191 temperature = <85000>;
5192 hysteresis = <1000>;
5193 type = "passive";
5194 };
5195
5196 trip-point1 {
5197 temperature = <90000>;
5198 hysteresis = <1000>;
5199 type = "hot";
5200 };
5201
5202 trip-point2 {
5203 temperature = <110000>;
5204 hysteresis = <1000>;
5205 type = "critical";
5206 };
5207 };
5208 };
5209
5210 aoss1-thermal {
5211 polling-delay-passive = <250>;
5212
5213 thermal-sensors = <&tsens1 0>;
5214
5215 trips {
5216 aoss1_alert0: trip-point0 {
5217 temperature = <90000>;
5218 hysteresis = <2000>;
5219 type = "hot";
5220 };
5221 };
5222 };
5223
5224 wlan-thermal {
5225 polling-delay-passive = <250>;
5226
5227 thermal-sensors = <&tsens1 1>;
5228
5229 trips {
5230 wlan_alert0: trip-point0 {
5231 temperature = <90000>;
5232 hysteresis = <2000>;
5233 type = "hot";
5234 };
5235 };
5236 };
5237
5238 video-thermal {
5239 polling-delay-passive = <250>;
5240
5241 thermal-sensors = <&tsens1 2>;
5242
5243 trips {
5244 video_alert0: trip-point0 {
5245 temperature = <90000>;
5246 hysteresis = <2000>;
5247 type = "hot";
5248 };
5249 };
5250 };
5251
5252 mem-thermal {
5253 polling-delay-passive = <250>;
5254
5255 thermal-sensors = <&tsens1 3>;
5256
5257 trips {
5258 mem_alert0: trip-point0 {
5259 temperature = <90000>;
5260 hysteresis = <2000>;
5261 type = "hot";
5262 };
5263 };
5264 };
5265
5266 q6-hvx-thermal {
5267 polling-delay-passive = <250>;
5268
5269 thermal-sensors = <&tsens1 4>;
5270
5271 trips {
5272 q6_hvx_alert0: trip-point0 {
5273 temperature = <90000>;
5274 hysteresis = <2000>;
5275 type = "hot";
5276 };
5277 };
5278 };
5279
5280 camera-thermal {
5281 polling-delay-passive = <250>;
5282
5283 thermal-sensors = <&tsens1 5>;
5284
5285 trips {
5286 camera_alert0: trip-point0 {
5287 temperature = <90000>;
5288 hysteresis = <2000>;
5289 type = "hot";
5290 };
5291 };
5292 };
5293
5294 compute-thermal {
5295 polling-delay-passive = <250>;
5296
5297 thermal-sensors = <&tsens1 6>;
5298
5299 trips {
5300 compute_alert0: trip-point0 {
5301 temperature = <90000>;
5302 hysteresis = <2000>;
5303 type = "hot";
5304 };
5305 };
5306 };
5307
5308 modem-thermal {
5309 polling-delay-passive = <250>;
5310
5311 thermal-sensors = <&tsens1 7>;
5312
5313 trips {
5314 modem_alert0: trip-point0 {
5315 temperature = <90000>;
5316 hysteresis = <2000>;
5317 type = "hot";
5318 };
5319 };
5320 };
5321
5322 npu-thermal {
5323 polling-delay-passive = <250>;
5324
5325 thermal-sensors = <&tsens1 8>;
5326
5327 trips {
5328 npu_alert0: trip-point0 {
5329 temperature = <90000>;
5330 hysteresis = <2000>;
5331 type = "hot";
5332 };
5333 };
5334 };
5335
5336 modem-vec-thermal {
5337 polling-delay-passive = <250>;
5338
5339 thermal-sensors = <&tsens1 9>;
5340
5341 trips {
5342 modem_vec_alert0: trip-point0 {
5343 temperature = <90000>;
5344 hysteresis = <2000>;
5345 type = "hot";
5346 };
5347 };
5348 };
5349
5350 modem-scl-thermal {
5351 polling-delay-passive = <250>;
5352
5353 thermal-sensors = <&tsens1 10>;
5354
5355 trips {
5356 modem_scl_alert0: trip-point0 {
5357 temperature = <90000>;
5358 hysteresis = <2000>;
5359 type = "hot";
5360 };
5361 };
5362 };
5363
5364 gpu-bottom-thermal {
5365 polling-delay-passive = <250>;
5366
5367 thermal-sensors = <&tsens1 11>;
5368
5369 cooling-maps {
5370 map0 {
5371 trip = <&gpu_bottom_alert0>;
5372 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5373 };
5374 };
5375
5376 trips {
5377 gpu_bottom_alert0: trip-point0 {
5378 temperature = <85000>;
5379 hysteresis = <1000>;
5380 type = "passive";
5381 };
5382
5383 trip-point1 {
5384 temperature = <90000>;
5385 hysteresis = <1000>;
5386 type = "hot";
5387 };
5388
5389 trip-point2 {
5390 temperature = <110000>;
5391 hysteresis = <1000>;
5392 type = "critical";
5393 };
5394 };
5395 };
5396 };
5397 };
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