1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25
26 / {
27 interrupt-parent = <&intc>;
28
29 #address-cells = <2>;
30 #size-cells = <2>;
31
32 aliases {
33 i2c0 = &i2c0;
34 i2c1 = &i2c1;
35 i2c2 = &i2c2;
36 i2c3 = &i2c3;
37 i2c4 = &i2c4;
38 i2c5 = &i2c5;
39 i2c6 = &i2c6;
40 i2c7 = &i2c7;
41 i2c8 = &i2c8;
42 i2c9 = &i2c9;
43 i2c10 = &i2c10;
44 i2c11 = &i2c11;
45 i2c12 = &i2c12;
46 i2c13 = &i2c13;
47 i2c14 = &i2c14;
48 i2c15 = &i2c15;
49 i2c16 = &i2c16;
50 i2c17 = &i2c17;
51 i2c18 = &i2c18;
52 i2c19 = &i2c19;
53 spi0 = &spi0;
54 spi1 = &spi1;
55 spi2 = &spi2;
56 spi3 = &spi3;
57 spi4 = &spi4;
58 spi5 = &spi5;
59 spi6 = &spi6;
60 spi7 = &spi7;
61 spi8 = &spi8;
62 spi9 = &spi9;
63 spi10 = &spi10;
64 spi11 = &spi11;
65 spi12 = &spi12;
66 spi13 = &spi13;
67 spi14 = &spi14;
68 spi15 = &spi15;
69 spi16 = &spi16;
70 spi17 = &spi17;
71 spi18 = &spi18;
72 spi19 = &spi19;
73 };
74
75 chosen { };
76
77 clocks {
78 xo_board: xo-board {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <38400000>;
82 clock-output-names = "xo_board";
83 };
84
85 sleep_clk: sleep-clk {
86 compatible = "fixed-clock";
87 clock-frequency = <32768>;
88 #clock-cells = <0>;
89 };
90 };
91
92 cpus {
93 #address-cells = <2>;
94 #size-cells = <0>;
95
96 CPU0: cpu@0 {
97 device_type = "cpu";
98 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
101 enable-method = "psci";
102 capacity-dmips-mhz = <448>;
103 dynamic-power-coefficient = <105>;
104 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_PD0>;
106 power-domain-names = "psci";
107 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
110 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>;
112 L2_0: l2-cache {
113 compatible = "cache";
114 cache-level = <2>;
115 cache-size = <0x20000>;
116 cache-unified;
117 next-level-cache = <&L3_0>;
118 L3_0: l3-cache {
119 compatible = "cache";
120 cache-level = <3>;
121 cache-size = <0x400000>;
122 cache-unified;
123 };
124 };
125 };
126
127 CPU1: cpu@100 {
128 device_type = "cpu";
129 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw 0>;
132 enable-method = "psci";
133 capacity-dmips-mhz = <448>;
134 dynamic-power-coefficient = <105>;
135 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_PD1>;
137 power-domain-names = "psci";
138 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
141 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>;
143 L2_100: l2-cache {
144 compatible = "cache";
145 cache-level = <2>;
146 cache-size = <0x20000>;
147 cache-unified;
148 next-level-cache = <&L3_0>;
149 };
150 };
151
152 CPU2: cpu@200 {
153 device_type = "cpu";
154 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw 0>;
157 enable-method = "psci";
158 capacity-dmips-mhz = <448>;
159 dynamic-power-coefficient = <105>;
160 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_PD2>;
162 power-domain-names = "psci";
163 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
166 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>;
168 L2_200: l2-cache {
169 compatible = "cache";
170 cache-level = <2>;
171 cache-size = <0x20000>;
172 cache-unified;
173 next-level-cache = <&L3_0>;
174 };
175 };
176
177 CPU3: cpu@300 {
178 device_type = "cpu";
179 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw 0>;
182 enable-method = "psci";
183 capacity-dmips-mhz = <448>;
184 dynamic-power-coefficient = <105>;
185 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_PD3>;
187 power-domain-names = "psci";
188 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
191 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>;
193 L2_300: l2-cache {
194 compatible = "cache";
195 cache-level = <2>;
196 cache-size = <0x20000>;
197 cache-unified;
198 next-level-cache = <&L3_0>;
199 };
200 };
201
202 CPU4: cpu@400 {
203 device_type = "cpu";
204 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw 1>;
207 enable-method = "psci";
208 capacity-dmips-mhz = <1024>;
209 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_PD4>;
212 power-domain-names = "psci";
213 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
216 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>;
218 L2_400: l2-cache {
219 compatible = "cache";
220 cache-level = <2>;
221 cache-size = <0x40000>;
222 cache-unified;
223 next-level-cache = <&L3_0>;
224 };
225 };
226
227 CPU5: cpu@500 {
228 device_type = "cpu";
229 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw 1>;
232 enable-method = "psci";
233 capacity-dmips-mhz = <1024>;
234 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_PD5>;
237 power-domain-names = "psci";
238 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
241 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>;
243 L2_500: l2-cache {
244 compatible = "cache";
245 cache-level = <2>;
246 cache-size = <0x40000>;
247 cache-unified;
248 next-level-cache = <&L3_0>;
249 };
250 };
251
252 CPU6: cpu@600 {
253 device_type = "cpu";
254 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw 1>;
257 enable-method = "psci";
258 capacity-dmips-mhz = <1024>;
259 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_PD6>;
262 power-domain-names = "psci";
263 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
266 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>;
268 L2_600: l2-cache {
269 compatible = "cache";
270 cache-level = <2>;
271 cache-size = <0x40000>;
272 cache-unified;
273 next-level-cache = <&L3_0>;
274 };
275 };
276
277 CPU7: cpu@700 {
278 device_type = "cpu";
279 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw 2>;
282 enable-method = "psci";
283 capacity-dmips-mhz = <1024>;
284 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_PD7>;
287 power-domain-names = "psci";
288 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
291 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>;
293 L2_700: l2-cache {
294 compatible = "cache";
295 cache-level = <2>;
296 cache-size = <0x80000>;
297 cache-unified;
298 next-level-cache = <&L3_0>;
299 };
300 };
301
302 cpu-map {
303 cluster0 {
304 core0 {
305 cpu = <&CPU0>;
306 };
307
308 core1 {
309 cpu = <&CPU1>;
310 };
311
312 core2 {
313 cpu = <&CPU2>;
314 };
315
316 core3 {
317 cpu = <&CPU3>;
318 };
319
320 core4 {
321 cpu = <&CPU4>;
322 };
323
324 core5 {
325 cpu = <&CPU5>;
326 };
327
328 core6 {
329 cpu = <&CPU6>;
330 };
331
332 core7 {
333 cpu = <&CPU7>;
334 };
335 };
336 };
337
338 idle-states {
339 entry-method = "psci";
340
341 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = "arm,idle-state";
343 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspend-param = <0x40000004>;
345 entry-latency-us = <360>;
346 exit-latency-us = <531>;
347 min-residency-us = <3934>;
348 local-timer-stop;
349 };
350
351 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = "arm,idle-state";
353 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspend-param = <0x40000004>;
355 entry-latency-us = <702>;
356 exit-latency-us = <1061>;
357 min-residency-us = <4488>;
358 local-timer-stop;
359 };
360 };
361
362 domain-idle-states {
363 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = "domain-idle-state";
365 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency-us = <3264>;
367 exit-latency-us = <6562>;
368 min-residency-us = <9987>;
369 };
370 };
371 };
372
373 qup_virt: interconnect-qup-virt {
374 compatible = "qcom,sm8250-qup-virt";
375 #interconnect-cells = <2>;
376 qcom,bcm-voters = <&apps_bcm_voter>;
377 };
378
379 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points-v2";
381 opp-shared;
382
383 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <800000 9600000>;
386 };
387
388 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <800000 9600000>;
391 };
392
393 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <800000 16588800>;
396 };
397
398 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <800000 16588800>;
401 };
402
403 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <800000 19660800>;
406 };
407
408 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <1804000 19660800>;
411 };
412
413 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <1804000 23347200>;
416 };
417
418 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <1804000 26419200>;
421 };
422
423 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <1804000 29491200>;
426 };
427
428 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <1804000 32563200>;
431 };
432
433 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <1804000 36249600>;
436 };
437
438 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <2188000 36249600>;
441 };
442
443 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <2188000 39321600>;
446 };
447
448 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <3072000 42393600>;
451 };
452
453 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <3072000 42393600>;
456 };
457
458 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <4068000 42393600>;
461 };
462
463 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <4068000 42393600>;
466 };
467 };
468
469 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points-v2";
471 opp-shared;
472
473 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <1804000 19660800>;
476 };
477
478 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <2188000 23347200>;
481 };
482
483 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <2188000 26419200>;
486 };
487
488 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <3072000 26419200>;
491 };
492
493 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <3072000 29491200>;
496 };
497
498 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <4068000 29491200>;
501 };
502
503 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <4068000 32563200>;
506 };
507
508 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <4068000 32563200>;
511 };
512
513 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <5412000 39321600>;
516 };
517
518 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <5412000 42393600>;
521 };
522
523 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <5412000 45465600>;
526 };
527
528 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <6220000 45465600>;
531 };
532
533 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <6220000 48537600>;
536 };
537
538 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <7216000 48537600>;
541 };
542
543 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <7216000 51609600>;
546 };
547
548 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <7216000 51609600>;
551 };
552
553 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <8368000 51609600>;
556 };
557
558 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <8368000 51609600>;
561 };
562 };
563
564 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points-v2";
566 opp-shared;
567
568 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <2188000 19660800>;
571 };
572
573 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <2188000 26419200>;
576 };
577
578 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <3072000 26419200>;
581 };
582
583 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <3072000 29491200>;
586 };
587
588 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <4068000 32563200>;
591 };
592
593 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <4068000 32563200>;
596 };
597
598 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <4068000 36249600>;
601 };
602
603 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <5412000 39321600>;
606 };
607
608 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <5412000 42393600>;
611 };
612
613 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <6220000 45465600>;
616 };
617
618 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <6220000 48537600>;
621 };
622
623 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <7216000 48537600>;
626 };
627
628 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <7216000 51609600>;
631 };
632
633 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <7216000 51609600>;
636 };
637
638 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <8368000 51609600>;
641 };
642
643 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <8368000 51609600>;
646 };
647
648 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <8368000 51609600>;
651 };
652
653 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <8368000 51609600>;
656 };
657
658 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <8368000 51609600>;
661 };
662
663 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <8368000 51609600>;
666 };
667 };
668
669 firmware {
670 scm: scm {
671 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tcsr 0x13000>;
673 #reset-cells = <1>;
674 };
675 };
676
677 memory@80000000 {
678 device_type = "memory";
679 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0>;
681 };
682
683 pmu {
684 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 };
687
688 psci {
689 compatible = "arm,psci-1.0";
690 method = "smc";
691
692 CPU_PD0: power-domain-cpu0 {
693 #power-domain-cells = <0>;
694 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 };
697
698 CPU_PD1: power-domain-cpu1 {
699 #power-domain-cells = <0>;
700 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 };
703
704 CPU_PD2: power-domain-cpu2 {
705 #power-domain-cells = <0>;
706 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 };
709
710 CPU_PD3: power-domain-cpu3 {
711 #power-domain-cells = <0>;
712 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 };
715
716 CPU_PD4: power-domain-cpu4 {
717 #power-domain-cells = <0>;
718 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 };
721
722 CPU_PD5: power-domain-cpu5 {
723 #power-domain-cells = <0>;
724 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 };
727
728 CPU_PD6: power-domain-cpu6 {
729 #power-domain-cells = <0>;
730 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 };
733
734 CPU_PD7: power-domain-cpu7 {
735 #power-domain-cells = <0>;
736 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 };
739
740 CLUSTER_PD: power-domain-cpu-cluster0 {
741 #power-domain-cells = <0>;
742 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 };
744 };
745
746 qup_opp_table: opp-table-qup {
747 compatible = "operating-points-v2";
748
749 opp-50000000 {
750 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmhpd_opp_min_svs>;
752 };
753
754 opp-75000000 {
755 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmhpd_opp_low_svs>;
757 };
758
759 opp-120000000 {
760 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmhpd_opp_svs>;
762 };
763 };
764
765 reserved-memory {
766 #address-cells = <2>;
767 #size-cells = <2>;
768 ranges;
769
770 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map;
773 };
774
775 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map;
778 };
779
780 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map;
784 };
785
786 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map;
789 };
790
791 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map;
794 };
795
796 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map;
799 };
800
801 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map;
804 };
805
806 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map;
809 };
810
811 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map;
814 };
815
816 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map;
819 };
820
821 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map;
824 };
825
826 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map;
829 };
830
831 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map;
834 };
835
836 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map;
839 };
840
841 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map;
844 };
845
846 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map;
849 };
850
851 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map;
854 };
855
856 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map;
859 };
860 };
861
862 smem {
863 compatible = "qcom,smem";
864 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>;
866 };
867
868 smp2p-adsp {
869 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 IPCC_MPROC_SIGNAL_SMP2P
873 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIGNAL_SMP2P>;
876
877 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>;
879
880 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells = <1>;
883 };
884
885 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "slave-kernel";
887 interrupt-controller;
888 #interrupt-cells = <2>;
889 };
890 };
891
892 smp2p-cdsp {
893 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 IPCC_MPROC_SIGNAL_SMP2P
897 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIGNAL_SMP2P>;
900
901 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>;
903
904 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells = <1>;
907 };
908
909 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "slave-kernel";
911 interrupt-controller;
912 #interrupt-cells = <2>;
913 };
914 };
915
916 smp2p-slpi {
917 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 IPCC_MPROC_SIGNAL_SMP2P
921 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIGNAL_SMP2P>;
924
925 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>;
927
928 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells = <1>;
931 };
932
933 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "slave-kernel";
935 interrupt-controller;
936 #interrupt-cells = <2>;
937 };
938 };
939
940 soc: soc@0 {
941 #address-cells = <2>;
942 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus";
946
947 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>;
951 #reset-cells = <1>;
952 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo",
954 "bi_tcxo_ao",
955 "sleep_clk";
956 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>;
959 };
960
961 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller;
966 #interrupt-cells = <3>;
967 #mbox-cells = <2>;
968 };
969
970 qfprom: efuse@784000 {
971 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
972 reg = <0 0x00784000 0 0x8ff>;
973 #address-cells = <1>;
974 #size-cells = <1>;
975
976 gpu_speed_bin: gpu-speed-bin@19b {
977 reg = <0x19b 0x1>;
978 bits = <5 3>;
979 };
980 };
981
982 rng: rng@793000 {
983 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core";
987 };
988
989 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
991 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>;
1003 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>;
1006 status = "disabled";
1007 };
1008
1009 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>;
1016 #size-cells = <2>;
1017 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges;
1019 status = "disabled";
1020
1021 i2c14: i2c@880000 {
1022 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = "se";
1025 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = "tx", "rx";
1032 power-domains = <&rpmhpd SM8250_CX>;
1033 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1035 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1036 interconnect-names = "qup-core",
1037 "qup-config",
1038 "qup-memory";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1041 status = "disabled";
1042 };
1043
1044 spi14: spi@880000 {
1045 compatible = "qcom,geni-spi";
1046 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = "se";
1048 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = "tx", "rx";
1053 power-domains = <&rpmhpd RPMHPD_CX>;
1054 operating-points-v2 = <&qup_opp_table>;
1055 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1056 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1057 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1058 interconnect-names = "qup-core",
1059 "qup-config",
1060 "qup-memory";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 status = "disabled";
1064 };
1065
1066 i2c15: i2c@884000 {
1067 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = "se";
1070 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = "tx", "rx";
1077 power-domains = <&rpmhpd SM8250_CX>;
1078 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1079 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1080 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1081 interconnect-names = "qup-core",
1082 "qup-config",
1083 "qup-memory";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 status = "disabled";
1087 };
1088
1089 spi15: spi@884000 {
1090 compatible = "qcom,geni-spi";
1091 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = "se";
1093 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = "tx", "rx";
1098 power-domains = <&rpmhpd RPMHPD_CX>;
1099 operating-points-v2 = <&qup_opp_table>;
1100 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1101 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1102 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1103 interconnect-names = "qup-core",
1104 "qup-config",
1105 "qup-memory";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1108 status = "disabled";
1109 };
1110
1111 i2c16: i2c@888000 {
1112 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = "se";
1115 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = "tx", "rx";
1122 power-domains = <&rpmhpd SM8250_CX>;
1123 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1124 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1125 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1126 interconnect-names = "qup-core",
1127 "qup-config",
1128 "qup-memory";
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131 status = "disabled";
1132 };
1133
1134 spi16: spi@888000 {
1135 compatible = "qcom,geni-spi";
1136 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = "se";
1138 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = "tx", "rx";
1143 power-domains = <&rpmhpd RPMHPD_CX>;
1144 operating-points-v2 = <&qup_opp_table>;
1145 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1147 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1148 interconnect-names = "qup-core",
1149 "qup-config",
1150 "qup-memory";
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 status = "disabled";
1154 };
1155
1156 i2c17: i2c@88c000 {
1157 compatible = "qcom,geni-i2c";
1158 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = "se";
1160 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = "tx", "rx";
1167 power-domains = <&rpmhpd SM8250_CX>;
1168 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1169 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1170 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1171 interconnect-names = "qup-core",
1172 "qup-config",
1173 "qup-memory";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 status = "disabled";
1177 };
1178
1179 spi17: spi@88c000 {
1180 compatible = "qcom,geni-spi";
1181 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = "se";
1183 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = "tx", "rx";
1188 power-domains = <&rpmhpd RPMHPD_CX>;
1189 operating-points-v2 = <&qup_opp_table>;
1190 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1191 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1192 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1193 interconnect-names = "qup-core",
1194 "qup-config",
1195 "qup-memory";
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198 status = "disabled";
1199 };
1200
1201 uart17: serial@88c000 {
1202 compatible = "qcom,geni-uart";
1203 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = "se";
1205 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains = <&rpmhpd RPMHPD_CX>;
1210 operating-points-v2 = <&qup_opp_table>;
1211 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1213 interconnect-names = "qup-core",
1214 "qup-config";
1215 status = "disabled";
1216 };
1217
1218 i2c18: i2c@890000 {
1219 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = "se";
1222 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names = "default";
1224 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = "tx", "rx";
1229 power-domains = <&rpmhpd SM8250_CX>;
1230 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1231 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1232 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1233 interconnect-names = "qup-core",
1234 "qup-config",
1235 "qup-memory";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 status = "disabled";
1239 };
1240
1241 spi18: spi@890000 {
1242 compatible = "qcom,geni-spi";
1243 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = "se";
1245 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = "tx", "rx";
1250 power-domains = <&rpmhpd RPMHPD_CX>;
1251 operating-points-v2 = <&qup_opp_table>;
1252 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1253 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1254 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1255 interconnect-names = "qup-core",
1256 "qup-config",
1257 "qup-memory";
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1260 status = "disabled";
1261 };
1262
1263 uart18: serial@890000 {
1264 compatible = "qcom,geni-uart";
1265 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = "se";
1267 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains = <&rpmhpd RPMHPD_CX>;
1272 operating-points-v2 = <&qup_opp_table>;
1273 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1274 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1275 interconnect-names = "qup-core",
1276 "qup-config";
1277 status = "disabled";
1278 };
1279
1280 i2c19: i2c@894000 {
1281 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = "se";
1284 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = "tx", "rx";
1291 power-domains = <&rpmhpd SM8250_CX>;
1292 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1293 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1294 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1295 interconnect-names = "qup-core",
1296 "qup-config",
1297 "qup-memory";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1300 status = "disabled";
1301 };
1302
1303 spi19: spi@894000 {
1304 compatible = "qcom,geni-spi";
1305 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = "se";
1307 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = "tx", "rx";
1312 power-domains = <&rpmhpd RPMHPD_CX>;
1313 operating-points-v2 = <&qup_opp_table>;
1314 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1315 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1316 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1317 interconnect-names = "qup-core",
1318 "qup-config",
1319 "qup-memory";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1322 status = "disabled";
1323 };
1324 };
1325
1326 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1328 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>;
1343 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>;
1346 status = "disabled";
1347 };
1348
1349 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1357 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges;
1359 status = "disabled";
1360
1361 i2c0: i2c@980000 {
1362 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = "se";
1365 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = "tx", "rx";
1372 power-domains = <&rpmhpd SM8250_CX>;
1373 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1374 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1375 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1376 interconnect-names = "qup-core",
1377 "qup-config",
1378 "qup-memory";
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1381 status = "disabled";
1382 };
1383
1384 spi0: spi@980000 {
1385 compatible = "qcom,geni-spi";
1386 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = "se";
1388 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = "tx", "rx";
1393 power-domains = <&rpmhpd RPMHPD_CX>;
1394 operating-points-v2 = <&qup_opp_table>;
1395 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1396 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1397 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1398 interconnect-names = "qup-core",
1399 "qup-config",
1400 "qup-memory";
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1403 status = "disabled";
1404 };
1405
1406 i2c1: i2c@984000 {
1407 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = "se";
1410 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names = "default";
1412 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = "tx", "rx";
1417 power-domains = <&rpmhpd SM8250_CX>;
1418 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1419 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1420 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1421 interconnect-names = "qup-core",
1422 "qup-config",
1423 "qup-memory";
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1426 status = "disabled";
1427 };
1428
1429 spi1: spi@984000 {
1430 compatible = "qcom,geni-spi";
1431 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = "se";
1433 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = "tx", "rx";
1438 power-domains = <&rpmhpd RPMHPD_CX>;
1439 operating-points-v2 = <&qup_opp_table>;
1440 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1441 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1442 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1443 interconnect-names = "qup-core",
1444 "qup-config",
1445 "qup-memory";
1446 #address-cells = <1>;
1447 #size-cells = <0>;
1448 status = "disabled";
1449 };
1450
1451 i2c2: i2c@988000 {
1452 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = "se";
1455 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = "tx", "rx";
1462 power-domains = <&rpmhpd SM8250_CX>;
1463 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1464 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1465 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1466 interconnect-names = "qup-core",
1467 "qup-config",
1468 "qup-memory";
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1471 status = "disabled";
1472 };
1473
1474 spi2: spi@988000 {
1475 compatible = "qcom,geni-spi";
1476 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = "se";
1478 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = "tx", "rx";
1483 power-domains = <&rpmhpd RPMHPD_CX>;
1484 operating-points-v2 = <&qup_opp_table>;
1485 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1486 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1487 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1488 interconnect-names = "qup-core",
1489 "qup-config",
1490 "qup-memory";
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1493 status = "disabled";
1494 };
1495
1496 uart2: serial@988000 {
1497 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = "se";
1500 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains = <&rpmhpd RPMHPD_CX>;
1505 operating-points-v2 = <&qup_opp_table>;
1506 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1507 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1508 interconnect-names = "qup-core",
1509 "qup-config";
1510 status = "disabled";
1511 };
1512
1513 i2c3: i2c@98c000 {
1514 compatible = "qcom,geni-i2c";
1515 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = "se";
1517 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = "tx", "rx";
1524 power-domains = <&rpmhpd SM8250_CX>;
1525 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1526 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1527 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1528 interconnect-names = "qup-core",
1529 "qup-config",
1530 "qup-memory";
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1533 status = "disabled";
1534 };
1535
1536 spi3: spi@98c000 {
1537 compatible = "qcom,geni-spi";
1538 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = "se";
1540 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = "tx", "rx";
1545 power-domains = <&rpmhpd RPMHPD_CX>;
1546 operating-points-v2 = <&qup_opp_table>;
1547 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1548 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1549 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1550 interconnect-names = "qup-core",
1551 "qup-config",
1552 "qup-memory";
1553 #address-cells = <1>;
1554 #size-cells = <0>;
1555 status = "disabled";
1556 };
1557
1558 i2c4: i2c@990000 {
1559 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = "se";
1562 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names = "default";
1564 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = "tx", "rx";
1569 power-domains = <&rpmhpd SM8250_CX>;
1570 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1571 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1572 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1573 interconnect-names = "qup-core",
1574 "qup-config",
1575 "qup-memory";
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1578 status = "disabled";
1579 };
1580
1581 spi4: spi@990000 {
1582 compatible = "qcom,geni-spi";
1583 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = "se";
1585 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = "tx", "rx";
1590 power-domains = <&rpmhpd RPMHPD_CX>;
1591 operating-points-v2 = <&qup_opp_table>;
1592 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1593 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1594 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1595 interconnect-names = "qup-core",
1596 "qup-config",
1597 "qup-memory";
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1600 status = "disabled";
1601 };
1602
1603 i2c5: i2c@994000 {
1604 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = "se";
1607 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = "tx", "rx";
1614 power-domains = <&rpmhpd SM8250_CX>;
1615 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1616 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1617 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1618 interconnect-names = "qup-core",
1619 "qup-config",
1620 "qup-memory";
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1623 status = "disabled";
1624 };
1625
1626 spi5: spi@994000 {
1627 compatible = "qcom,geni-spi";
1628 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = "se";
1630 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = "tx", "rx";
1635 power-domains = <&rpmhpd RPMHPD_CX>;
1636 operating-points-v2 = <&qup_opp_table>;
1637 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1638 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1639 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1640 interconnect-names = "qup-core",
1641 "qup-config",
1642 "qup-memory";
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1645 status = "disabled";
1646 };
1647
1648 i2c6: i2c@998000 {
1649 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = "se";
1652 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = "tx", "rx";
1659 power-domains = <&rpmhpd SM8250_CX>;
1660 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1661 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1662 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1663 interconnect-names = "qup-core",
1664 "qup-config",
1665 "qup-memory";
1666 #address-cells = <1>;
1667 #size-cells = <0>;
1668 status = "disabled";
1669 };
1670
1671 spi6: spi@998000 {
1672 compatible = "qcom,geni-spi";
1673 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = "se";
1675 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = "tx", "rx";
1680 power-domains = <&rpmhpd RPMHPD_CX>;
1681 operating-points-v2 = <&qup_opp_table>;
1682 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1683 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1684 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1685 interconnect-names = "qup-core",
1686 "qup-config",
1687 "qup-memory";
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1690 status = "disabled";
1691 };
1692
1693 uart6: serial@998000 {
1694 compatible = "qcom,geni-uart";
1695 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = "se";
1697 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains = <&rpmhpd RPMHPD_CX>;
1702 operating-points-v2 = <&qup_opp_table>;
1703 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1704 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1705 interconnect-names = "qup-core",
1706 "qup-config";
1707 status = "disabled";
1708 };
1709
1710 i2c7: i2c@99c000 {
1711 compatible = "qcom,geni-i2c";
1712 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = "se";
1714 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names = "default";
1716 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = "tx", "rx";
1721 power-domains = <&rpmhpd SM8250_CX>;
1722 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1723 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1724 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1725 interconnect-names = "qup-core",
1726 "qup-config",
1727 "qup-memory";
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1730 status = "disabled";
1731 };
1732
1733 spi7: spi@99c000 {
1734 compatible = "qcom,geni-spi";
1735 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = "se";
1737 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = "tx", "rx";
1742 power-domains = <&rpmhpd RPMHPD_CX>;
1743 operating-points-v2 = <&qup_opp_table>;
1744 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1745 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1746 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1747 interconnect-names = "qup-core",
1748 "qup-config",
1749 "qup-memory";
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1752 status = "disabled";
1753 };
1754 };
1755
1756 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1758 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>;
1770 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>;
1773 status = "disabled";
1774 };
1775
1776 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>;
1783 #size-cells = <2>;
1784 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges;
1786 status = "disabled";
1787
1788 i2c8: i2c@a80000 {
1789 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = "se";
1792 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names = "default";
1794 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = "tx", "rx";
1799 power-domains = <&rpmhpd SM8250_CX>;
1800 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1801 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1802 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1803 interconnect-names = "qup-core",
1804 "qup-config",
1805 "qup-memory";
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1808 status = "disabled";
1809 };
1810
1811 spi8: spi@a80000 {
1812 compatible = "qcom,geni-spi";
1813 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = "se";
1815 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = "tx", "rx";
1820 power-domains = <&rpmhpd RPMHPD_CX>;
1821 operating-points-v2 = <&qup_opp_table>;
1822 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1823 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1824 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1825 interconnect-names = "qup-core",
1826 "qup-config",
1827 "qup-memory";
1828 #address-cells = <1>;
1829 #size-cells = <0>;
1830 status = "disabled";
1831 };
1832
1833 i2c9: i2c@a84000 {
1834 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = "se";
1837 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names = "default";
1839 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = "tx", "rx";
1844 power-domains = <&rpmhpd SM8250_CX>;
1845 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1847 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1848 interconnect-names = "qup-core",
1849 "qup-config",
1850 "qup-memory";
1851 #address-cells = <1>;
1852 #size-cells = <0>;
1853 status = "disabled";
1854 };
1855
1856 spi9: spi@a84000 {
1857 compatible = "qcom,geni-spi";
1858 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = "se";
1860 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = "tx", "rx";
1865 power-domains = <&rpmhpd RPMHPD_CX>;
1866 operating-points-v2 = <&qup_opp_table>;
1867 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1868 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1869 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1870 interconnect-names = "qup-core",
1871 "qup-config",
1872 "qup-memory";
1873 #address-cells = <1>;
1874 #size-cells = <0>;
1875 status = "disabled";
1876 };
1877
1878 i2c10: i2c@a88000 {
1879 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = "se";
1882 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names = "default";
1884 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = "tx", "rx";
1889 power-domains = <&rpmhpd SM8250_CX>;
1890 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1891 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1892 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1893 interconnect-names = "qup-core",
1894 "qup-config",
1895 "qup-memory";
1896 #address-cells = <1>;
1897 #size-cells = <0>;
1898 status = "disabled";
1899 };
1900
1901 spi10: spi@a88000 {
1902 compatible = "qcom,geni-spi";
1903 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = "se";
1905 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = "tx", "rx";
1910 power-domains = <&rpmhpd RPMHPD_CX>;
1911 operating-points-v2 = <&qup_opp_table>;
1912 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1913 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1914 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1915 interconnect-names = "qup-core",
1916 "qup-config",
1917 "qup-memory";
1918 #address-cells = <1>;
1919 #size-cells = <0>;
1920 status = "disabled";
1921 };
1922
1923 i2c11: i2c@a8c000 {
1924 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = "se";
1927 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names = "default";
1929 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = "tx", "rx";
1934 power-domains = <&rpmhpd SM8250_CX>;
1935 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1936 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1937 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1938 interconnect-names = "qup-core",
1939 "qup-config",
1940 "qup-memory";
1941 #address-cells = <1>;
1942 #size-cells = <0>;
1943 status = "disabled";
1944 };
1945
1946 spi11: spi@a8c000 {
1947 compatible = "qcom,geni-spi";
1948 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = "se";
1950 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = "tx", "rx";
1955 power-domains = <&rpmhpd RPMHPD_CX>;
1956 operating-points-v2 = <&qup_opp_table>;
1957 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1959 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1960 interconnect-names = "qup-core",
1961 "qup-config",
1962 "qup-memory";
1963 #address-cells = <1>;
1964 #size-cells = <0>;
1965 status = "disabled";
1966 };
1967
1968 i2c12: i2c@a90000 {
1969 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = "se";
1972 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names = "default";
1974 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = "tx", "rx";
1979 power-domains = <&rpmhpd SM8250_CX>;
1980 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1981 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1982 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1983 interconnect-names = "qup-core",
1984 "qup-config",
1985 "qup-memory";
1986 #address-cells = <1>;
1987 #size-cells = <0>;
1988 status = "disabled";
1989 };
1990
1991 spi12: spi@a90000 {
1992 compatible = "qcom,geni-spi";
1993 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = "se";
1995 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = "tx", "rx";
2000 power-domains = <&rpmhpd RPMHPD_CX>;
2001 operating-points-v2 = <&qup_opp_table>;
2002 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2003 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2004 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2005 interconnect-names = "qup-core",
2006 "qup-config",
2007 "qup-memory";
2008 #address-cells = <1>;
2009 #size-cells = <0>;
2010 status = "disabled";
2011 };
2012
2013 uart12: serial@a90000 {
2014 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = "se";
2017 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names = "default";
2019 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains = <&rpmhpd RPMHPD_CX>;
2022 operating-points-v2 = <&qup_opp_table>;
2023 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2024 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2025 interconnect-names = "qup-core",
2026 "qup-config";
2027 status = "disabled";
2028 };
2029
2030 i2c13: i2c@a94000 {
2031 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = "se";
2034 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names = "default";
2036 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = "tx", "rx";
2041 power-domains = <&rpmhpd SM8250_CX>;
2042 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2043 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2044 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2045 interconnect-names = "qup-core",
2046 "qup-config",
2047 "qup-memory";
2048 #address-cells = <1>;
2049 #size-cells = <0>;
2050 status = "disabled";
2051 };
2052
2053 spi13: spi@a94000 {
2054 compatible = "qcom,geni-spi";
2055 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = "se";
2057 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = "tx", "rx";
2062 power-domains = <&rpmhpd RPMHPD_CX>;
2063 operating-points-v2 = <&qup_opp_table>;
2064 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2065 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2066 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2067 interconnect-names = "qup-core",
2068 "qup-config",
2069 "qup-memory";
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2072 status = "disabled";
2073 };
2074 };
2075
2076 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&apps_bcm_voter>;
2081 };
2082
2083 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&apps_bcm_voter>;
2088 };
2089
2090 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&apps_bcm_voter>;
2095 };
2096
2097 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&apps_bcm_voter>;
2102 };
2103
2104 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&apps_bcm_voter>;
2109 };
2110
2111 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&apps_bcm_voter>;
2116 };
2117
2118 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&apps_bcm_voter>;
2123 };
2124
2125 pcie0: pcie@1c00000 {
2126 compatible = "qcom,pcie-sm8250";
2127 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 0x100000>,
2132 <0 0x01c03000 0 0x1000>;
2133 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2134 device_type = "pci";
2135 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xff>;
2137 num-lanes = <1>;
2138
2139 #address-cells = <3>;
2140 #size-cells = <2>;
2141
2142 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144
2145 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2153 interrupt-names = "msi0",
2154 "msi1",
2155 "msi2",
2156 "msi3",
2157 "msi4",
2158 "msi5",
2159 "msi6",
2160 "msi7";
2161 #interrupt-cells = <1>;
2162 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167
2168 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe",
2177 "aux",
2178 "cfg",
2179 "bus_master",
2180 "bus_slave",
2181 "slave_q2a",
2182 "tbu",
2183 "ddrss_sf_tbu";
2184
2185 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &apps_smmu 0x1c01 0x1>;
2187
2188 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci";
2190
2191 power-domains = <&gcc PCIE_0_GDSC>;
2192
2193 phys = <&pcie0_phy>;
2194 phy-names = "pciephy";
2195
2196 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198
2199 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent;
2202
2203 status = "disabled";
2204
2205 pcieport0: pcie@0 {
2206 device_type = "pci";
2207 reg = <0x0 0x0 0x0 0x0 0x0>;
2208 bus-range = <0x01 0xff>;
2209
2210 #address-cells = <3>;
2211 #size-cells = <2>;
2212 ranges;
2213 };
2214 };
2215
2216 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 0x1000>;
2219
2220 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
2224 <&gcc GCC_PCIE_0_PIPE_CLK>;
2225 clock-names = "aux",
2226 "cfg_ahb",
2227 "ref",
2228 "refgen",
2229 "pipe";
2230
2231 clock-output-names = "pcie_0_pipe_clk";
2232 #clock-cells = <0>;
2233
2234 #phy-cells = <0>;
2235
2236 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy";
2238
2239 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates = <100000000>;
2241
2242 status = "disabled";
2243 };
2244
2245 pcie1: pcie@1c08000 {
2246 compatible = "qcom,pcie-sm8250";
2247 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 0x100000>,
2252 <0 0x01c0b000 0 0x1000>;
2253 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2254 device_type = "pci";
2255 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xff>;
2257 num-lanes = <2>;
2258
2259 #address-cells = <3>;
2260 #size-cells = <2>;
2261
2262 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264
2265 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2266 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2267 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2268 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2269 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2270 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2271 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2272 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2273 interrupt-names = "msi0",
2274 "msi1",
2275 "msi2",
2276 "msi3",
2277 "msi4",
2278 "msi5",
2279 "msi6",
2280 "msi7";
2281 #interrupt-cells = <1>;
2282 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287
2288 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe",
2298 "aux",
2299 "cfg",
2300 "bus_master",
2301 "bus_slave",
2302 "slave_q2a",
2303 "ref",
2304 "tbu",
2305 "ddrss_sf_tbu";
2306
2307 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates = <19200000>;
2309
2310 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &apps_smmu 0x1c81 0x1>;
2312
2313 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci";
2315
2316 power-domains = <&gcc PCIE_1_GDSC>;
2317
2318 phys = <&pcie1_phy>;
2319 phy-names = "pciephy";
2320
2321 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323
2324 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent;
2327
2328 status = "disabled";
2329
2330 pcie@0 {
2331 device_type = "pci";
2332 reg = <0x0 0x0 0x0 0x0 0x0>;
2333 bus-range = <0x01 0xff>;
2334
2335 #address-cells = <3>;
2336 #size-cells = <2>;
2337 ranges;
2338 };
2339 };
2340
2341 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 0x1000>;
2344
2345 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2349 <&gcc GCC_PCIE_1_PIPE_CLK>;
2350 clock-names = "aux",
2351 "cfg_ahb",
2352 "ref",
2353 "refgen",
2354 "pipe";
2355
2356 clock-output-names = "pcie_1_pipe_clk";
2357 #clock-cells = <0>;
2358
2359 #phy-cells = <0>;
2360
2361 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy";
2363
2364 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates = <100000000>;
2366
2367 status = "disabled";
2368 };
2369
2370 pcie2: pcie@1c10000 {
2371 compatible = "qcom,pcie-sm8250";
2372 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 0x100000>,
2377 <0 0x01c13000 0 0x1000>;
2378 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2379 device_type = "pci";
2380 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xff>;
2382 num-lanes = <2>;
2383
2384 #address-cells = <3>;
2385 #size-cells = <2>;
2386
2387 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389
2390 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
2391 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2392 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2395 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
2396 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
2397 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
2398 interrupt-names = "msi0",
2399 "msi1",
2400 "msi2",
2401 "msi3",
2402 "msi4",
2403 "msi5",
2404 "msi6",
2405 "msi7";
2406 #interrupt-cells = <1>;
2407 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412
2413 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe",
2423 "aux",
2424 "cfg",
2425 "bus_master",
2426 "bus_slave",
2427 "slave_q2a",
2428 "ref",
2429 "tbu",
2430 "ddrss_sf_tbu";
2431
2432 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates = <19200000>;
2434
2435 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &apps_smmu 0x1d01 0x1>;
2437
2438 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci";
2440
2441 power-domains = <&gcc PCIE_2_GDSC>;
2442
2443 phys = <&pcie2_phy>;
2444 phy-names = "pciephy";
2445
2446 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448
2449 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent;
2452
2453 status = "disabled";
2454
2455 pcie@0 {
2456 device_type = "pci";
2457 reg = <0x0 0x0 0x0 0x0 0x0>;
2458 bus-range = <0x01 0xff>;
2459
2460 #address-cells = <3>;
2461 #size-cells = <2>;
2462 ranges;
2463 };
2464 };
2465
2466 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 0x1000>;
2469
2470 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2474 <&gcc GCC_PCIE_2_PIPE_CLK>;
2475 clock-names = "aux",
2476 "cfg_ahb",
2477 "ref",
2478 "refgen",
2479 "pipe";
2480
2481 clock-output-names = "pcie_2_pipe_clk";
2482 #clock-cells = <0>;
2483
2484 #phy-cells = <0>;
2485
2486 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy";
2488
2489 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates = <100000000>;
2491
2492 status = "disabled";
2493 };
2494
2495 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy>;
2501 phy-names = "ufsphy";
2502 lanes-per-direction = <2>;
2503 #reset-cells = <1>;
2504 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst";
2506
2507 power-domains = <&gcc UFS_PHY_GDSC>;
2508
2509 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510
2511 clock-names =
2512 "core_clk",
2513 "bus_aggr_clk",
2514 "iface_clk",
2515 "core_clk_unipro",
2516 "ref_clk",
2517 "tx_lane0_sync_clk",
2518 "rx_lane0_sync_clk",
2519 "rx_lane1_sync_clk";
2520 clocks =
2521 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529
2530 operating-points-v2 = <&ufs_opp_table>;
2531
2532 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2533 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2534 interconnect-names = "ufs-ddr", "cpu-ufs";
2535
2536 status = "disabled";
2537
2538 ufs_opp_table: opp-table {
2539 compatible = "operating-points-v2";
2540
2541 opp-37500000 {
2542 opp-hz = /bits/ 64 <37500000>,
2543 /bits/ 64 <0>,
2544 /bits/ 64 <0>,
2545 /bits/ 64 <37500000>,
2546 /bits/ 64 <0>,
2547 /bits/ 64 <0>,
2548 /bits/ 64 <0>,
2549 /bits/ 64 <0>;
2550 required-opps = <&rpmhpd_opp_low_svs>;
2551 };
2552
2553 opp-300000000 {
2554 opp-hz = /bits/ 64 <300000000>,
2555 /bits/ 64 <0>,
2556 /bits/ 64 <0>,
2557 /bits/ 64 <300000000>,
2558 /bits/ 64 <0>,
2559 /bits/ 64 <0>,
2560 /bits/ 64 <0>,
2561 /bits/ 64 <0>;
2562 required-opps = <&rpmhpd_opp_nom>;
2563 };
2564 };
2565 };
2566
2567 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 0x1000>;
2570
2571 clocks = <&rpmhcc RPMH_CXO_CLK>,
2572 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2573 <&gcc GCC_UFS_1X_CLKREF_EN>;
2574 clock-names = "ref",
2575 "ref_aux",
2576 "qref";
2577
2578 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy";
2580
2581 power-domains = <&gcc UFS_PHY_GDSC>;
2582
2583 #phy-cells = <0>;
2584
2585 status = "disabled";
2586 };
2587
2588 cryptobam: dma-controller@1dc4000 {
2589 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2590 reg = <0 0x01dc4000 0 0x24000>;
2591 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2592 #dma-cells = <1>;
2593 qcom,ee = <0>;
2594 qcom,controlled-remotely;
2595 num-channels = <8>;
2596 qcom,num-ees = <2>;
2597 iommus = <&apps_smmu 0x592 0x0000>,
2598 <&apps_smmu 0x598 0x0000>,
2599 <&apps_smmu 0x599 0x0000>,
2600 <&apps_smmu 0x59f 0x0000>,
2601 <&apps_smmu 0x586 0x0011>,
2602 <&apps_smmu 0x596 0x0011>;
2603 };
2604
2605 crypto: crypto@1dfa000 {
2606 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2607 reg = <0 0x01dfa000 0 0x6000>;
2608 dmas = <&cryptobam 4>, <&cryptobam 5>;
2609 dma-names = "rx", "tx";
2610 iommus = <&apps_smmu 0x592 0x0000>,
2611 <&apps_smmu 0x598 0x0000>,
2612 <&apps_smmu 0x599 0x0000>,
2613 <&apps_smmu 0x59f 0x0000>,
2614 <&apps_smmu 0x586 0x0011>,
2615 <&apps_smmu 0x596 0x0011>;
2616 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2617 interconnect-names = "memory";
2618 };
2619
2620 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>;
2624 };
2625
2626 tcsr: syscon@1fc0000 {
2627 compatible = "qcom,sm8250-tcsr", "syscon";
2628 reg = <0x0 0x1fc0000 0x0 0x30000>;
2629 };
2630
2631 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2635 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2636 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2638 <&vamacro>;
2639
2640 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2641
2642 #clock-cells = <0>;
2643 clock-output-names = "mclk";
2644 #sound-dai-cells = <1>;
2645
2646 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr_active>;
2648
2649 status = "disabled";
2650 };
2651
2652 swr0: soundwire@3250000 {
2653 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>;
2657 clock-names = "iface";
2658
2659 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6>;
2661
2662 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666
2667 #sound-dai-cells = <1>;
2668 #address-cells = <2>;
2669 #size-cells = <0>;
2670
2671 status = "disabled";
2672 };
2673
2674 vamacro: codec@3370000 {
2675 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2678 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680
2681 clock-names = "mclk", "macro", "dcodec";
2682
2683 #clock-cells = <0>;
2684 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1>;
2686 };
2687
2688 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 0x1000>;
2693 status = "disabled";
2694
2695 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>;
2700
2701 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702
2703 #clock-cells = <0>;
2704 clock-output-names = "mclk";
2705 #sound-dai-cells = <1>;
2706 };
2707
2708 swr1: soundwire@3210000 {
2709 reg = <0 0x03210000 0 0x2000>;
2710 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled";
2712 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>;
2714 clock-names = "iface";
2715 label = "RX";
2716 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5>;
2718
2719 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2728
2729 #sound-dai-cells = <1>;
2730 #address-cells = <2>;
2731 #size-cells = <0>;
2732 };
2733
2734 txmacro: txmacro@3220000 {
2735 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 0x1000>;
2739 status = "disabled";
2740
2741 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>;
2746
2747 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748
2749 #clock-cells = <0>;
2750 clock-output-names = "mclk";
2751 #sound-dai-cells = <1>;
2752 };
2753
2754 /* tx macro */
2755 swr2: soundwire@3230000 {
2756 reg = <0 0x03230000 0 0x2000>;
2757 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "core";
2760 status = "disabled";
2761
2762 clocks = <&txmacro>;
2763 clock-names = "iface";
2764 label = "TX";
2765
2766 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1>;
2778 #address-cells = <2>;
2779 #size-cells = <0>;
2780 };
2781
2782 lpass_tlmm: pinctrl@33c0000 {
2783 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller;
2787 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789
2790 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", "audio";
2793
2794 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins {
2796 pins = "gpio10";
2797 function = "wsa_swr_clk";
2798 drive-strength = <2>;
2799 slew-rate = <1>;
2800 bias-disable;
2801 };
2802
2803 data-pins {
2804 pins = "gpio11";
2805 function = "wsa_swr_data";
2806 drive-strength = <2>;
2807 slew-rate = <1>;
2808 bias-bus-hold;
2809 };
2810 };
2811
2812 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins {
2814 pins = "gpio10";
2815 function = "wsa_swr_clk";
2816 drive-strength = <2>;
2817 bias-pull-down;
2818 };
2819
2820 data-pins {
2821 pins = "gpio11";
2822 function = "wsa_swr_data";
2823 drive-strength = <2>;
2824 bias-pull-down;
2825 };
2826 };
2827
2828 dmic01_active: dmic01-active-state {
2829 clk-pins {
2830 pins = "gpio6";
2831 function = "dmic1_clk";
2832 drive-strength = <8>;
2833 output-high;
2834 };
2835 data-pins {
2836 pins = "gpio7";
2837 function = "dmic1_data";
2838 drive-strength = <8>;
2839 };
2840 };
2841
2842 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins {
2844 pins = "gpio6";
2845 function = "dmic1_clk";
2846 drive-strength = <2>;
2847 bias-disable;
2848 output-low;
2849 };
2850
2851 data-pins {
2852 pins = "gpio7";
2853 function = "dmic1_data";
2854 drive-strength = <2>;
2855 bias-pull-down;
2856 };
2857 };
2858
2859 rx_swr_active: rx-swr-active-state {
2860 clk-pins {
2861 pins = "gpio3";
2862 function = "swr_rx_clk";
2863 drive-strength = <2>;
2864 slew-rate = <1>;
2865 bias-disable;
2866 };
2867
2868 data-pins {
2869 pins = "gpio4", "gpio5";
2870 function = "swr_rx_data";
2871 drive-strength = <2>;
2872 slew-rate = <1>;
2873 bias-bus-hold;
2874 };
2875 };
2876
2877 tx_swr_active: tx-swr-active-state {
2878 clk-pins {
2879 pins = "gpio0";
2880 function = "swr_tx_clk";
2881 drive-strength = <2>;
2882 slew-rate = <1>;
2883 bias-disable;
2884 };
2885
2886 data-pins {
2887 pins = "gpio1", "gpio2";
2888 function = "swr_tx_data";
2889 drive-strength = <2>;
2890 slew-rate = <1>;
2891 bias-bus-hold;
2892 };
2893 };
2894
2895 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins {
2897 pins = "gpio0";
2898 function = "swr_tx_clk";
2899 drive-strength = <2>;
2900 bias-pull-down;
2901 };
2902
2903 data1-pins {
2904 pins = "gpio1";
2905 function = "swr_tx_data";
2906 drive-strength = <2>;
2907 bias-bus-hold;
2908 };
2909
2910 data2-pins {
2911 pins = "gpio2";
2912 function = "swr_tx_data";
2913 drive-strength = <2>;
2914 bias-pull-down;
2915 };
2916 };
2917 };
2918
2919 gpu: gpu@3d00000 {
2920 compatible = "qcom,adreno-650.2",
2921 "qcom,adreno";
2922
2923 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0_reg_memory";
2925
2926 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927
2928 iommus = <&adreno_smmu 0 0x401>;
2929
2930 operating-points-v2 = <&gpu_opp_table>;
2931
2932 qcom,gmu = <&gmu>;
2933
2934 nvmem-cells = <&gpu_speed_bin>;
2935 nvmem-cell-names = "speed_bin";
2936 #cooling-cells = <2>;
2937
2938 status = "disabled";
2939
2940 zap-shader {
2941 memory-region = <&gpu_mem>;
2942 };
2943
2944 gpu_opp_table: opp-table {
2945 compatible = "operating-points-v2";
2946
2947 opp-670000000 {
2948 opp-hz = /bits/ 64 <670000000>;
2949 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-supported-hw = <0xa>;
2951 };
2952
2953 opp-587000000 {
2954 opp-hz = /bits/ 64 <587000000>;
2955 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-supported-hw = <0xb>;
2957 };
2958
2959 opp-525000000 {
2960 opp-hz = /bits/ 64 <525000000>;
2961 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-supported-hw = <0xf>;
2963 };
2964
2965 opp-490000000 {
2966 opp-hz = /bits/ 64 <490000000>;
2967 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-supported-hw = <0xf>;
2969 };
2970
2971 opp-441600000 {
2972 opp-hz = /bits/ 64 <441600000>;
2973 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-supported-hw = <0xf>;
2975 };
2976
2977 opp-400000000 {
2978 opp-hz = /bits/ 64 <400000000>;
2979 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-supported-hw = <0xf>;
2981 };
2982
2983 opp-305000000 {
2984 opp-hz = /bits/ 64 <305000000>;
2985 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-supported-hw = <0xf>;
2987 };
2988 };
2989 };
2990
2991 gmu: gmu@3d6a000 {
2992 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993
2994 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999
3000 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hfi", "gmu";
3003
3004 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010
3011 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = "cx", "gx";
3014
3015 iommus = <&adreno_smmu 5 0x400>;
3016
3017 operating-points-v2 = <&gmu_opp_table>;
3018
3019 status = "disabled";
3020
3021 gmu_opp_table: opp-table {
3022 compatible = "operating-points-v2";
3023
3024 opp-200000000 {
3025 opp-hz = /bits/ 64 <200000000>;
3026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 };
3028 };
3029 };
3030
3031 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcxo",
3038 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>;
3041 #reset-cells = <1>;
3042 #power-domain-cells = <1>;
3043 };
3044
3045 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3047 "qcom,smmu-500", "arm,mmu-500";
3048 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>;
3050 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", "bus", "iface";
3065
3066 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent;
3068 };
3069
3070 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 0x4000>;
3073
3074 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3075 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wdog", "fatal", "ready",
3080 "handover", "stop-ack";
3081
3082 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo";
3084
3085 power-domains = <&rpmhpd RPMHPD_LCX>,
3086 <&rpmhpd RPMHPD_LMX>;
3087 power-domain-names = "lcx", "lmx";
3088
3089 memory-region = <&slpi_mem>;
3090
3091 qcom,qmp = <&aoss_qmp>;
3092
3093 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names = "stop";
3095
3096 status = "disabled";
3097
3098 glink-edge {
3099 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104
3105 label = "slpi";
3106 qcom,remote-pid = <3>;
3107
3108 fastrpc {
3109 compatible = "qcom,fastrpc";
3110 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label = "sdsp";
3112 qcom,non-secure-domain;
3113 #address-cells = <1>;
3114 #size-cells = <0>;
3115
3116 compute-cb@1 {
3117 compatible = "qcom,fastrpc-compute-cb";
3118 reg = <1>;
3119 iommus = <&apps_smmu 0x0541 0x0>;
3120 };
3121
3122 compute-cb@2 {
3123 compatible = "qcom,fastrpc-compute-cb";
3124 reg = <2>;
3125 iommus = <&apps_smmu 0x0542 0x0>;
3126 };
3127
3128 compute-cb@3 {
3129 compatible = "qcom,fastrpc-compute-cb";
3130 reg = <3>;
3131 iommus = <&apps_smmu 0x0543 0x0>;
3132 /* note: shared-cb = <4> in downstream */
3133 };
3134 };
3135 };
3136 };
3137
3138 stm@6002000 {
3139 compatible = "arm,coresight-stm", "arm,primecell";
3140 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3141 reg-names = "stm-base", "stm-stimulus-base";
3142
3143 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pclk";
3145
3146 out-ports {
3147 port {
3148 stm_out: endpoint {
3149 remote-endpoint = <&funnel0_in7>;
3150 };
3151 };
3152 };
3153 };
3154
3155 tpda@6004000 {
3156 compatible = "qcom,coresight-tpda", "arm,primecell";
3157 reg = <0 0x06004000 0 0x1000>;
3158
3159 clocks = <&aoss_qmp>;
3160 clock-names = "apb_pclk";
3161
3162 out-ports {
3163
3164 port {
3165 tpda_out_funnel_qatb: endpoint {
3166 remote-endpoint = <&funnel_qatb_in_tpda>;
3167 };
3168 };
3169 };
3170
3171 in-ports {
3172 #address-cells = <1>;
3173 #size-cells = <0>;
3174
3175 port@9 {
3176 reg = <9>;
3177 tpda_9_in_tpdm_mm: endpoint {
3178 remote-endpoint = <&tpdm_mm_out_tpda9>;
3179 };
3180 };
3181
3182 port@17 {
3183 reg = <23>;
3184 tpda_23_in_tpdm_prng: endpoint {
3185 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3186 };
3187 };
3188 };
3189 };
3190
3191 funnel@6005000 {
3192 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3193 reg = <0 0x06005000 0 0x1000>;
3194
3195 clocks = <&aoss_qmp>;
3196 clock-names = "apb_pclk";
3197
3198 out-ports {
3199 port {
3200 funnel_qatb_out_funnel_in0: endpoint {
3201 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3202 };
3203 };
3204 };
3205
3206 in-ports {
3207 port {
3208 funnel_qatb_in_tpda: endpoint {
3209 remote-endpoint = <&tpda_out_funnel_qatb>;
3210 };
3211 };
3212 };
3213 };
3214
3215 funnel@6041000 {
3216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3217 reg = <0 0x06041000 0 0x1000>;
3218
3219 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pclk";
3221
3222 out-ports {
3223 port {
3224 funnel_in0_out_funnel_merg: endpoint {
3225 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3226 };
3227 };
3228 };
3229
3230 in-ports {
3231 #address-cells = <1>;
3232 #size-cells = <0>;
3233
3234 port@6 {
3235 reg = <6>;
3236 funnel_in0_in_funnel_qatb: endpoint {
3237 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3238 };
3239 };
3240
3241 port@7 {
3242 reg = <7>;
3243 funnel0_in7: endpoint {
3244 remote-endpoint = <&stm_out>;
3245 };
3246 };
3247 };
3248 };
3249
3250 funnel@6042000 {
3251 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3252 reg = <0 0x06042000 0 0x1000>;
3253
3254 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pclk";
3256
3257 out-ports {
3258 port {
3259 funnel_in1_out_funnel_merg: endpoint {
3260 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3261 };
3262 };
3263 };
3264
3265 in-ports {
3266 #address-cells = <1>;
3267 #size-cells = <0>;
3268
3269 port@4 {
3270 reg = <4>;
3271 funnel_in1_in_funnel_apss_merg: endpoint {
3272 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3273 };
3274 };
3275 };
3276 };
3277
3278 funnel@6045000 {
3279 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 reg = <0 0x06045000 0 0x1000>;
3281
3282 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pclk";
3284
3285 out-ports {
3286 port {
3287 funnel_merg_out_funnel_swao: endpoint {
3288 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3289 };
3290 };
3291 };
3292
3293 in-ports {
3294 #address-cells = <1>;
3295 #size-cells = <0>;
3296
3297 port@0 {
3298 reg = <0>;
3299 funnel_merg_in_funnel_in0: endpoint {
3300 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3301 };
3302 };
3303
3304 port@1 {
3305 reg = <1>;
3306 funnel_merg_in_funnel_in1: endpoint {
3307 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3308 };
3309 };
3310 };
3311 };
3312
3313 replicator@6046000 {
3314 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3315 reg = <0 0x06046000 0 0x1000>;
3316
3317 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pclk";
3319
3320 out-ports {
3321 port {
3322 replicator_out: endpoint {
3323 remote-endpoint = <&etr_in>;
3324 };
3325 };
3326 };
3327
3328 in-ports {
3329 port {
3330 replicator_cx_in_swao_out: endpoint {
3331 remote-endpoint = <&replicator_swao_out_cx_in>;
3332 };
3333 };
3334 };
3335 };
3336
3337 etr@6048000 {
3338 compatible = "arm,coresight-tmc", "arm,primecell";
3339 reg = <0 0x06048000 0 0x1000>;
3340
3341 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pclk";
3343 arm,scatter-gather;
3344
3345 in-ports {
3346 port {
3347 etr_in: endpoint {
3348 remote-endpoint = <&replicator_out>;
3349 };
3350 };
3351 };
3352 };
3353
3354 tpdm@684c000 {
3355 compatible = "qcom,coresight-tpdm", "arm,primecell";
3356 reg = <0 0x0684c000 0 0x1000>;
3357
3358 clocks = <&aoss_qmp>;
3359 clock-names = "apb_pclk";
3360
3361 out-ports {
3362 port {
3363 tpdm_prng_out_tpda_23: endpoint {
3364 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3365 };
3366 };
3367 };
3368 };
3369
3370 funnel@6b04000 {
3371 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphid = <0x000bb908>;
3373
3374 reg = <0 0x06b04000 0 0x1000>;
3375
3376 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pclk";
3378
3379 out-ports {
3380 port {
3381 funnel_swao_out_etf: endpoint {
3382 remote-endpoint = <&etf_in_funnel_swao_out>;
3383 };
3384 };
3385 };
3386
3387 in-ports {
3388 #address-cells = <1>;
3389 #size-cells = <0>;
3390
3391 port@7 {
3392 reg = <7>;
3393 funnel_swao_in_funnel_merg: endpoint {
3394 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3395 };
3396 };
3397 };
3398 };
3399
3400 etf@6b05000 {
3401 compatible = "arm,coresight-tmc", "arm,primecell";
3402 reg = <0 0x06b05000 0 0x1000>;
3403
3404 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pclk";
3406
3407 out-ports {
3408 port {
3409 etf_out: endpoint {
3410 remote-endpoint = <&replicator_in>;
3411 };
3412 };
3413 };
3414
3415 in-ports {
3416
3417 port {
3418 etf_in_funnel_swao_out: endpoint {
3419 remote-endpoint = <&funnel_swao_out_etf>;
3420 };
3421 };
3422 };
3423 };
3424
3425 replicator@6b06000 {
3426 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3427 reg = <0 0x06b06000 0 0x1000>;
3428
3429 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pclk";
3431
3432 out-ports {
3433 port {
3434 replicator_swao_out_cx_in: endpoint {
3435 remote-endpoint = <&replicator_cx_in_swao_out>;
3436 };
3437 };
3438 };
3439
3440 in-ports {
3441 port {
3442 replicator_in: endpoint {
3443 remote-endpoint = <&etf_out>;
3444 };
3445 };
3446 };
3447 };
3448
3449 tpdm@6c08000 {
3450 compatible = "qcom,coresight-tpdm", "arm,primecell";
3451 reg = <0 0x06c08000 0 0x1000>;
3452
3453 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pclk";
3455
3456 out-ports {
3457 port {
3458 tpdm_mm_out_funnel_dl_mm: endpoint {
3459 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3460 };
3461 };
3462 };
3463 };
3464
3465 funnel@6c0b000 {
3466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3467 reg = <0 0x06c0b000 0 0x1000>;
3468
3469 clocks = <&aoss_qmp>;
3470 clock-names = "apb_pclk";
3471
3472 out-ports {
3473 port {
3474 funnel_dl_mm_out_funnel_dl_center: endpoint {
3475 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3476 };
3477 };
3478 };
3479
3480 in-ports {
3481 #address-cells = <1>;
3482 #size-cells = <0>;
3483
3484 port@3 {
3485 reg = <3>;
3486 funnel_dl_mm_in_tpdm_mm: endpoint {
3487 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3488 };
3489 };
3490 };
3491 };
3492
3493 funnel@6c2d000 {
3494 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3495 reg = <0 0x06c2d000 0 0x1000>;
3496
3497 clocks = <&aoss_qmp>;
3498 clock-names = "apb_pclk";
3499
3500 out-ports {
3501 port {
3502 tpdm_mm_out_tpda9: endpoint {
3503 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3504 };
3505 };
3506 };
3507
3508 in-ports {
3509 #address-cells = <1>;
3510 #size-cells = <0>;
3511
3512 port@2 {
3513 reg = <2>;
3514 funnel_dl_center_in_funnel_dl_mm: endpoint {
3515 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3516 };
3517 };
3518 };
3519 };
3520
3521 etm@7040000 {
3522 compatible = "arm,coresight-etm4x", "arm,primecell";
3523 reg = <0 0x07040000 0 0x1000>;
3524
3525 cpu = <&CPU0>;
3526
3527 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pclk";
3529 arm,coresight-loses-context-with-cpu;
3530
3531 out-ports {
3532 port {
3533 etm0_out: endpoint {
3534 remote-endpoint = <&apss_funnel_in0>;
3535 };
3536 };
3537 };
3538 };
3539
3540 etm@7140000 {
3541 compatible = "arm,coresight-etm4x", "arm,primecell";
3542 reg = <0 0x07140000 0 0x1000>;
3543
3544 cpu = <&CPU1>;
3545
3546 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pclk";
3548 arm,coresight-loses-context-with-cpu;
3549
3550 out-ports {
3551 port {
3552 etm1_out: endpoint {
3553 remote-endpoint = <&apss_funnel_in1>;
3554 };
3555 };
3556 };
3557 };
3558
3559 etm@7240000 {
3560 compatible = "arm,coresight-etm4x", "arm,primecell";
3561 reg = <0 0x07240000 0 0x1000>;
3562
3563 cpu = <&CPU2>;
3564
3565 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pclk";
3567 arm,coresight-loses-context-with-cpu;
3568
3569 out-ports {
3570 port {
3571 etm2_out: endpoint {
3572 remote-endpoint = <&apss_funnel_in2>;
3573 };
3574 };
3575 };
3576 };
3577
3578 etm@7340000 {
3579 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 reg = <0 0x07340000 0 0x1000>;
3581
3582 cpu = <&CPU3>;
3583
3584 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pclk";
3586 arm,coresight-loses-context-with-cpu;
3587
3588 out-ports {
3589 port {
3590 etm3_out: endpoint {
3591 remote-endpoint = <&apss_funnel_in3>;
3592 };
3593 };
3594 };
3595 };
3596
3597 etm@7440000 {
3598 compatible = "arm,coresight-etm4x", "arm,primecell";
3599 reg = <0 0x07440000 0 0x1000>;
3600
3601 cpu = <&CPU4>;
3602
3603 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pclk";
3605 arm,coresight-loses-context-with-cpu;
3606
3607 out-ports {
3608 port {
3609 etm4_out: endpoint {
3610 remote-endpoint = <&apss_funnel_in4>;
3611 };
3612 };
3613 };
3614 };
3615
3616 etm@7540000 {
3617 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 reg = <0 0x07540000 0 0x1000>;
3619
3620 cpu = <&CPU5>;
3621
3622 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pclk";
3624 arm,coresight-loses-context-with-cpu;
3625
3626 out-ports {
3627 port {
3628 etm5_out: endpoint {
3629 remote-endpoint = <&apss_funnel_in5>;
3630 };
3631 };
3632 };
3633 };
3634
3635 etm@7640000 {
3636 compatible = "arm,coresight-etm4x", "arm,primecell";
3637 reg = <0 0x07640000 0 0x1000>;
3638
3639 cpu = <&CPU6>;
3640
3641 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pclk";
3643 arm,coresight-loses-context-with-cpu;
3644
3645 out-ports {
3646 port {
3647 etm6_out: endpoint {
3648 remote-endpoint = <&apss_funnel_in6>;
3649 };
3650 };
3651 };
3652 };
3653
3654 etm@7740000 {
3655 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07740000 0 0x1000>;
3657
3658 cpu = <&CPU7>;
3659
3660 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pclk";
3662 arm,coresight-loses-context-with-cpu;
3663
3664 out-ports {
3665 port {
3666 etm7_out: endpoint {
3667 remote-endpoint = <&apss_funnel_in7>;
3668 };
3669 };
3670 };
3671 };
3672
3673 funnel@7800000 {
3674 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3675 reg = <0 0x07800000 0 0x1000>;
3676
3677 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pclk";
3679
3680 out-ports {
3681 port {
3682 funnel_apss_out_funnel_apss_merg: endpoint {
3683 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3684 };
3685 };
3686 };
3687
3688 in-ports {
3689 #address-cells = <1>;
3690 #size-cells = <0>;
3691
3692 port@0 {
3693 reg = <0>;
3694 apss_funnel_in0: endpoint {
3695 remote-endpoint = <&etm0_out>;
3696 };
3697 };
3698
3699 port@1 {
3700 reg = <1>;
3701 apss_funnel_in1: endpoint {
3702 remote-endpoint = <&etm1_out>;
3703 };
3704 };
3705
3706 port@2 {
3707 reg = <2>;
3708 apss_funnel_in2: endpoint {
3709 remote-endpoint = <&etm2_out>;
3710 };
3711 };
3712
3713 port@3 {
3714 reg = <3>;
3715 apss_funnel_in3: endpoint {
3716 remote-endpoint = <&etm3_out>;
3717 };
3718 };
3719
3720 port@4 {
3721 reg = <4>;
3722 apss_funnel_in4: endpoint {
3723 remote-endpoint = <&etm4_out>;
3724 };
3725 };
3726
3727 port@5 {
3728 reg = <5>;
3729 apss_funnel_in5: endpoint {
3730 remote-endpoint = <&etm5_out>;
3731 };
3732 };
3733
3734 port@6 {
3735 reg = <6>;
3736 apss_funnel_in6: endpoint {
3737 remote-endpoint = <&etm6_out>;
3738 };
3739 };
3740
3741 port@7 {
3742 reg = <7>;
3743 apss_funnel_in7: endpoint {
3744 remote-endpoint = <&etm7_out>;
3745 };
3746 };
3747 };
3748 };
3749
3750 funnel@7810000 {
3751 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3752 reg = <0 0x07810000 0 0x1000>;
3753
3754 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pclk";
3756
3757 out-ports {
3758 port {
3759 funnel_apss_merg_out_funnel_in1: endpoint {
3760 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3761 };
3762 };
3763 };
3764
3765 in-ports {
3766 port {
3767 funnel_apss_merg_in_funnel_apss: endpoint {
3768 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3769 };
3770 };
3771 };
3772 };
3773
3774 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 0x10000>;
3777
3778 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3779 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wdog", "fatal", "ready",
3784 "handover", "stop-ack";
3785
3786 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo";
3788
3789 power-domains = <&rpmhpd RPMHPD_CX>;
3790
3791 memory-region = <&cdsp_mem>;
3792
3793 qcom,qmp = <&aoss_qmp>;
3794
3795 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names = "stop";
3797
3798 status = "disabled";
3799
3800 glink-edge {
3801 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806
3807 label = "cdsp";
3808 qcom,remote-pid = <5>;
3809
3810 fastrpc {
3811 compatible = "qcom,fastrpc";
3812 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label = "cdsp";
3814 qcom,non-secure-domain;
3815 #address-cells = <1>;
3816 #size-cells = <0>;
3817
3818 compute-cb@1 {
3819 compatible = "qcom,fastrpc-compute-cb";
3820 reg = <1>;
3821 iommus = <&apps_smmu 0x1001 0x0460>;
3822 };
3823
3824 compute-cb@2 {
3825 compatible = "qcom,fastrpc-compute-cb";
3826 reg = <2>;
3827 iommus = <&apps_smmu 0x1002 0x0460>;
3828 };
3829
3830 compute-cb@3 {
3831 compatible = "qcom,fastrpc-compute-cb";
3832 reg = <3>;
3833 iommus = <&apps_smmu 0x1003 0x0460>;
3834 };
3835
3836 compute-cb@4 {
3837 compatible = "qcom,fastrpc-compute-cb";
3838 reg = <4>;
3839 iommus = <&apps_smmu 0x1004 0x0460>;
3840 };
3841
3842 compute-cb@5 {
3843 compatible = "qcom,fastrpc-compute-cb";
3844 reg = <5>;
3845 iommus = <&apps_smmu 0x1005 0x0460>;
3846 };
3847
3848 compute-cb@6 {
3849 compatible = "qcom,fastrpc-compute-cb";
3850 reg = <6>;
3851 iommus = <&apps_smmu 0x1006 0x0460>;
3852 };
3853
3854 compute-cb@7 {
3855 compatible = "qcom,fastrpc-compute-cb";
3856 reg = <7>;
3857 iommus = <&apps_smmu 0x1007 0x0460>;
3858 };
3859
3860 compute-cb@8 {
3861 compatible = "qcom,fastrpc-compute-cb";
3862 reg = <8>;
3863 iommus = <&apps_smmu 0x1008 0x0460>;
3864 };
3865
3866 /* note: secure cb9 in downstream */
3867 };
3868 };
3869 };
3870
3871 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled";
3876 #phy-cells = <0>;
3877
3878 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref";
3880
3881 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 };
3883
3884 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled";
3889 #phy-cells = <0>;
3890
3891 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref";
3893
3894 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 };
3896
3897 usb_1_qmpphy: phy@88e8000 {
3898 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 0x3000>;
3900 status = "disabled";
3901
3902 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3905 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3906 clock-names = "aux",
3907 "ref",
3908 "com_aux",
3909 "usb3_pipe";
3910
3911 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", "common";
3914
3915 #clock-cells = <1>;
3916 #phy-cells = <1>;
3917
3918 orientation-switch;
3919
3920 ports {
3921 #address-cells = <1>;
3922 #size-cells = <0>;
3923
3924 port@0 {
3925 reg = <0>;
3926 usb_1_qmpphy_out: endpoint {};
3927 };
3928
3929 port@1 {
3930 reg = <1>;
3931
3932 usb_1_qmpphy_usb_ss_in: endpoint {
3933 remote-endpoint = <&usb_1_dwc3_ss_out>;
3934 };
3935 };
3936
3937 port@2 {
3938 reg = <2>;
3939
3940 usb_1_qmpphy_dp_in: endpoint {};
3941 };
3942 };
3943 };
3944
3945 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 0x1000>;
3948
3949 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3950 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3952 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3953 clock-names = "aux",
3954 "ref",
3955 "com_aux",
3956 "pipe";
3957 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3958 #clock-cells = <0>;
3959 #phy-cells = <0>;
3960
3961 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3962 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3963 reset-names = "phy",
3964 "phy_phy";
3965
3966 status = "disabled";
3967 };
3968
3969 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 0x1000>;
3972
3973 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc_irq", "pwr_irq";
3976
3977 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpmhpd RPMHPD_CX>;
3985 operating-points-v2 = <&sdhc2_opp_table>;
3986
3987 status = "disabled";
3988
3989 sdhc2_opp_table: opp-table {
3990 compatible = "operating-points-v2";
3991
3992 opp-19200000 {
3993 opp-hz = /bits/ 64 <19200000>;
3994 required-opps = <&rpmhpd_opp_min_svs>;
3995 };
3996
3997 opp-50000000 {
3998 opp-hz = /bits/ 64 <50000000>;
3999 required-opps = <&rpmhpd_opp_low_svs>;
4000 };
4001
4002 opp-100000000 {
4003 opp-hz = /bits/ 64 <100000000>;
4004 required-opps = <&rpmhpd_opp_svs>;
4005 };
4006
4007 opp-202000000 {
4008 opp-hz = /bits/ 64 <202000000>;
4009 required-opps = <&rpmhpd_opp_svs_l1>;
4010 };
4011 };
4012 };
4013
4014 pmu@9091000 {
4015 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4016 reg = <0 0x09091000 0 0x1000>;
4017
4018 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4019
4020 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
4021
4022 operating-points-v2 = <&llcc_bwmon_opp_table>;
4023
4024 llcc_bwmon_opp_table: opp-table {
4025 compatible = "operating-points-v2";
4026
4027 opp-800000 {
4028 opp-peak-kBps = <(200 * 4 * 1000)>;
4029 };
4030
4031 opp-1200000 {
4032 opp-peak-kBps = <(300 * 4 * 1000)>;
4033 };
4034
4035 opp-1804000 {
4036 opp-peak-kBps = <(451 * 4 * 1000)>;
4037 };
4038
4039 opp-2188000 {
4040 opp-peak-kBps = <(547 * 4 * 1000)>;
4041 };
4042
4043 opp-2724000 {
4044 opp-peak-kBps = <(681 * 4 * 1000)>;
4045 };
4046
4047 opp-3072000 {
4048 opp-peak-kBps = <(768 * 4 * 1000)>;
4049 };
4050
4051 opp-4068000 {
4052 opp-peak-kBps = <(1017 * 4 * 1000)>;
4053 };
4054
4055 /* 1353 MHz, LPDDR4X */
4056
4057 opp-6220000 {
4058 opp-peak-kBps = <(1555 * 4 * 1000)>;
4059 };
4060
4061 opp-7216000 {
4062 opp-peak-kBps = <(1804 * 4 * 1000)>;
4063 };
4064
4065 opp-8368000 {
4066 opp-peak-kBps = <(2092 * 4 * 1000)>;
4067 };
4068
4069 /* LPDDR5 */
4070 opp-10944000 {
4071 opp-peak-kBps = <(2736 * 4 * 1000)>;
4072 };
4073 };
4074 };
4075
4076 pmu@90b6400 {
4077 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4078 reg = <0 0x090b6400 0 0x600>;
4079
4080 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4081
4082 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4083 operating-points-v2 = <&cpu_bwmon_opp_table>;
4084
4085 cpu_bwmon_opp_table: opp-table {
4086 compatible = "operating-points-v2";
4087
4088 opp-800000 {
4089 opp-peak-kBps = <(200 * 4 * 1000)>;
4090 };
4091
4092 opp-1804000 {
4093 opp-peak-kBps = <(451 * 4 * 1000)>;
4094 };
4095
4096 opp-2188000 {
4097 opp-peak-kBps = <(547 * 4 * 1000)>;
4098 };
4099
4100 opp-2724000 {
4101 opp-peak-kBps = <(681 * 4 * 1000)>;
4102 };
4103
4104 opp-3072000 {
4105 opp-peak-kBps = <(768 * 4 * 1000)>;
4106 };
4107
4108 /* 1017MHz, 1353 MHz, LPDDR4X */
4109
4110 opp-6220000 {
4111 opp-peak-kBps = <(1555 * 4 * 1000)>;
4112 };
4113
4114 opp-6832000 {
4115 opp-peak-kBps = <(1708 * 4 * 1000)>;
4116 };
4117
4118 opp-8368000 {
4119 opp-peak-kBps = <(2092 * 4 * 1000)>;
4120 };
4121
4122 /* 2133MHz, LPDDR4X */
4123
4124 /* LPDDR5 */
4125 opp-10944000 {
4126 opp-peak-kBps = <(2736 * 4 * 1000)>;
4127 };
4128
4129 /* LPDDR5 */
4130 opp-12784000 {
4131 opp-peak-kBps = <(3196 * 4 * 1000)>;
4132 };
4133 };
4134 };
4135
4136 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = <2>;
4140 qcom,bcm-voters = <&apps_bcm_voter>;
4141 };
4142
4143 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = <2>;
4147 qcom,bcm-voters = <&apps_bcm_voter>;
4148 };
4149
4150 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = <2>;
4154 qcom,bcm-voters = <&apps_bcm_voter>;
4155 };
4156
4157 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled";
4161 #address-cells = <2>;
4162 #size-cells = <2>;
4163 ranges;
4164 dma-ranges;
4165
4166 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_noc",
4173 "core",
4174 "iface",
4175 "sleep",
4176 "mock_utmi",
4177 "xo";
4178
4179 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates = <19200000>, <200000000>;
4182
4183 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4184 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4185 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pwr_event",
4189 "hs_phy_irq",
4190 "dp_hs_phy_irq",
4191 "dm_hs_phy_irq",
4192 "ss_phy_irq";
4193
4194 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source;
4196
4197 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198
4199 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4200 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4201 interconnect-names = "usb-ddr", "apps-usb";
4202
4203 usb_1_dwc3: usb@a600000 {
4204 compatible = "snps,dwc3";
4205 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_susphy_quirk;
4209 snps,dis_enblslpm_quirk;
4210 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4211 phy-names = "usb2-phy", "usb3-phy";
4212
4213 ports {
4214 #address-cells = <1>;
4215 #size-cells = <0>;
4216
4217 port@0 {
4218 reg = <0>;
4219
4220 usb_1_dwc3_hs_out: endpoint {
4221 };
4222 };
4223
4224 port@1 {
4225 reg = <1>;
4226
4227 usb_1_dwc3_ss_out: endpoint {
4228 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4229 };
4230 };
4231 };
4232 };
4233 };
4234
4235 system-cache-controller@9200000 {
4236 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4238 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4239 <0 0x09600000 0 0x50000>;
4240 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4241 "llcc3_base", "llcc_broadcast_base";
4242 };
4243
4244 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled";
4248 #address-cells = <2>;
4249 #size-cells = <2>;
4250 ranges;
4251 dma-ranges;
4252
4253 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_noc",
4260 "core",
4261 "iface",
4262 "sleep",
4263 "mock_utmi",
4264 "xo";
4265
4266 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates = <19200000>, <200000000>;
4269
4270 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4271 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4272 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pwr_event",
4276 "hs_phy_irq",
4277 "dp_hs_phy_irq",
4278 "dm_hs_phy_irq",
4279 "ss_phy_irq";
4280
4281 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source;
4283
4284 resets = <&gcc GCC_USB30_SEC_BCR>;
4285
4286 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4287 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4288 interconnect-names = "usb-ddr", "apps-usb";
4289
4290 usb_2_dwc3: usb@a800000 {
4291 compatible = "snps,dwc3";
4292 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_susphy_quirk;
4296 snps,dis_enblslpm_quirk;
4297 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
4298 phy-names = "usb2-phy", "usb3-phy";
4299 };
4300 };
4301
4302 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&videocc MVS0C_GDSC>,
4307 <&videocc MVS0_GDSC>,
4308 <&rpmhpd RPMHPD_MX>;
4309 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = <&venus_opp_table>;
4311
4312 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface", "core", "vcodec0_core";
4316
4317 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4318 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4319 interconnect-names = "cpu-cfg", "video-mem";
4320
4321 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&video_mem>;
4323
4324 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", "core";
4327
4328 status = "disabled";
4329
4330 video-decoder {
4331 compatible = "venus-decoder";
4332 };
4333
4334 video-encoder {
4335 compatible = "venus-encoder";
4336 };
4337
4338 venus_opp_table: opp-table {
4339 compatible = "operating-points-v2";
4340
4341 opp-720000000 {
4342 opp-hz = /bits/ 64 <720000000>;
4343 required-opps = <&rpmhpd_opp_low_svs>;
4344 };
4345
4346 opp-1014000000 {
4347 opp-hz = /bits/ 64 <1014000000>;
4348 required-opps = <&rpmhpd_opp_svs>;
4349 };
4350
4351 opp-1098000000 {
4352 opp-hz = /bits/ 64 <1098000000>;
4353 required-opps = <&rpmhpd_opp_svs_l1>;
4354 };
4355
4356 opp-1332000000 {
4357 opp-hz = /bits/ 64 <1332000000>;
4358 required-opps = <&rpmhpd_opp_nom>;
4359 };
4360 };
4361 };
4362
4363 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpmhpd RPMHPD_MMCX>;
4370 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>;
4373 #reset-cells = <1>;
4374 #power-domain-cells = <1>;
4375 };
4376
4377 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4379 #address-cells = <1>;
4380 #size-cells = <0>;
4381
4382 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&camcc TITAN_TOP_GDSC>;
4385
4386 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc_axi",
4392 "slow_ahb_src",
4393 "cpas_ahb",
4394 "cci",
4395 "cci_src";
4396
4397 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "default", "sleep";
4400
4401 status = "disabled";
4402
4403 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>;
4405 clock-frequency = <1000000>;
4406 #address-cells = <1>;
4407 #size-cells = <0>;
4408 };
4409
4410 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>;
4412 clock-frequency = <1000000>;
4413 #address-cells = <1>;
4414 #size-cells = <0>;
4415 };
4416 };
4417
4418 cci1: cci@ac50000 {
4419 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4420 #address-cells = <1>;
4421 #size-cells = <0>;
4422
4423 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&camcc TITAN_TOP_GDSC>;
4426
4427 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc_axi",
4433 "slow_ahb_src",
4434 "cpas_ahb",
4435 "cci",
4436 "cci_src";
4437
4438 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "default", "sleep";
4441
4442 status = "disabled";
4443
4444 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>;
4446 clock-frequency = <1000000>;
4447 #address-cells = <1>;
4448 #size-cells = <0>;
4449 };
4450
4451 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>;
4453 clock-frequency = <1000000>;
4454 #address-cells = <1>;
4455 #size-cells = <0>;
4456 };
4457 };
4458
4459 camss: camss@ac6a000 {
4460 compatible = "qcom,sm8250-camss";
4461 status = "disabled";
4462
4463 reg = <0 0x0ac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 0x1000>,
4467 <0 0x0ac72000 0 0x1000>,
4468 <0 0x0ac74000 0 0x1000>,
4469 <0 0x0acb4000 0 0xd000>,
4470 <0 0x0acc3000 0 0xd000>,
4471 <0 0x0acd9000 0 0x2200>,
4472 <0 0x0acdb200 0 0x2200>;
4473 reg-names = "csiphy0",
4474 "csiphy1",
4475 "csiphy2",
4476 "csiphy3",
4477 "csiphy4",
4478 "csiphy5",
4479 "vfe0",
4480 "vfe1",
4481 "vfe_lite0",
4482 "vfe_lite1";
4483
4484 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "csiphy0",
4499 "csiphy1",
4500 "csiphy2",
4501 "csiphy3",
4502 "csiphy4",
4503 "csiphy5",
4504 "csid0",
4505 "csid1",
4506 "csid2",
4507 "csid3",
4508 "vfe0",
4509 "vfe1",
4510 "vfe_lite0",
4511 "vfe_lite1";
4512
4513 power-domains = <&camcc IFE_0_GDSC>,
4514 <&camcc IFE_1_GDSC>,
4515 <&camcc TITAN_TOP_GDSC>;
4516
4517 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554
4555 clock-names = "cam_ahb_clk",
4556 "cam_hf_axi",
4557 "cam_sf_axi",
4558 "camnoc_axi",
4559 "camnoc_axi_src",
4560 "core_ahb",
4561 "cpas_ahb",
4562 "csiphy0",
4563 "csiphy0_timer",
4564 "csiphy1",
4565 "csiphy1_timer",
4566 "csiphy2",
4567 "csiphy2_timer",
4568 "csiphy3",
4569 "csiphy3_timer",
4570 "csiphy4",
4571 "csiphy4_timer",
4572 "csiphy5",
4573 "csiphy5_timer",
4574 "slow_ahb_src",
4575 "vfe0_ahb",
4576 "vfe0_axi",
4577 "vfe0",
4578 "vfe0_cphy_rx",
4579 "vfe0_csid",
4580 "vfe0_areg",
4581 "vfe1_ahb",
4582 "vfe1_axi",
4583 "vfe1",
4584 "vfe1_cphy_rx",
4585 "vfe1_csid",
4586 "vfe1_areg",
4587 "vfe_lite_ahb",
4588 "vfe_lite_axi",
4589 "vfe_lite",
4590 "vfe_lite_cphy_rx",
4591 "vfe_lite_csid";
4592
4593 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 0xc41 0x400>;
4601
4602 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4603 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4604 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4605 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4606 interconnect-names = "cam_ahb",
4607 "cam_hf_0_mnoc",
4608 "cam_sf_0_mnoc",
4609 "cam_sf_icp_mnoc";
4610
4611 ports {
4612 #address-cells = <1>;
4613 #size-cells = <0>;
4614
4615 port@0 {
4616 reg = <0>;
4617 };
4618
4619 port@1 {
4620 reg = <1>;
4621 };
4622
4623 port@2 {
4624 reg = <2>;
4625 };
4626
4627 port@3 {
4628 reg = <3>;
4629 };
4630
4631 port@4 {
4632 reg = <4>;
4633 };
4634
4635 port@5 {
4636 reg = <5>;
4637 };
4638 };
4639 };
4640
4641 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk>;
4648 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpmhpd RPMHPD_MMCX>;
4650 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled";
4652 #clock-cells = <1>;
4653 #reset-cells = <1>;
4654 #power-domain-cells = <1>;
4655 };
4656
4657 mdss: display-subsystem@ae00000 {
4658 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss";
4661
4662 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4663 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4664 interconnect-names = "mdp0-mem", "mdp1-mem";
4665
4666 power-domains = <&dispcc MDSS_GDSC>;
4667
4668 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface", "bus", "nrt_bus", "core";
4673
4674 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller;
4676 #interrupt-cells = <1>;
4677
4678 iommus = <&apps_smmu 0x820 0x402>;
4679
4680 status = "disabled";
4681
4682 #address-cells = <2>;
4683 #size-cells = <2>;
4684 ranges;
4685
4686 mdss_mdp: display-controller@ae01000 {
4687 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = "mdp", "vbif";
4691
4692 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = "iface", "bus", "core", "vsync";
4697
4698 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-clock-rates = <19200000>;
4700
4701 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains = <&rpmhpd RPMHPD_MMCX>;
4703
4704 interrupt-parent = <&mdss>;
4705 interrupts = <0>;
4706
4707 ports {
4708 #address-cells = <1>;
4709 #size-cells = <0>;
4710
4711 port@0 {
4712 reg = <0>;
4713 dpu_intf1_out: endpoint {
4714 remote-endpoint = <&mdss_dsi0_in>;
4715 };
4716 };
4717
4718 port@1 {
4719 reg = <1>;
4720 dpu_intf2_out: endpoint {
4721 remote-endpoint = <&mdss_dsi1_in>;
4722 };
4723 };
4724
4725 port@2 {
4726 reg = <2>;
4727
4728 dpu_intf0_out: endpoint {
4729 remote-endpoint = <&mdss_dp_in>;
4730 };
4731 };
4732 };
4733
4734 mdp_opp_table: opp-table {
4735 compatible = "operating-points-v2";
4736
4737 opp-200000000 {
4738 opp-hz = /bits/ 64 <200000000>;
4739 required-opps = <&rpmhpd_opp_low_svs>;
4740 };
4741
4742 opp-300000000 {
4743 opp-hz = /bits/ 64 <300000000>;
4744 required-opps = <&rpmhpd_opp_svs>;
4745 };
4746
4747 opp-345000000 {
4748 opp-hz = /bits/ 64 <345000000>;
4749 required-opps = <&rpmhpd_opp_svs_l1>;
4750 };
4751
4752 opp-460000000 {
4753 opp-hz = /bits/ 64 <460000000>;
4754 required-opps = <&rpmhpd_opp_nom>;
4755 };
4756 };
4757 };
4758
4759 mdss_dp: displayport-controller@ae90000 {
4760 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4761 reg = <0 0xae90000 0 0x200>,
4762 <0 0xae90200 0 0x200>,
4763 <0 0xae90400 0 0x600>,
4764 <0 0xae91000 0 0x400>,
4765 <0 0xae91400 0 0x400>;
4766 interrupt-parent = <&mdss>;
4767 interrupts = <12>;
4768 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4769 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4770 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4771 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4772 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4773 clock-names = "core_iface",
4774 "core_aux",
4775 "ctrl_link",
4776 "ctrl_link_iface",
4777 "stream_pixel";
4778
4779 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4780 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4781 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4782 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4783
4784 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4785 phy-names = "dp";
4786
4787 #sound-dai-cells = <0>;
4788
4789 operating-points-v2 = <&dp_opp_table>;
4790 power-domains = <&rpmhpd SM8250_MMCX>;
4791
4792 status = "disabled";
4793
4794 ports {
4795 #address-cells = <1>;
4796 #size-cells = <0>;
4797
4798 port@0 {
4799 reg = <0>;
4800 mdss_dp_in: endpoint {
4801 remote-endpoint = <&dpu_intf0_out>;
4802 };
4803 };
4804
4805 port@1 {
4806 reg = <1>;
4807
4808 mdss_dp_out: endpoint {
4809 };
4810 };
4811 };
4812
4813 dp_opp_table: opp-table {
4814 compatible = "operating-points-v2";
4815
4816 opp-160000000 {
4817 opp-hz = /bits/ 64 <160000000>;
4818 required-opps = <&rpmhpd_opp_low_svs>;
4819 };
4820
4821 opp-270000000 {
4822 opp-hz = /bits/ 64 <270000000>;
4823 required-opps = <&rpmhpd_opp_svs>;
4824 };
4825
4826 opp-540000000 {
4827 opp-hz = /bits/ 64 <540000000>;
4828 required-opps = <&rpmhpd_opp_svs_l1>;
4829 };
4830
4831 opp-810000000 {
4832 opp-hz = /bits/ 64 <810000000>;
4833 required-opps = <&rpmhpd_opp_nom>;
4834 };
4835 };
4836 };
4837
4838 mdss_dsi0: dsi@ae94000 {
4839 compatible = "qcom,sm8250-dsi-ctrl",
4840 "qcom,mdss-dsi-ctrl";
4841 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = "dsi_ctrl";
4843
4844 interrupt-parent = <&mdss>;
4845 interrupts = <4>;
4846
4847 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = "byte",
4854 "byte_intf",
4855 "pixel",
4856 "core",
4857 "iface",
4858 "bus";
4859
4860 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4862
4863 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains = <&rpmhpd RPMHPD_MMCX>;
4865
4866 phys = <&mdss_dsi0_phy>;
4867
4868 status = "disabled";
4869
4870 #address-cells = <1>;
4871 #size-cells = <0>;
4872
4873 ports {
4874 #address-cells = <1>;
4875 #size-cells = <0>;
4876
4877 port@0 {
4878 reg = <0>;
4879 mdss_dsi0_in: endpoint {
4880 remote-endpoint = <&dpu_intf1_out>;
4881 };
4882 };
4883
4884 port@1 {
4885 reg = <1>;
4886 mdss_dsi0_out: endpoint {
4887 };
4888 };
4889 };
4890
4891 dsi_opp_table: opp-table {
4892 compatible = "operating-points-v2";
4893
4894 opp-187500000 {
4895 opp-hz = /bits/ 64 <187500000>;
4896 required-opps = <&rpmhpd_opp_low_svs>;
4897 };
4898
4899 opp-300000000 {
4900 opp-hz = /bits/ 64 <300000000>;
4901 required-opps = <&rpmhpd_opp_svs>;
4902 };
4903
4904 opp-358000000 {
4905 opp-hz = /bits/ 64 <358000000>;
4906 required-opps = <&rpmhpd_opp_svs_l1>;
4907 };
4908 };
4909 };
4910
4911 mdss_dsi0_phy: phy@ae94400 {
4912 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0ae94600 0 0x280>,
4915 <0 0x0ae94900 0 0x260>;
4916 reg-names = "dsi_phy",
4917 "dsi_phy_lane",
4918 "dsi_pll";
4919
4920 #clock-cells = <1>;
4921 #phy-cells = <0>;
4922
4923 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = "iface", "ref";
4926
4927 status = "disabled";
4928 };
4929
4930 mdss_dsi1: dsi@ae96000 {
4931 compatible = "qcom,sm8250-dsi-ctrl",
4932 "qcom,mdss-dsi-ctrl";
4933 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = "dsi_ctrl";
4935
4936 interrupt-parent = <&mdss>;
4937 interrupts = <5>;
4938
4939 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = "byte",
4946 "byte_intf",
4947 "pixel",
4948 "core",
4949 "iface",
4950 "bus";
4951
4952 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4954
4955 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains = <&rpmhpd RPMHPD_MMCX>;
4957
4958 phys = <&mdss_dsi1_phy>;
4959
4960 status = "disabled";
4961
4962 #address-cells = <1>;
4963 #size-cells = <0>;
4964
4965 ports {
4966 #address-cells = <1>;
4967 #size-cells = <0>;
4968
4969 port@0 {
4970 reg = <0>;
4971 mdss_dsi1_in: endpoint {
4972 remote-endpoint = <&dpu_intf2_out>;
4973 };
4974 };
4975
4976 port@1 {
4977 reg = <1>;
4978 mdss_dsi1_out: endpoint {
4979 };
4980 };
4981 };
4982 };
4983
4984 mdss_dsi1_phy: phy@ae96400 {
4985 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0ae96600 0 0x280>,
4988 <0 0x0ae96900 0 0x260>;
4989 reg-names = "dsi_phy",
4990 "dsi_phy_lane",
4991 "dsi_pll";
4992
4993 #clock-cells = <1>;
4994 #phy-cells = <0>;
4995
4996 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = "iface", "ref";
4999
5000 status = "disabled";
5001 };
5002 };
5003
5004 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpmhpd RPMHPD_MMCX>;
5008 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_phy 0>,
5011 <&mdss_dsi0_phy 1>,
5012 <&mdss_dsi1_phy 0>,
5013 <&mdss_dsi1_phy 1>,
5014 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5015 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
5016 clock-names = "bi_tcxo",
5017 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy_pll_link_clk",
5022 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>;
5024 #reset-cells = <1>;
5025 #power-domain-cells = <1>;
5026 };
5027
5028 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2>;
5034 interrupt-parent = <&intc>;
5035 interrupt-controller;
5036 };
5037
5038 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells = <1>;
5047 };
5048
5049 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells = <1>;
5058 };
5059
5060 aoss_qmp: power-management@c300000 {
5061 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068
5069 #clock-cells = <0>;
5070 };
5071
5072 sram@c3f0000 {
5073 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 0x400>;
5075 };
5076
5077 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "periph_irq";
5086 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>;
5088 qcom,channel = <0>;
5089 #address-cells = <2>;
5090 #size-cells = <0>;
5091 interrupt-controller;
5092 #interrupt-cells = <4>;
5093 };
5094
5095 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller;
5103 #gpio-cells = <2>;
5104 interrupt-controller;
5105 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc>;
5108
5109 cam2_default: cam2-default-state {
5110 rst-pins {
5111 pins = "gpio78";
5112 function = "gpio";
5113 drive-strength = <2>;
5114 bias-disable;
5115 };
5116
5117 mclk-pins {
5118 pins = "gpio96";
5119 function = "cam_mclk";
5120 drive-strength = <16>;
5121 bias-disable;
5122 };
5123 };
5124
5125 cam2_suspend: cam2-suspend-state {
5126 rst-pins {
5127 pins = "gpio78";
5128 function = "gpio";
5129 drive-strength = <2>;
5130 bias-pull-down;
5131 output-low;
5132 };
5133
5134 mclk-pins {
5135 pins = "gpio96";
5136 function = "cam_mclk";
5137 drive-strength = <2>;
5138 bias-disable;
5139 };
5140 };
5141
5142 cci0_default: cci0-default-state {
5143 cci0_i2c0_default: cci0-i2c0-default-pins {
5144 /* SDA, SCL */
5145 pins = "gpio101", "gpio102";
5146 function = "cci_i2c";
5147
5148 bias-pull-up;
5149 drive-strength = <2>; /* 2 mA */
5150 };
5151
5152 cci0_i2c1_default: cci0-i2c1-default-pins {
5153 /* SDA, SCL */
5154 pins = "gpio103", "gpio104";
5155 function = "cci_i2c";
5156
5157 bias-pull-up;
5158 drive-strength = <2>; /* 2 mA */
5159 };
5160 };
5161
5162 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5164 /* SDA, SCL */
5165 pins = "gpio101", "gpio102";
5166 function = "cci_i2c";
5167
5168 drive-strength = <2>; /* 2 mA */
5169 bias-pull-down;
5170 };
5171
5172 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5173 /* SDA, SCL */
5174 pins = "gpio103", "gpio104";
5175 function = "cci_i2c";
5176
5177 drive-strength = <2>; /* 2 mA */
5178 bias-pull-down;
5179 };
5180 };
5181
5182 cci1_default: cci1-default-state {
5183 cci1_i2c0_default: cci1-i2c0-default-pins {
5184 /* SDA, SCL */
5185 pins = "gpio105","gpio106";
5186 function = "cci_i2c";
5187
5188 bias-pull-up;
5189 drive-strength = <2>; /* 2 mA */
5190 };
5191
5192 cci1_i2c1_default: cci1-i2c1-default-pins {
5193 /* SDA, SCL */
5194 pins = "gpio107","gpio108";
5195 function = "cci_i2c";
5196
5197 bias-pull-up;
5198 drive-strength = <2>; /* 2 mA */
5199 };
5200 };
5201
5202 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5204 /* SDA, SCL */
5205 pins = "gpio105","gpio106";
5206 function = "cci_i2c";
5207
5208 bias-pull-down;
5209 drive-strength = <2>; /* 2 mA */
5210 };
5211
5212 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5213 /* SDA, SCL */
5214 pins = "gpio107","gpio108";
5215 function = "cci_i2c";
5216
5217 bias-pull-down;
5218 drive-strength = <2>; /* 2 mA */
5219 };
5220 };
5221
5222 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins {
5224 pins = "gpio138";
5225 function = "mi2s0_sck";
5226 drive-strength = <8>;
5227 bias-disable;
5228 };
5229
5230 ws-pins {
5231 pins = "gpio141";
5232 function = "mi2s0_ws";
5233 drive-strength = <8>;
5234 output-high;
5235 };
5236
5237 data0-pins {
5238 pins = "gpio139";
5239 function = "mi2s0_data0";
5240 drive-strength = <8>;
5241 bias-disable;
5242 output-high;
5243 };
5244
5245 data1-pins {
5246 pins = "gpio140";
5247 function = "mi2s0_data1";
5248 drive-strength = <8>;
5249 output-high;
5250 };
5251 };
5252
5253 qup_i2c0_default: qup-i2c0-default-state {
5254 pins = "gpio28", "gpio29";
5255 function = "qup0";
5256 drive-strength = <2>;
5257 bias-disable;
5258 };
5259
5260 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4", "gpio5";
5262 function = "qup1";
5263 drive-strength = <2>;
5264 bias-disable;
5265 };
5266
5267 qup_i2c2_default: qup-i2c2-default-state {
5268 pins = "gpio115", "gpio116";
5269 function = "qup2";
5270 drive-strength = <2>;
5271 bias-disable;
5272 };
5273
5274 qup_i2c3_default: qup-i2c3-default-state {
5275 pins = "gpio119", "gpio120";
5276 function = "qup3";
5277 drive-strength = <2>;
5278 bias-disable;
5279 };
5280
5281 qup_i2c4_default: qup-i2c4-default-state {
5282 pins = "gpio8", "gpio9";
5283 function = "qup4";
5284 drive-strength = <2>;
5285 bias-disable;
5286 };
5287
5288 qup_i2c5_default: qup-i2c5-default-state {
5289 pins = "gpio12", "gpio13";
5290 function = "qup5";
5291 drive-strength = <2>;
5292 bias-disable;
5293 };
5294
5295 qup_i2c6_default: qup-i2c6-default-state {
5296 pins = "gpio16", "gpio17";
5297 function = "qup6";
5298 drive-strength = <2>;
5299 bias-disable;
5300 };
5301
5302 qup_i2c7_default: qup-i2c7-default-state {
5303 pins = "gpio20", "gpio21";
5304 function = "qup7";
5305 drive-strength = <2>;
5306 bias-disable;
5307 };
5308
5309 qup_i2c8_default: qup-i2c8-default-state {
5310 pins = "gpio24", "gpio25";
5311 function = "qup8";
5312 drive-strength = <2>;
5313 bias-disable;
5314 };
5315
5316 qup_i2c9_default: qup-i2c9-default-state {
5317 pins = "gpio125", "gpio126";
5318 function = "qup9";
5319 drive-strength = <2>;
5320 bias-disable;
5321 };
5322
5323 qup_i2c10_default: qup-i2c10-default-state {
5324 pins = "gpio129", "gpio130";
5325 function = "qup10";
5326 drive-strength = <2>;
5327 bias-disable;
5328 };
5329
5330 qup_i2c11_default: qup-i2c11-default-state {
5331 pins = "gpio60", "gpio61";
5332 function = "qup11";
5333 drive-strength = <2>;
5334 bias-disable;
5335 };
5336
5337 qup_i2c12_default: qup-i2c12-default-state {
5338 pins = "gpio32", "gpio33";
5339 function = "qup12";
5340 drive-strength = <2>;
5341 bias-disable;
5342 };
5343
5344 qup_i2c13_default: qup-i2c13-default-state {
5345 pins = "gpio36", "gpio37";
5346 function = "qup13";
5347 drive-strength = <2>;
5348 bias-disable;
5349 };
5350
5351 qup_i2c14_default: qup-i2c14-default-state {
5352 pins = "gpio40", "gpio41";
5353 function = "qup14";
5354 drive-strength = <2>;
5355 bias-disable;
5356 };
5357
5358 qup_i2c15_default: qup-i2c15-default-state {
5359 pins = "gpio44", "gpio45";
5360 function = "qup15";
5361 drive-strength = <2>;
5362 bias-disable;
5363 };
5364
5365 qup_i2c16_default: qup-i2c16-default-state {
5366 pins = "gpio48", "gpio49";
5367 function = "qup16";
5368 drive-strength = <2>;
5369 bias-disable;
5370 };
5371
5372 qup_i2c17_default: qup-i2c17-default-state {
5373 pins = "gpio52", "gpio53";
5374 function = "qup17";
5375 drive-strength = <2>;
5376 bias-disable;
5377 };
5378
5379 qup_i2c18_default: qup-i2c18-default-state {
5380 pins = "gpio56", "gpio57";
5381 function = "qup18";
5382 drive-strength = <2>;
5383 bias-disable;
5384 };
5385
5386 qup_i2c19_default: qup-i2c19-default-state {
5387 pins = "gpio0", "gpio1";
5388 function = "qup19";
5389 drive-strength = <2>;
5390 bias-disable;
5391 };
5392
5393 qup_spi0_cs: qup-spi0-cs-state {
5394 pins = "gpio31";
5395 function = "qup0";
5396 };
5397
5398 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5399 pins = "gpio31";
5400 function = "gpio";
5401 };
5402
5403 qup_spi0_data_clk: qup-spi0-data-clk-state {
5404 pins = "gpio28", "gpio29",
5405 "gpio30";
5406 function = "qup0";
5407 };
5408
5409 qup_spi1_cs: qup-spi1-cs-state {
5410 pins = "gpio7";
5411 function = "qup1";
5412 };
5413
5414 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5415 pins = "gpio7";
5416 function = "gpio";
5417 };
5418
5419 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4", "gpio5",
5421 "gpio6";
5422 function = "qup1";
5423 };
5424
5425 qup_spi2_cs: qup-spi2-cs-state {
5426 pins = "gpio118";
5427 function = "qup2";
5428 };
5429
5430 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5431 pins = "gpio118";
5432 function = "gpio";
5433 };
5434
5435 qup_spi2_data_clk: qup-spi2-data-clk-state {
5436 pins = "gpio115", "gpio116",
5437 "gpio117";
5438 function = "qup2";
5439 };
5440
5441 qup_spi3_cs: qup-spi3-cs-state {
5442 pins = "gpio122";
5443 function = "qup3";
5444 };
5445
5446 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5447 pins = "gpio122";
5448 function = "gpio";
5449 };
5450
5451 qup_spi3_data_clk: qup-spi3-data-clk-state {
5452 pins = "gpio119", "gpio120",
5453 "gpio121";
5454 function = "qup3";
5455 };
5456
5457 qup_spi4_cs: qup-spi4-cs-state {
5458 pins = "gpio11";
5459 function = "qup4";
5460 };
5461
5462 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5463 pins = "gpio11";
5464 function = "gpio";
5465 };
5466
5467 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 pins = "gpio8", "gpio9",
5469 "gpio10";
5470 function = "qup4";
5471 };
5472
5473 qup_spi5_cs: qup-spi5-cs-state {
5474 pins = "gpio15";
5475 function = "qup5";
5476 };
5477
5478 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5479 pins = "gpio15";
5480 function = "gpio";
5481 };
5482
5483 qup_spi5_data_clk: qup-spi5-data-clk-state {
5484 pins = "gpio12", "gpio13",
5485 "gpio14";
5486 function = "qup5";
5487 };
5488
5489 qup_spi6_cs: qup-spi6-cs-state {
5490 pins = "gpio19";
5491 function = "qup6";
5492 };
5493
5494 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5495 pins = "gpio19";
5496 function = "gpio";
5497 };
5498
5499 qup_spi6_data_clk: qup-spi6-data-clk-state {
5500 pins = "gpio16", "gpio17",
5501 "gpio18";
5502 function = "qup6";
5503 };
5504
5505 qup_spi7_cs: qup-spi7-cs-state {
5506 pins = "gpio23";
5507 function = "qup7";
5508 };
5509
5510 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5511 pins = "gpio23";
5512 function = "gpio";
5513 };
5514
5515 qup_spi7_data_clk: qup-spi7-data-clk-state {
5516 pins = "gpio20", "gpio21",
5517 "gpio22";
5518 function = "qup7";
5519 };
5520
5521 qup_spi8_cs: qup-spi8-cs-state {
5522 pins = "gpio27";
5523 function = "qup8";
5524 };
5525
5526 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5527 pins = "gpio27";
5528 function = "gpio";
5529 };
5530
5531 qup_spi8_data_clk: qup-spi8-data-clk-state {
5532 pins = "gpio24", "gpio25",
5533 "gpio26";
5534 function = "qup8";
5535 };
5536
5537 qup_spi9_cs: qup-spi9-cs-state {
5538 pins = "gpio128";
5539 function = "qup9";
5540 };
5541
5542 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5543 pins = "gpio128";
5544 function = "gpio";
5545 };
5546
5547 qup_spi9_data_clk: qup-spi9-data-clk-state {
5548 pins = "gpio125", "gpio126",
5549 "gpio127";
5550 function = "qup9";
5551 };
5552
5553 qup_spi10_cs: qup-spi10-cs-state {
5554 pins = "gpio132";
5555 function = "qup10";
5556 };
5557
5558 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5559 pins = "gpio132";
5560 function = "gpio";
5561 };
5562
5563 qup_spi10_data_clk: qup-spi10-data-clk-state {
5564 pins = "gpio129", "gpio130",
5565 "gpio131";
5566 function = "qup10";
5567 };
5568
5569 qup_spi11_cs: qup-spi11-cs-state {
5570 pins = "gpio63";
5571 function = "qup11";
5572 };
5573
5574 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 pins = "gpio63";
5576 function = "gpio";
5577 };
5578
5579 qup_spi11_data_clk: qup-spi11-data-clk-state {
5580 pins = "gpio60", "gpio61",
5581 "gpio62";
5582 function = "qup11";
5583 };
5584
5585 qup_spi12_cs: qup-spi12-cs-state {
5586 pins = "gpio35";
5587 function = "qup12";
5588 };
5589
5590 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5591 pins = "gpio35";
5592 function = "gpio";
5593 };
5594
5595 qup_spi12_data_clk: qup-spi12-data-clk-state {
5596 pins = "gpio32", "gpio33",
5597 "gpio34";
5598 function = "qup12";
5599 };
5600
5601 qup_spi13_cs: qup-spi13-cs-state {
5602 pins = "gpio39";
5603 function = "qup13";
5604 };
5605
5606 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5607 pins = "gpio39";
5608 function = "gpio";
5609 };
5610
5611 qup_spi13_data_clk: qup-spi13-data-clk-state {
5612 pins = "gpio36", "gpio37",
5613 "gpio38";
5614 function = "qup13";
5615 };
5616
5617 qup_spi14_cs: qup-spi14-cs-state {
5618 pins = "gpio43";
5619 function = "qup14";
5620 };
5621
5622 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5623 pins = "gpio43";
5624 function = "gpio";
5625 };
5626
5627 qup_spi14_data_clk: qup-spi14-data-clk-state {
5628 pins = "gpio40", "gpio41",
5629 "gpio42";
5630 function = "qup14";
5631 };
5632
5633 qup_spi15_cs: qup-spi15-cs-state {
5634 pins = "gpio47";
5635 function = "qup15";
5636 };
5637
5638 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5639 pins = "gpio47";
5640 function = "gpio";
5641 };
5642
5643 qup_spi15_data_clk: qup-spi15-data-clk-state {
5644 pins = "gpio44", "gpio45",
5645 "gpio46";
5646 function = "qup15";
5647 };
5648
5649 qup_spi16_cs: qup-spi16-cs-state {
5650 pins = "gpio51";
5651 function = "qup16";
5652 };
5653
5654 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5655 pins = "gpio51";
5656 function = "gpio";
5657 };
5658
5659 qup_spi16_data_clk: qup-spi16-data-clk-state {
5660 pins = "gpio48", "gpio49",
5661 "gpio50";
5662 function = "qup16";
5663 };
5664
5665 qup_spi17_cs: qup-spi17-cs-state {
5666 pins = "gpio55";
5667 function = "qup17";
5668 };
5669
5670 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5671 pins = "gpio55";
5672 function = "gpio";
5673 };
5674
5675 qup_spi17_data_clk: qup-spi17-data-clk-state {
5676 pins = "gpio52", "gpio53",
5677 "gpio54";
5678 function = "qup17";
5679 };
5680
5681 qup_spi18_cs: qup-spi18-cs-state {
5682 pins = "gpio59";
5683 function = "qup18";
5684 };
5685
5686 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5687 pins = "gpio59";
5688 function = "gpio";
5689 };
5690
5691 qup_spi18_data_clk: qup-spi18-data-clk-state {
5692 pins = "gpio56", "gpio57",
5693 "gpio58";
5694 function = "qup18";
5695 };
5696
5697 qup_spi19_cs: qup-spi19-cs-state {
5698 pins = "gpio3";
5699 function = "qup19";
5700 };
5701
5702 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5703 pins = "gpio3";
5704 function = "gpio";
5705 };
5706
5707 qup_spi19_data_clk: qup-spi19-data-clk-state {
5708 pins = "gpio0", "gpio1",
5709 "gpio2";
5710 function = "qup19";
5711 };
5712
5713 qup_uart2_default: qup-uart2-default-state {
5714 pins = "gpio117", "gpio118";
5715 function = "qup2";
5716 };
5717
5718 qup_uart6_default: qup-uart6-default-state {
5719 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5720 function = "qup6";
5721 };
5722
5723 qup_uart12_default: qup-uart12-default-state {
5724 pins = "gpio34", "gpio35";
5725 function = "qup12";
5726 };
5727
5728 qup_uart17_default: qup-uart17-default-state {
5729 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5730 function = "qup17";
5731 };
5732
5733 qup_uart18_default: qup-uart18-default-state {
5734 pins = "gpio58", "gpio59";
5735 function = "qup18";
5736 };
5737
5738 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins {
5740 pins = "gpio133";
5741 function = "mi2s2_sck";
5742 drive-strength = <8>;
5743 bias-disable;
5744 };
5745
5746 data0-pins {
5747 pins = "gpio134";
5748 function = "mi2s2_data0";
5749 drive-strength = <8>;
5750 bias-disable;
5751 output-high;
5752 };
5753
5754 ws-pins {
5755 pins = "gpio135";
5756 function = "mi2s2_ws";
5757 drive-strength = <8>;
5758 output-high;
5759 };
5760 };
5761
5762 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins {
5764 pins = "sdc2_clk";
5765 drive-strength = <2>;
5766 bias-disable;
5767 };
5768
5769 cmd-pins {
5770 pins = "sdc2_cmd";
5771 drive-strength = <2>;
5772 bias-pull-up;
5773 };
5774
5775 data-pins {
5776 pins = "sdc2_data";
5777 drive-strength = <2>;
5778 bias-pull-up;
5779 };
5780 };
5781
5782 pcie0_default_state: pcie0-default-state {
5783 perst-pins {
5784 pins = "gpio79";
5785 function = "gpio";
5786 drive-strength = <2>;
5787 bias-pull-down;
5788 };
5789
5790 clkreq-pins {
5791 pins = "gpio80";
5792 function = "pci_e0";
5793 drive-strength = <2>;
5794 bias-pull-up;
5795 };
5796
5797 wake-pins {
5798 pins = "gpio81";
5799 function = "gpio";
5800 drive-strength = <2>;
5801 bias-pull-up;
5802 };
5803 };
5804
5805 pcie1_default_state: pcie1-default-state {
5806 perst-pins {
5807 pins = "gpio82";
5808 function = "gpio";
5809 drive-strength = <2>;
5810 bias-pull-down;
5811 };
5812
5813 clkreq-pins {
5814 pins = "gpio83";
5815 function = "pci_e1";
5816 drive-strength = <2>;
5817 bias-pull-up;
5818 };
5819
5820 wake-pins {
5821 pins = "gpio84";
5822 function = "gpio";
5823 drive-strength = <2>;
5824 bias-pull-up;
5825 };
5826 };
5827
5828 pcie2_default_state: pcie2-default-state {
5829 perst-pins {
5830 pins = "gpio85";
5831 function = "gpio";
5832 drive-strength = <2>;
5833 bias-pull-down;
5834 };
5835
5836 clkreq-pins {
5837 pins = "gpio86";
5838 function = "pci_e2";
5839 drive-strength = <2>;
5840 bias-pull-up;
5841 };
5842
5843 wake-pins {
5844 pins = "gpio87";
5845 function = "gpio";
5846 drive-strength = <2>;
5847 bias-pull-up;
5848 };
5849 };
5850 };
5851
5852 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>;
5856 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent;
5956 };
5957
5958 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 0x100>;
5961
5962 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5963 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wdog", "fatal", "ready",
5968 "handover", "stop-ack";
5969
5970 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo";
5972
5973 power-domains = <&rpmhpd RPMHPD_LCX>,
5974 <&rpmhpd RPMHPD_LMX>;
5975 power-domain-names = "lcx", "lmx";
5976
5977 memory-region = <&adsp_mem>;
5978
5979 qcom,qmp = <&aoss_qmp>;
5980
5981 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names = "stop";
5983
5984 status = "disabled";
5985
5986 glink-edge {
5987 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992
5993 label = "lpass";
5994 qcom,remote-pid = <2>;
5995
5996 apr {
5997 compatible = "qcom,apr-v2";
5998 qcom,glink-channels = "apr_audio_svc";
5999 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #address-cells = <1>;
6001 #size-cells = <0>;
6002
6003 service@3 {
6004 reg = <APR_SVC_ADSP_CORE>;
6005 compatible = "qcom,q6core";
6006 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 };
6008
6009 q6afe: service@4 {
6010 compatible = "qcom,q6afe";
6011 reg = <APR_SVC_AFE>;
6012 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 q6afedai: dais {
6014 compatible = "qcom,q6afe-dais";
6015 #address-cells = <1>;
6016 #size-cells = <0>;
6017 #sound-dai-cells = <1>;
6018 };
6019
6020 q6afecc: clock-controller {
6021 compatible = "qcom,q6afe-clocks";
6022 #clock-cells = <2>;
6023 };
6024 };
6025
6026 q6asm: service@7 {
6027 compatible = "qcom,q6asm";
6028 reg = <APR_SVC_ASM>;
6029 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 q6asmdai: dais {
6031 compatible = "qcom,q6asm-dais";
6032 #address-cells = <1>;
6033 #size-cells = <0>;
6034 #sound-dai-cells = <1>;
6035 iommus = <&apps_smmu 0x1801 0x0>;
6036 };
6037 };
6038
6039 q6adm: service@8 {
6040 compatible = "qcom,q6adm";
6041 reg = <APR_SVC_ADM>;
6042 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 q6routing: routing {
6044 compatible = "qcom,q6adm-routing";
6045 #sound-dai-cells = <0>;
6046 };
6047 };
6048 };
6049
6050 fastrpc {
6051 compatible = "qcom,fastrpc";
6052 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label = "adsp";
6054 qcom,non-secure-domain;
6055 #address-cells = <1>;
6056 #size-cells = <0>;
6057
6058 compute-cb@3 {
6059 compatible = "qcom,fastrpc-compute-cb";
6060 reg = <3>;
6061 iommus = <&apps_smmu 0x1803 0x0>;
6062 };
6063
6064 compute-cb@4 {
6065 compatible = "qcom,fastrpc-compute-cb";
6066 reg = <4>;
6067 iommus = <&apps_smmu 0x1804 0x0>;
6068 };
6069
6070 compute-cb@5 {
6071 compatible = "qcom,fastrpc-compute-cb";
6072 reg = <5>;
6073 iommus = <&apps_smmu 0x1805 0x0>;
6074 };
6075 };
6076 };
6077 };
6078
6079 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3>;
6082 interrupt-controller;
6083 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 };
6087
6088 watchdog@17c10000 {
6089 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6093 };
6094
6095 timer@17c20000 {
6096 #address-cells = <1>;
6097 #size-cells = <1>;
6098 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19200000>;
6102
6103 frame@17c21000 {
6104 frame-number = <0>;
6105 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c21000 0x1000>,
6108 <0x17c22000 0x1000>;
6109 };
6110
6111 frame@17c23000 {
6112 frame-number = <1>;
6113 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c23000 0x1000>;
6115 status = "disabled";
6116 };
6117
6118 frame@17c25000 {
6119 frame-number = <2>;
6120 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c25000 0x1000>;
6122 status = "disabled";
6123 };
6124
6125 frame@17c27000 {
6126 frame-number = <3>;
6127 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c27000 0x1000>;
6129 status = "disabled";
6130 };
6131
6132 frame@17c29000 {
6133 frame-number = <4>;
6134 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c29000 0x1000>;
6136 status = "disabled";
6137 };
6138
6139 frame@17c2b000 {
6140 frame-number = <5>;
6141 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2b000 0x1000>;
6143 status = "disabled";
6144 };
6145
6146 frame@17c2d000 {
6147 frame-number = <6>;
6148 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2d000 0x1000>;
6150 status = "disabled";
6151 };
6152 };
6153
6154 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc";
6156 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>;
6166 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLUSTER_PD>;
6169
6170 rpmhcc: clock-controller {
6171 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells = <1>;
6173 clock-names = "xo";
6174 clocks = <&xo_board>;
6175 };
6176
6177 rpmhpd: power-controller {
6178 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain-cells = <1>;
6180 operating-points-v2 = <&rpmhpd_opp_table>;
6181
6182 rpmhpd_opp_table: opp-table {
6183 compatible = "operating-points-v2";
6184
6185 rpmhpd_opp_ret: opp1 {
6186 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 };
6188
6189 rpmhpd_opp_min_svs: opp2 {
6190 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 };
6192
6193 rpmhpd_opp_low_svs: opp3 {
6194 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 };
6196
6197 rpmhpd_opp_svs: opp4 {
6198 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 };
6200
6201 rpmhpd_opp_svs_l1: opp5 {
6202 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 };
6204
6205 rpmhpd_opp_nom: opp6 {
6206 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 };
6208
6209 rpmhpd_opp_nom_l1: opp7 {
6210 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 };
6212
6213 rpmhpd_opp_nom_l2: opp8 {
6214 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 };
6216
6217 rpmhpd_opp_turbo: opp9 {
6218 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 };
6220
6221 rpmhpd_opp_turbo_l1: opp10 {
6222 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 };
6224 };
6225 };
6226
6227 apps_bcm_voter: bcm-voter {
6228 compatible = "qcom,bcm-voter";
6229 };
6230 };
6231
6232 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6234 reg = <0 0x18590000 0 0x1000>;
6235
6236 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", "alternate";
6238
6239 #interconnect-cells = <1>;
6240 };
6241
6242 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-domain2";
6249
6250 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = <1>;
6257 #clock-cells = <1>;
6258 };
6259 };
6260
6261 sound: sound {
6262 };
6263
6264 timer {
6265 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14
6269 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11
6271 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10
6273 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 };
6275
6276 thermal-zones {
6277 cpu0-thermal {
6278 polling-delay-passive = <250>;
6279
6280 thermal-sensors = <&tsens0 1>;
6281
6282 trips {
6283 cpu0_alert0: trip-point0 {
6284 temperature = <90000>;
6285 hysteresis = <2000>;
6286 type = "passive";
6287 };
6288
6289 cpu0_alert1: trip-point1 {
6290 temperature = <95000>;
6291 hysteresis = <2000>;
6292 type = "passive";
6293 };
6294
6295 cpu0_crit: cpu-crit {
6296 temperature = <110000>;
6297 hysteresis = <1000>;
6298 type = "critical";
6299 };
6300 };
6301
6302 cooling-maps {
6303 map0 {
6304 trip = <&cpu0_alert0>;
6305 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 };
6310 map1 {
6311 trip = <&cpu0_alert1>;
6312 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 };
6317 };
6318 };
6319
6320 cpu1-thermal {
6321 polling-delay-passive = <250>;
6322
6323 thermal-sensors = <&tsens0 2>;
6324
6325 trips {
6326 cpu1_alert0: trip-point0 {
6327 temperature = <90000>;
6328 hysteresis = <2000>;
6329 type = "passive";
6330 };
6331
6332 cpu1_alert1: trip-point1 {
6333 temperature = <95000>;
6334 hysteresis = <2000>;
6335 type = "passive";
6336 };
6337
6338 cpu1_crit: cpu-crit {
6339 temperature = <110000>;
6340 hysteresis = <1000>;
6341 type = "critical";
6342 };
6343 };
6344
6345 cooling-maps {
6346 map0 {
6347 trip = <&cpu1_alert0>;
6348 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 };
6353 map1 {
6354 trip = <&cpu1_alert1>;
6355 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 };
6360 };
6361 };
6362
6363 cpu2-thermal {
6364 polling-delay-passive = <250>;
6365
6366 thermal-sensors = <&tsens0 3>;
6367
6368 trips {
6369 cpu2_alert0: trip-point0 {
6370 temperature = <90000>;
6371 hysteresis = <2000>;
6372 type = "passive";
6373 };
6374
6375 cpu2_alert1: trip-point1 {
6376 temperature = <95000>;
6377 hysteresis = <2000>;
6378 type = "passive";
6379 };
6380
6381 cpu2_crit: cpu-crit {
6382 temperature = <110000>;
6383 hysteresis = <1000>;
6384 type = "critical";
6385 };
6386 };
6387
6388 cooling-maps {
6389 map0 {
6390 trip = <&cpu2_alert0>;
6391 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 };
6396 map1 {
6397 trip = <&cpu2_alert1>;
6398 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 };
6403 };
6404 };
6405
6406 cpu3-thermal {
6407 polling-delay-passive = <250>;
6408
6409 thermal-sensors = <&tsens0 4>;
6410
6411 trips {
6412 cpu3_alert0: trip-point0 {
6413 temperature = <90000>;
6414 hysteresis = <2000>;
6415 type = "passive";
6416 };
6417
6418 cpu3_alert1: trip-point1 {
6419 temperature = <95000>;
6420 hysteresis = <2000>;
6421 type = "passive";
6422 };
6423
6424 cpu3_crit: cpu-crit {
6425 temperature = <110000>;
6426 hysteresis = <1000>;
6427 type = "critical";
6428 };
6429 };
6430
6431 cooling-maps {
6432 map0 {
6433 trip = <&cpu3_alert0>;
6434 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 };
6439 map1 {
6440 trip = <&cpu3_alert1>;
6441 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 };
6446 };
6447 };
6448
6449 cpu4-top-thermal {
6450 polling-delay-passive = <250>;
6451
6452 thermal-sensors = <&tsens0 7>;
6453
6454 trips {
6455 cpu4_top_alert0: trip-point0 {
6456 temperature = <90000>;
6457 hysteresis = <2000>;
6458 type = "passive";
6459 };
6460
6461 cpu4_top_alert1: trip-point1 {
6462 temperature = <95000>;
6463 hysteresis = <2000>;
6464 type = "passive";
6465 };
6466
6467 cpu4_top_crit: cpu-crit {
6468 temperature = <110000>;
6469 hysteresis = <1000>;
6470 type = "critical";
6471 };
6472 };
6473
6474 cooling-maps {
6475 map0 {
6476 trip = <&cpu4_top_alert0>;
6477 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 };
6482 map1 {
6483 trip = <&cpu4_top_alert1>;
6484 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 };
6489 };
6490 };
6491
6492 cpu5-top-thermal {
6493 polling-delay-passive = <250>;
6494
6495 thermal-sensors = <&tsens0 8>;
6496
6497 trips {
6498 cpu5_top_alert0: trip-point0 {
6499 temperature = <90000>;
6500 hysteresis = <2000>;
6501 type = "passive";
6502 };
6503
6504 cpu5_top_alert1: trip-point1 {
6505 temperature = <95000>;
6506 hysteresis = <2000>;
6507 type = "passive";
6508 };
6509
6510 cpu5_top_crit: cpu-crit {
6511 temperature = <110000>;
6512 hysteresis = <1000>;
6513 type = "critical";
6514 };
6515 };
6516
6517 cooling-maps {
6518 map0 {
6519 trip = <&cpu5_top_alert0>;
6520 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 };
6525 map1 {
6526 trip = <&cpu5_top_alert1>;
6527 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 };
6532 };
6533 };
6534
6535 cpu6-top-thermal {
6536 polling-delay-passive = <250>;
6537
6538 thermal-sensors = <&tsens0 9>;
6539
6540 trips {
6541 cpu6_top_alert0: trip-point0 {
6542 temperature = <90000>;
6543 hysteresis = <2000>;
6544 type = "passive";
6545 };
6546
6547 cpu6_top_alert1: trip-point1 {
6548 temperature = <95000>;
6549 hysteresis = <2000>;
6550 type = "passive";
6551 };
6552
6553 cpu6_top_crit: cpu-crit {
6554 temperature = <110000>;
6555 hysteresis = <1000>;
6556 type = "critical";
6557 };
6558 };
6559
6560 cooling-maps {
6561 map0 {
6562 trip = <&cpu6_top_alert0>;
6563 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 };
6568 map1 {
6569 trip = <&cpu6_top_alert1>;
6570 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 };
6575 };
6576 };
6577
6578 cpu7-top-thermal {
6579 polling-delay-passive = <250>;
6580
6581 thermal-sensors = <&tsens0 10>;
6582
6583 trips {
6584 cpu7_top_alert0: trip-point0 {
6585 temperature = <90000>;
6586 hysteresis = <2000>;
6587 type = "passive";
6588 };
6589
6590 cpu7_top_alert1: trip-point1 {
6591 temperature = <95000>;
6592 hysteresis = <2000>;
6593 type = "passive";
6594 };
6595
6596 cpu7_top_crit: cpu-crit {
6597 temperature = <110000>;
6598 hysteresis = <1000>;
6599 type = "critical";
6600 };
6601 };
6602
6603 cooling-maps {
6604 map0 {
6605 trip = <&cpu7_top_alert0>;
6606 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 };
6611 map1 {
6612 trip = <&cpu7_top_alert1>;
6613 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 };
6618 };
6619 };
6620
6621 cpu4-bottom-thermal {
6622 polling-delay-passive = <250>;
6623
6624 thermal-sensors = <&tsens0 11>;
6625
6626 trips {
6627 cpu4_bottom_alert0: trip-point0 {
6628 temperature = <90000>;
6629 hysteresis = <2000>;
6630 type = "passive";
6631 };
6632
6633 cpu4_bottom_alert1: trip-point1 {
6634 temperature = <95000>;
6635 hysteresis = <2000>;
6636 type = "passive";
6637 };
6638
6639 cpu4_bottom_crit: cpu-crit {
6640 temperature = <110000>;
6641 hysteresis = <1000>;
6642 type = "critical";
6643 };
6644 };
6645
6646 cooling-maps {
6647 map0 {
6648 trip = <&cpu4_bottom_alert0>;
6649 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 };
6654 map1 {
6655 trip = <&cpu4_bottom_alert1>;
6656 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 };
6661 };
6662 };
6663
6664 cpu5-bottom-thermal {
6665 polling-delay-passive = <250>;
6666
6667 thermal-sensors = <&tsens0 12>;
6668
6669 trips {
6670 cpu5_bottom_alert0: trip-point0 {
6671 temperature = <90000>;
6672 hysteresis = <2000>;
6673 type = "passive";
6674 };
6675
6676 cpu5_bottom_alert1: trip-point1 {
6677 temperature = <95000>;
6678 hysteresis = <2000>;
6679 type = "passive";
6680 };
6681
6682 cpu5_bottom_crit: cpu-crit {
6683 temperature = <110000>;
6684 hysteresis = <1000>;
6685 type = "critical";
6686 };
6687 };
6688
6689 cooling-maps {
6690 map0 {
6691 trip = <&cpu5_bottom_alert0>;
6692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 };
6697 map1 {
6698 trip = <&cpu5_bottom_alert1>;
6699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 };
6704 };
6705 };
6706
6707 cpu6-bottom-thermal {
6708 polling-delay-passive = <250>;
6709
6710 thermal-sensors = <&tsens0 13>;
6711
6712 trips {
6713 cpu6_bottom_alert0: trip-point0 {
6714 temperature = <90000>;
6715 hysteresis = <2000>;
6716 type = "passive";
6717 };
6718
6719 cpu6_bottom_alert1: trip-point1 {
6720 temperature = <95000>;
6721 hysteresis = <2000>;
6722 type = "passive";
6723 };
6724
6725 cpu6_bottom_crit: cpu-crit {
6726 temperature = <110000>;
6727 hysteresis = <1000>;
6728 type = "critical";
6729 };
6730 };
6731
6732 cooling-maps {
6733 map0 {
6734 trip = <&cpu6_bottom_alert0>;
6735 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 };
6740 map1 {
6741 trip = <&cpu6_bottom_alert1>;
6742 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 };
6747 };
6748 };
6749
6750 cpu7-bottom-thermal {
6751 polling-delay-passive = <250>;
6752
6753 thermal-sensors = <&tsens0 14>;
6754
6755 trips {
6756 cpu7_bottom_alert0: trip-point0 {
6757 temperature = <90000>;
6758 hysteresis = <2000>;
6759 type = "passive";
6760 };
6761
6762 cpu7_bottom_alert1: trip-point1 {
6763 temperature = <95000>;
6764 hysteresis = <2000>;
6765 type = "passive";
6766 };
6767
6768 cpu7_bottom_crit: cpu-crit {
6769 temperature = <110000>;
6770 hysteresis = <1000>;
6771 type = "critical";
6772 };
6773 };
6774
6775 cooling-maps {
6776 map0 {
6777 trip = <&cpu7_bottom_alert0>;
6778 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 };
6783 map1 {
6784 trip = <&cpu7_bottom_alert1>;
6785 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 };
6790 };
6791 };
6792
6793 aoss0-thermal {
6794 polling-delay-passive = <250>;
6795
6796 thermal-sensors = <&tsens0 0>;
6797
6798 trips {
6799 aoss0_alert0: trip-point0 {
6800 temperature = <90000>;
6801 hysteresis = <2000>;
6802 type = "hot";
6803 };
6804 };
6805 };
6806
6807 cluster0-thermal {
6808 polling-delay-passive = <250>;
6809
6810 thermal-sensors = <&tsens0 5>;
6811
6812 trips {
6813 cluster0_alert0: trip-point0 {
6814 temperature = <90000>;
6815 hysteresis = <2000>;
6816 type = "hot";
6817 };
6818 cluster0_crit: cluster0-crit {
6819 temperature = <110000>;
6820 hysteresis = <2000>;
6821 type = "critical";
6822 };
6823 };
6824 };
6825
6826 cluster1-thermal {
6827 polling-delay-passive = <250>;
6828
6829 thermal-sensors = <&tsens0 6>;
6830
6831 trips {
6832 cluster1_alert0: trip-point0 {
6833 temperature = <90000>;
6834 hysteresis = <2000>;
6835 type = "hot";
6836 };
6837 cluster1_crit: cluster1-crit {
6838 temperature = <110000>;
6839 hysteresis = <2000>;
6840 type = "critical";
6841 };
6842 };
6843 };
6844
6845 gpu-top-thermal {
6846 polling-delay-passive = <250>;
6847
6848 thermal-sensors = <&tsens0 15>;
6849
6850 cooling-maps {
6851 map0 {
6852 trip = <&gpu_top_alert0>;
6853 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6854 };
6855 };
6856
6857 trips {
6858 gpu_top_alert0: trip-point0 {
6859 temperature = <85000>;
6860 hysteresis = <1000>;
6861 type = "passive";
6862 };
6863
6864 trip-point1 {
6865 temperature = <90000>;
6866 hysteresis = <1000>;
6867 type = "hot";
6868 };
6869
6870 trip-point2 {
6871 temperature = <110000>;
6872 hysteresis = <1000>;
6873 type = "critical";
6874 };
6875 };
6876 };
6877
6878 aoss1-thermal {
6879 polling-delay-passive = <250>;
6880
6881 thermal-sensors = <&tsens1 0>;
6882
6883 trips {
6884 aoss1_alert0: trip-point0 {
6885 temperature = <90000>;
6886 hysteresis = <2000>;
6887 type = "hot";
6888 };
6889 };
6890 };
6891
6892 wlan-thermal {
6893 polling-delay-passive = <250>;
6894
6895 thermal-sensors = <&tsens1 1>;
6896
6897 trips {
6898 wlan_alert0: trip-point0 {
6899 temperature = <90000>;
6900 hysteresis = <2000>;
6901 type = "hot";
6902 };
6903 };
6904 };
6905
6906 video-thermal {
6907 polling-delay-passive = <250>;
6908
6909 thermal-sensors = <&tsens1 2>;
6910
6911 trips {
6912 video_alert0: trip-point0 {
6913 temperature = <90000>;
6914 hysteresis = <2000>;
6915 type = "hot";
6916 };
6917 };
6918 };
6919
6920 mem-thermal {
6921 polling-delay-passive = <250>;
6922
6923 thermal-sensors = <&tsens1 3>;
6924
6925 trips {
6926 mem_alert0: trip-point0 {
6927 temperature = <90000>;
6928 hysteresis = <2000>;
6929 type = "hot";
6930 };
6931 };
6932 };
6933
6934 q6-hvx-thermal {
6935 polling-delay-passive = <250>;
6936
6937 thermal-sensors = <&tsens1 4>;
6938
6939 trips {
6940 q6_hvx_alert0: trip-point0 {
6941 temperature = <90000>;
6942 hysteresis = <2000>;
6943 type = "hot";
6944 };
6945 };
6946 };
6947
6948 camera-thermal {
6949 polling-delay-passive = <250>;
6950
6951 thermal-sensors = <&tsens1 5>;
6952
6953 trips {
6954 camera_alert0: trip-point0 {
6955 temperature = <90000>;
6956 hysteresis = <2000>;
6957 type = "hot";
6958 };
6959 };
6960 };
6961
6962 compute-thermal {
6963 polling-delay-passive = <250>;
6964
6965 thermal-sensors = <&tsens1 6>;
6966
6967 trips {
6968 compute_alert0: trip-point0 {
6969 temperature = <90000>;
6970 hysteresis = <2000>;
6971 type = "hot";
6972 };
6973 };
6974 };
6975
6976 npu-thermal {
6977 polling-delay-passive = <250>;
6978
6979 thermal-sensors = <&tsens1 7>;
6980
6981 trips {
6982 npu_alert0: trip-point0 {
6983 temperature = <90000>;
6984 hysteresis = <2000>;
6985 type = "hot";
6986 };
6987 };
6988 };
6989
6990 gpu-bottom-thermal {
6991 polling-delay-passive = <250>;
6992
6993 thermal-sensors = <&tsens1 8>;
6994
6995 cooling-maps {
6996 map0 {
6997 trip = <&gpu_bottom_alert0>;
6998 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6999 };
7000 };
7001
7002 trips {
7003 gpu_bottom_alert0: trip-point0 {
7004 temperature = <85000>;
7005 hysteresis = <1000>;
7006 type = "passive";
7007 };
7008
7009 trip-point1 {
7010 temperature = <90000>;
7011 hysteresis = <1000>;
7012 type = "hot";
7013 };
7014
7015 trip-point2 {
7016 temperature = <110000>;
7017 hysteresis = <1000>;
7018 type = "critical";
7019 };
7020 };
7021 };
7022 };
7023 };
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