1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, Linaro Limited
4 */
5
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,sm8350.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,apr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6afe.h>
24 #include <dt-bindings/thermal/thermal.h>
25 #include <dt-bindings/interconnect/qcom,sm8350.h>
26
27 / {
28 interrupt-parent = <&intc>;
29
30 #address-cells = <2>;
31 #size-cells = <2>;
32
33 chosen { };
34
35 clocks {
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <38400000>;
40 clock-output-names = "xo_board";
41 };
42
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 clock-frequency = <32000>;
46 #clock-cells = <0>;
47 };
48 };
49
50 cpus {
51 #address-cells = <2>;
52 #size-cells = <0>;
53
54 CPU0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a55";
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
59 enable-method = "psci";
60 next-level-cache = <&L2_0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
62 power-domains = <&CPU_PD0>;
63 power-domain-names = "psci";
64 #cooling-cells = <2>;
65 L2_0: l2-cache {
66 compatible = "cache";
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "cache";
72 cache-level = <3>;
73 cache-unified;
74 };
75 };
76 };
77
78 CPU1: cpu@100 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a55";
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
83 enable-method = "psci";
84 next-level-cache = <&L2_100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
86 power-domains = <&CPU_PD1>;
87 power-domain-names = "psci";
88 #cooling-cells = <2>;
89 L2_100: l2-cache {
90 compatible = "cache";
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&L3_0>;
94 };
95 };
96
97 CPU2: cpu@200 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a55";
100 reg = <0x0 0x200>;
101 clocks = <&cpufreq_hw 0>;
102 enable-method = "psci";
103 next-level-cache = <&L2_200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 power-domains = <&CPU_PD2>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
108 L2_200: l2-cache {
109 compatible = "cache";
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&L3_0>;
113 };
114 };
115
116 CPU3: cpu@300 {
117 device_type = "cpu";
118 compatible = "arm,cortex-a55";
119 reg = <0x0 0x300>;
120 clocks = <&cpufreq_hw 0>;
121 enable-method = "psci";
122 next-level-cache = <&L2_300>;
123 qcom,freq-domain = <&cpufreq_hw 0>;
124 power-domains = <&CPU_PD3>;
125 power-domain-names = "psci";
126 #cooling-cells = <2>;
127 L2_300: l2-cache {
128 compatible = "cache";
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
132 };
133 };
134
135 CPU4: cpu@400 {
136 device_type = "cpu";
137 compatible = "arm,cortex-a78";
138 reg = <0x0 0x400>;
139 clocks = <&cpufreq_hw 1>;
140 enable-method = "psci";
141 next-level-cache = <&L2_400>;
142 qcom,freq-domain = <&cpufreq_hw 1>;
143 power-domains = <&CPU_PD4>;
144 power-domain-names = "psci";
145 #cooling-cells = <2>;
146 L2_400: l2-cache {
147 compatible = "cache";
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
151 };
152 };
153
154 CPU5: cpu@500 {
155 device_type = "cpu";
156 compatible = "arm,cortex-a78";
157 reg = <0x0 0x500>;
158 clocks = <&cpufreq_hw 1>;
159 enable-method = "psci";
160 next-level-cache = <&L2_500>;
161 qcom,freq-domain = <&cpufreq_hw 1>;
162 power-domains = <&CPU_PD5>;
163 power-domain-names = "psci";
164 #cooling-cells = <2>;
165 L2_500: l2-cache {
166 compatible = "cache";
167 cache-level = <2>;
168 cache-unified;
169 next-level-cache = <&L3_0>;
170 };
171 };
172
173 CPU6: cpu@600 {
174 device_type = "cpu";
175 compatible = "arm,cortex-a78";
176 reg = <0x0 0x600>;
177 clocks = <&cpufreq_hw 1>;
178 enable-method = "psci";
179 next-level-cache = <&L2_600>;
180 qcom,freq-domain = <&cpufreq_hw 1>;
181 power-domains = <&CPU_PD6>;
182 power-domain-names = "psci";
183 #cooling-cells = <2>;
184 L2_600: l2-cache {
185 compatible = "cache";
186 cache-level = <2>;
187 cache-unified;
188 next-level-cache = <&L3_0>;
189 };
190 };
191
192 CPU7: cpu@700 {
193 device_type = "cpu";
194 compatible = "arm,cortex-x1";
195 reg = <0x0 0x700>;
196 clocks = <&cpufreq_hw 2>;
197 enable-method = "psci";
198 next-level-cache = <&L2_700>;
199 qcom,freq-domain = <&cpufreq_hw 2>;
200 power-domains = <&CPU_PD7>;
201 power-domain-names = "psci";
202 #cooling-cells = <2>;
203 L2_700: l2-cache {
204 compatible = "cache";
205 cache-level = <2>;
206 cache-unified;
207 next-level-cache = <&L3_0>;
208 };
209 };
210
211 cpu-map {
212 cluster0 {
213 core0 {
214 cpu = <&CPU0>;
215 };
216
217 core1 {
218 cpu = <&CPU1>;
219 };
220
221 core2 {
222 cpu = <&CPU2>;
223 };
224
225 core3 {
226 cpu = <&CPU3>;
227 };
228
229 core4 {
230 cpu = <&CPU4>;
231 };
232
233 core5 {
234 cpu = <&CPU5>;
235 };
236
237 core6 {
238 cpu = <&CPU6>;
239 };
240
241 core7 {
242 cpu = <&CPU7>;
243 };
244 };
245 };
246
247 idle-states {
248 entry-method = "psci";
249
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <360>;
255 exit-latency-us = <531>;
256 min-residency-us = <3934>;
257 local-timer-stop;
258 };
259
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <702>;
265 exit-latency-us = <1061>;
266 min-residency-us = <4488>;
267 local-timer-stop;
268 };
269 };
270
271 domain-idle-states {
272 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <2752>;
276 exit-latency-us = <3048>;
277 min-residency-us = <6118>;
278 };
279
280 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <3263>;
284 exit-latency-us = <6562>;
285 min-residency-us = <9987>;
286 };
287 };
288 };
289
290 firmware {
291 scm: scm {
292 compatible = "qcom,scm-sm8350", "qcom,scm";
293 qcom,dload-mode = <&tcsr 0x13000>;
294 #reset-cells = <1>;
295 };
296 };
297
298 memory@80000000 {
299 device_type = "memory";
300 /* We expect the bootloader to fill in the size */
301 reg = <0x0 0x80000000 0x0 0x0>;
302 };
303
304 pmu-a55 {
305 compatible = "arm,cortex-a55-pmu";
306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
307 };
308
309 pmu-a78 {
310 compatible = "arm,cortex-a78-pmu";
311 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
312 };
313
314 pmu-x1 {
315 compatible = "arm,cortex-x1-pmu";
316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
317 };
318
319 psci {
320 compatible = "arm,psci-1.0";
321 method = "smc";
322
323 CPU_PD0: power-domain-cpu0 {
324 #power-domain-cells = <0>;
325 power-domains = <&CLUSTER_PD>;
326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
327 };
328
329 CPU_PD1: power-domain-cpu1 {
330 #power-domain-cells = <0>;
331 power-domains = <&CLUSTER_PD>;
332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
333 };
334
335 CPU_PD2: power-domain-cpu2 {
336 #power-domain-cells = <0>;
337 power-domains = <&CLUSTER_PD>;
338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
339 };
340
341 CPU_PD3: power-domain-cpu3 {
342 #power-domain-cells = <0>;
343 power-domains = <&CLUSTER_PD>;
344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
345 };
346
347 CPU_PD4: power-domain-cpu4 {
348 #power-domain-cells = <0>;
349 power-domains = <&CLUSTER_PD>;
350 domain-idle-states = <&BIG_CPU_SLEEP_0>;
351 };
352
353 CPU_PD5: power-domain-cpu5 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD>;
356 domain-idle-states = <&BIG_CPU_SLEEP_0>;
357 };
358
359 CPU_PD6: power-domain-cpu6 {
360 #power-domain-cells = <0>;
361 power-domains = <&CLUSTER_PD>;
362 domain-idle-states = <&BIG_CPU_SLEEP_0>;
363 };
364
365 CPU_PD7: power-domain-cpu7 {
366 #power-domain-cells = <0>;
367 power-domains = <&CLUSTER_PD>;
368 domain-idle-states = <&BIG_CPU_SLEEP_0>;
369 };
370
371 CLUSTER_PD: power-domain-cpu-cluster0 {
372 #power-domain-cells = <0>;
373 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
374 };
375 };
376
377 qup_opp_table_100mhz: opp-table-qup100mhz {
378 compatible = "operating-points-v2";
379
380 opp-50000000 {
381 opp-hz = /bits/ 64 <50000000>;
382 required-opps = <&rpmhpd_opp_min_svs>;
383 };
384
385 opp-75000000 {
386 opp-hz = /bits/ 64 <75000000>;
387 required-opps = <&rpmhpd_opp_low_svs>;
388 };
389
390 opp-100000000 {
391 opp-hz = /bits/ 64 <100000000>;
392 required-opps = <&rpmhpd_opp_svs>;
393 };
394 };
395
396 qup_opp_table_120mhz: opp-table-qup120mhz {
397 compatible = "operating-points-v2";
398
399 opp-50000000 {
400 opp-hz = /bits/ 64 <50000000>;
401 required-opps = <&rpmhpd_opp_min_svs>;
402 };
403
404 opp-75000000 {
405 opp-hz = /bits/ 64 <75000000>;
406 required-opps = <&rpmhpd_opp_low_svs>;
407 };
408
409 opp-120000000 {
410 opp-hz = /bits/ 64 <120000000>;
411 required-opps = <&rpmhpd_opp_svs>;
412 };
413 };
414
415 reserved_memory: reserved-memory {
416 #address-cells = <2>;
417 #size-cells = <2>;
418 ranges;
419
420 hyp_mem: memory@80000000 {
421 reg = <0x0 0x80000000 0x0 0x600000>;
422 no-map;
423 };
424
425 xbl_aop_mem: memory@80700000 {
426 no-map;
427 reg = <0x0 0x80700000 0x0 0x160000>;
428 };
429
430 cmd_db: memory@80860000 {
431 compatible = "qcom,cmd-db";
432 reg = <0x0 0x80860000 0x0 0x20000>;
433 no-map;
434 };
435
436 reserved_xbl_uefi_log: memory@80880000 {
437 reg = <0x0 0x80880000 0x0 0x14000>;
438 no-map;
439 };
440
441 smem@80900000 {
442 compatible = "qcom,smem";
443 reg = <0x0 0x80900000 0x0 0x200000>;
444 hwlocks = <&tcsr_mutex 3>;
445 no-map;
446 };
447
448 cpucp_fw_mem: memory@80b00000 {
449 reg = <0x0 0x80b00000 0x0 0x100000>;
450 no-map;
451 };
452
453 cdsp_secure_heap: memory@80c00000 {
454 reg = <0x0 0x80c00000 0x0 0x4600000>;
455 no-map;
456 };
457
458 pil_camera_mem: mmeory@85200000 {
459 reg = <0x0 0x85200000 0x0 0x500000>;
460 no-map;
461 };
462
463 pil_video_mem: memory@85700000 {
464 reg = <0x0 0x85700000 0x0 0x500000>;
465 no-map;
466 };
467
468 pil_cvp_mem: memory@85c00000 {
469 reg = <0x0 0x85c00000 0x0 0x500000>;
470 no-map;
471 };
472
473 pil_adsp_mem: memory@86100000 {
474 reg = <0x0 0x86100000 0x0 0x2100000>;
475 no-map;
476 };
477
478 pil_slpi_mem: memory@88200000 {
479 reg = <0x0 0x88200000 0x0 0x1500000>;
480 no-map;
481 };
482
483 pil_cdsp_mem: memory@89700000 {
484 reg = <0x0 0x89700000 0x0 0x1e00000>;
485 no-map;
486 };
487
488 pil_ipa_fw_mem: memory@8b500000 {
489 reg = <0x0 0x8b500000 0x0 0x10000>;
490 no-map;
491 };
492
493 pil_ipa_gsi_mem: memory@8b510000 {
494 reg = <0x0 0x8b510000 0x0 0xa000>;
495 no-map;
496 };
497
498 pil_gpu_mem: memory@8b51a000 {
499 reg = <0x0 0x8b51a000 0x0 0x2000>;
500 no-map;
501 };
502
503 pil_spss_mem: memory@8b600000 {
504 reg = <0x0 0x8b600000 0x0 0x100000>;
505 no-map;
506 };
507
508 pil_modem_mem: memory@8b800000 {
509 reg = <0x0 0x8b800000 0x0 0x10000000>;
510 no-map;
511 };
512
513 rmtfs_mem: memory@9b800000 {
514 compatible = "qcom,rmtfs-mem";
515 reg = <0x0 0x9b800000 0x0 0x280000>;
516 no-map;
517
518 qcom,client-id = <1>;
519 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
520 };
521
522 hyp_reserved_mem: memory@d0000000 {
523 reg = <0x0 0xd0000000 0x0 0x800000>;
524 no-map;
525 };
526
527 pil_trustedvm_mem: memory@d0800000 {
528 reg = <0x0 0xd0800000 0x0 0x76f7000>;
529 no-map;
530 };
531
532 qrtr_shbuf: memory@d7ef7000 {
533 reg = <0x0 0xd7ef7000 0x0 0x9000>;
534 no-map;
535 };
536
537 chan0_shbuf: memory@d7f00000 {
538 reg = <0x0 0xd7f00000 0x0 0x80000>;
539 no-map;
540 };
541
542 chan1_shbuf: memory@d7f80000 {
543 reg = <0x0 0xd7f80000 0x0 0x80000>;
544 no-map;
545 };
546
547 removed_mem: memory@d8800000 {
548 reg = <0x0 0xd8800000 0x0 0x6800000>;
549 no-map;
550 };
551 };
552
553 smp2p-adsp {
554 compatible = "qcom,smp2p";
555 qcom,smem = <443>, <429>;
556 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
557 IPCC_MPROC_SIGNAL_SMP2P
558 IRQ_TYPE_EDGE_RISING>;
559 mboxes = <&ipcc IPCC_CLIENT_LPASS
560 IPCC_MPROC_SIGNAL_SMP2P>;
561
562 qcom,local-pid = <0>;
563 qcom,remote-pid = <2>;
564
565 smp2p_adsp_out: master-kernel {
566 qcom,entry-name = "master-kernel";
567 #qcom,smem-state-cells = <1>;
568 };
569
570 smp2p_adsp_in: slave-kernel {
571 qcom,entry-name = "slave-kernel";
572 interrupt-controller;
573 #interrupt-cells = <2>;
574 };
575 };
576
577 smp2p-cdsp {
578 compatible = "qcom,smp2p";
579 qcom,smem = <94>, <432>;
580 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
581 IPCC_MPROC_SIGNAL_SMP2P
582 IRQ_TYPE_EDGE_RISING>;
583 mboxes = <&ipcc IPCC_CLIENT_CDSP
584 IPCC_MPROC_SIGNAL_SMP2P>;
585
586 qcom,local-pid = <0>;
587 qcom,remote-pid = <5>;
588
589 smp2p_cdsp_out: master-kernel {
590 qcom,entry-name = "master-kernel";
591 #qcom,smem-state-cells = <1>;
592 };
593
594 smp2p_cdsp_in: slave-kernel {
595 qcom,entry-name = "slave-kernel";
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 };
599 };
600
601 smp2p-modem {
602 compatible = "qcom,smp2p";
603 qcom,smem = <435>, <428>;
604 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
605 IPCC_MPROC_SIGNAL_SMP2P
606 IRQ_TYPE_EDGE_RISING>;
607 mboxes = <&ipcc IPCC_CLIENT_MPSS
608 IPCC_MPROC_SIGNAL_SMP2P>;
609
610 qcom,local-pid = <0>;
611 qcom,remote-pid = <1>;
612
613 smp2p_modem_out: master-kernel {
614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells = <1>;
616 };
617
618 smp2p_modem_in: slave-kernel {
619 qcom,entry-name = "slave-kernel";
620 interrupt-controller;
621 #interrupt-cells = <2>;
622 };
623
624 ipa_smp2p_out: ipa-ap-to-modem {
625 qcom,entry-name = "ipa";
626 #qcom,smem-state-cells = <1>;
627 };
628
629 ipa_smp2p_in: ipa-modem-to-ap {
630 qcom,entry-name = "ipa";
631 interrupt-controller;
632 #interrupt-cells = <2>;
633 };
634 };
635
636 smp2p-slpi {
637 compatible = "qcom,smp2p";
638 qcom,smem = <481>, <430>;
639 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
640 IPCC_MPROC_SIGNAL_SMP2P
641 IRQ_TYPE_EDGE_RISING>;
642 mboxes = <&ipcc IPCC_CLIENT_SLPI
643 IPCC_MPROC_SIGNAL_SMP2P>;
644
645 qcom,local-pid = <0>;
646 qcom,remote-pid = <3>;
647
648 smp2p_slpi_out: master-kernel {
649 qcom,entry-name = "master-kernel";
650 #qcom,smem-state-cells = <1>;
651 };
652
653 smp2p_slpi_in: slave-kernel {
654 qcom,entry-name = "slave-kernel";
655 interrupt-controller;
656 #interrupt-cells = <2>;
657 };
658 };
659
660 soc: soc@0 {
661 #address-cells = <2>;
662 #size-cells = <2>;
663 ranges = <0 0 0 0 0x10 0>;
664 dma-ranges = <0 0 0 0 0x10 0>;
665 compatible = "simple-bus";
666
667 gcc: clock-controller@100000 {
668 compatible = "qcom,gcc-sm8350";
669 reg = <0x0 0x00100000 0x0 0x1f0000>;
670 #clock-cells = <1>;
671 #reset-cells = <1>;
672 #power-domain-cells = <1>;
673 clock-names = "bi_tcxo",
674 "sleep_clk",
675 "pcie_0_pipe_clk",
676 "pcie_1_pipe_clk",
677 "ufs_card_rx_symbol_0_clk",
678 "ufs_card_rx_symbol_1_clk",
679 "ufs_card_tx_symbol_0_clk",
680 "ufs_phy_rx_symbol_0_clk",
681 "ufs_phy_rx_symbol_1_clk",
682 "ufs_phy_tx_symbol_0_clk",
683 "usb3_phy_wrapper_gcc_usb30_pipe_clk",
684 "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
685 clocks = <&rpmhcc RPMH_CXO_CLK>,
686 <&sleep_clk>,
687 <&pcie0_phy>,
688 <&pcie1_phy>,
689 <0>,
690 <0>,
691 <0>,
692 <&ufs_mem_phy 0>,
693 <&ufs_mem_phy 1>,
694 <&ufs_mem_phy 2>,
695 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
696 <0>;
697 };
698
699 ipcc: mailbox@408000 {
700 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
701 reg = <0 0x00408000 0 0x1000>;
702 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-controller;
704 #interrupt-cells = <3>;
705 #mbox-cells = <2>;
706 };
707
708 gpi_dma2: dma-controller@800000 {
709 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
710 reg = <0 0x00800000 0 0x60000>;
711 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
723 dma-channels = <12>;
724 dma-channel-mask = <0xff>;
725 iommus = <&apps_smmu 0x5f6 0x0>;
726 #dma-cells = <3>;
727 status = "disabled";
728 };
729
730 qupv3_id_2: geniqup@8c0000 {
731 compatible = "qcom,geni-se-qup";
732 reg = <0x0 0x008c0000 0x0 0x6000>;
733 clock-names = "m-ahb", "s-ahb";
734 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
735 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
736 iommus = <&apps_smmu 0x5e3 0x0>;
737 #address-cells = <2>;
738 #size-cells = <2>;
739 ranges;
740 status = "disabled";
741
742 i2c14: i2c@880000 {
743 compatible = "qcom,geni-i2c";
744 reg = <0 0x00880000 0 0x4000>;
745 clock-names = "se";
746 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&qup_i2c14_default>;
749 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
750 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
751 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
752 dma-names = "tx", "rx";
753 #address-cells = <1>;
754 #size-cells = <0>;
755 status = "disabled";
756 };
757
758 spi14: spi@880000 {
759 compatible = "qcom,geni-spi";
760 reg = <0 0x00880000 0 0x4000>;
761 clock-names = "se";
762 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
763 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
764 power-domains = <&rpmhpd RPMHPD_CX>;
765 operating-points-v2 = <&qup_opp_table_120mhz>;
766 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
767 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
768 dma-names = "tx", "rx";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 status = "disabled";
772 };
773
774 i2c15: i2c@884000 {
775 compatible = "qcom,geni-i2c";
776 reg = <0 0x00884000 0 0x4000>;
777 clock-names = "se";
778 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&qup_i2c15_default>;
781 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
782 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
783 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
784 dma-names = "tx", "rx";
785 #address-cells = <1>;
786 #size-cells = <0>;
787 status = "disabled";
788 };
789
790 spi15: spi@884000 {
791 compatible = "qcom,geni-spi";
792 reg = <0 0x00884000 0 0x4000>;
793 clock-names = "se";
794 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
795 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
796 power-domains = <&rpmhpd RPMHPD_CX>;
797 operating-points-v2 = <&qup_opp_table_120mhz>;
798 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
799 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
800 dma-names = "tx", "rx";
801 #address-cells = <1>;
802 #size-cells = <0>;
803 status = "disabled";
804 };
805
806 i2c16: i2c@888000 {
807 compatible = "qcom,geni-i2c";
808 reg = <0 0x00888000 0 0x4000>;
809 clock-names = "se";
810 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&qup_i2c16_default>;
813 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
814 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
815 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
816 dma-names = "tx", "rx";
817 #address-cells = <1>;
818 #size-cells = <0>;
819 status = "disabled";
820 };
821
822 spi16: spi@888000 {
823 compatible = "qcom,geni-spi";
824 reg = <0 0x00888000 0 0x4000>;
825 clock-names = "se";
826 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
827 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
828 power-domains = <&rpmhpd RPMHPD_CX>;
829 operating-points-v2 = <&qup_opp_table_100mhz>;
830 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
831 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
832 dma-names = "tx", "rx";
833 #address-cells = <1>;
834 #size-cells = <0>;
835 status = "disabled";
836 };
837
838 i2c17: i2c@88c000 {
839 compatible = "qcom,geni-i2c";
840 reg = <0 0x0088c000 0 0x4000>;
841 clock-names = "se";
842 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
843 pinctrl-names = "default";
844 pinctrl-0 = <&qup_i2c17_default>;
845 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
846 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
847 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
848 dma-names = "tx", "rx";
849 #address-cells = <1>;
850 #size-cells = <0>;
851 status = "disabled";
852 };
853
854 spi17: spi@88c000 {
855 compatible = "qcom,geni-spi";
856 reg = <0 0x0088c000 0 0x4000>;
857 clock-names = "se";
858 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
859 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
860 power-domains = <&rpmhpd RPMHPD_CX>;
861 operating-points-v2 = <&qup_opp_table_100mhz>;
862 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
863 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
864 dma-names = "tx", "rx";
865 #address-cells = <1>;
866 #size-cells = <0>;
867 status = "disabled";
868 };
869
870 /* QUP no. 18 seems to be strictly SPI/UART-only */
871
872 spi18: spi@890000 {
873 compatible = "qcom,geni-spi";
874 reg = <0 0x00890000 0 0x4000>;
875 clock-names = "se";
876 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
877 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
878 power-domains = <&rpmhpd RPMHPD_CX>;
879 operating-points-v2 = <&qup_opp_table_100mhz>;
880 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
881 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
882 dma-names = "tx", "rx";
883 #address-cells = <1>;
884 #size-cells = <0>;
885 status = "disabled";
886 };
887
888 uart18: serial@890000 {
889 compatible = "qcom,geni-uart";
890 reg = <0 0x00890000 0 0x4000>;
891 clock-names = "se";
892 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_uart18_default>;
895 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
896 power-domains = <&rpmhpd RPMHPD_CX>;
897 operating-points-v2 = <&qup_opp_table_100mhz>;
898 status = "disabled";
899 };
900
901 i2c19: i2c@894000 {
902 compatible = "qcom,geni-i2c";
903 reg = <0 0x00894000 0 0x4000>;
904 clock-names = "se";
905 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
906 pinctrl-names = "default";
907 pinctrl-0 = <&qup_i2c19_default>;
908 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
909 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
910 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
911 dma-names = "tx", "rx";
912 #address-cells = <1>;
913 #size-cells = <0>;
914 status = "disabled";
915 };
916
917 spi19: spi@894000 {
918 compatible = "qcom,geni-spi";
919 reg = <0 0x00894000 0 0x4000>;
920 clock-names = "se";
921 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
922 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
923 power-domains = <&rpmhpd RPMHPD_CX>;
924 operating-points-v2 = <&qup_opp_table_100mhz>;
925 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
926 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
927 dma-names = "tx", "rx";
928 #address-cells = <1>;
929 #size-cells = <0>;
930 status = "disabled";
931 };
932 };
933
934 gpi_dma0: dma-controller@900000 {
935 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
936 reg = <0 0x00900000 0 0x60000>;
937 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
949 dma-channels = <12>;
950 dma-channel-mask = <0x7e>;
951 iommus = <&apps_smmu 0x5b6 0x0>;
952 #dma-cells = <3>;
953 status = "disabled";
954 };
955
956 qupv3_id_0: geniqup@9c0000 {
957 compatible = "qcom,geni-se-qup";
958 reg = <0x0 0x009c0000 0x0 0x6000>;
959 clock-names = "m-ahb", "s-ahb";
960 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
961 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
962 iommus = <&apps_smmu 0x5a3 0>;
963 #address-cells = <2>;
964 #size-cells = <2>;
965 ranges;
966 status = "disabled";
967
968 i2c0: i2c@980000 {
969 compatible = "qcom,geni-i2c";
970 reg = <0 0x00980000 0 0x4000>;
971 clock-names = "se";
972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_i2c0_default>;
975 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
976 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
977 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
978 dma-names = "tx", "rx";
979 #address-cells = <1>;
980 #size-cells = <0>;
981 status = "disabled";
982 };
983
984 spi0: spi@980000 {
985 compatible = "qcom,geni-spi";
986 reg = <0 0x00980000 0 0x4000>;
987 clock-names = "se";
988 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
989 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
990 power-domains = <&rpmhpd RPMHPD_CX>;
991 operating-points-v2 = <&qup_opp_table_100mhz>;
992 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
993 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
994 dma-names = "tx", "rx";
995 #address-cells = <1>;
996 #size-cells = <0>;
997 status = "disabled";
998 };
999
1000 i2c1: i2c@984000 {
1001 compatible = "qcom,geni-i2c";
1002 reg = <0 0x00984000 0 0x4000>;
1003 clock-names = "se";
1004 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c1_default>;
1007 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1008 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1009 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1010 dma-names = "tx", "rx";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 status = "disabled";
1014 };
1015
1016 spi1: spi@984000 {
1017 compatible = "qcom,geni-spi";
1018 reg = <0 0x00984000 0 0x4000>;
1019 clock-names = "se";
1020 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1021 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1022 power-domains = <&rpmhpd RPMHPD_CX>;
1023 operating-points-v2 = <&qup_opp_table_100mhz>;
1024 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1025 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1026 dma-names = "tx", "rx";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1029 status = "disabled";
1030 };
1031
1032 i2c2: i2c@988000 {
1033 compatible = "qcom,geni-i2c";
1034 reg = <0 0x00988000 0 0x4000>;
1035 clock-names = "se";
1036 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1037 pinctrl-names = "default";
1038 pinctrl-0 = <&qup_i2c2_default>;
1039 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1040 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1041 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1042 dma-names = "tx", "rx";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 status = "disabled";
1046 };
1047
1048 spi2: spi@988000 {
1049 compatible = "qcom,geni-spi";
1050 reg = <0 0x00988000 0 0x4000>;
1051 clock-names = "se";
1052 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1053 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1054 power-domains = <&rpmhpd RPMHPD_CX>;
1055 operating-points-v2 = <&qup_opp_table_100mhz>;
1056 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1057 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1058 dma-names = "tx", "rx";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 status = "disabled";
1062 };
1063
1064 uart2: serial@98c000 {
1065 compatible = "qcom,geni-debug-uart";
1066 reg = <0 0x0098c000 0 0x4000>;
1067 clock-names = "se";
1068 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&qup_uart3_default_state>;
1071 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1072 power-domains = <&rpmhpd RPMHPD_CX>;
1073 operating-points-v2 = <&qup_opp_table_100mhz>;
1074 status = "disabled";
1075 };
1076
1077 /* QUP no. 3 seems to be strictly SPI-only */
1078
1079 spi3: spi@98c000 {
1080 compatible = "qcom,geni-spi";
1081 reg = <0 0x0098c000 0 0x4000>;
1082 clock-names = "se";
1083 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1084 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1085 power-domains = <&rpmhpd RPMHPD_CX>;
1086 operating-points-v2 = <&qup_opp_table_100mhz>;
1087 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1088 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 status = "disabled";
1093 };
1094
1095 i2c4: i2c@990000 {
1096 compatible = "qcom,geni-i2c";
1097 reg = <0 0x00990000 0 0x4000>;
1098 clock-names = "se";
1099 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&qup_i2c4_default>;
1102 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1103 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1104 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1105 dma-names = "tx", "rx";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1108 status = "disabled";
1109 };
1110
1111 spi4: spi@990000 {
1112 compatible = "qcom,geni-spi";
1113 reg = <0 0x00990000 0 0x4000>;
1114 clock-names = "se";
1115 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1116 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1117 power-domains = <&rpmhpd RPMHPD_CX>;
1118 operating-points-v2 = <&qup_opp_table_100mhz>;
1119 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1120 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1121 dma-names = "tx", "rx";
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1124 status = "disabled";
1125 };
1126
1127 i2c5: i2c@994000 {
1128 compatible = "qcom,geni-i2c";
1129 reg = <0 0x00994000 0 0x4000>;
1130 clock-names = "se";
1131 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c5_default>;
1134 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1135 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1136 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1137 dma-names = "tx", "rx";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 status = "disabled";
1141 };
1142
1143 spi5: spi@994000 {
1144 compatible = "qcom,geni-spi";
1145 reg = <0 0x00994000 0 0x4000>;
1146 clock-names = "se";
1147 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1149 power-domains = <&rpmhpd RPMHPD_CX>;
1150 operating-points-v2 = <&qup_opp_table_100mhz>;
1151 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1152 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1153 dma-names = "tx", "rx";
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1156 status = "disabled";
1157 };
1158
1159 i2c6: i2c@998000 {
1160 compatible = "qcom,geni-i2c";
1161 reg = <0 0x00998000 0 0x4000>;
1162 clock-names = "se";
1163 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_i2c6_default>;
1166 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1167 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1168 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1169 dma-names = "tx", "rx";
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 status = "disabled";
1173 };
1174
1175 spi6: spi@998000 {
1176 compatible = "qcom,geni-spi";
1177 reg = <0 0x00998000 0 0x4000>;
1178 clock-names = "se";
1179 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1180 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1181 power-domains = <&rpmhpd RPMHPD_CX>;
1182 operating-points-v2 = <&qup_opp_table_100mhz>;
1183 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1184 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1185 dma-names = "tx", "rx";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 status = "disabled";
1189 };
1190
1191 uart6: serial@998000 {
1192 compatible = "qcom,geni-uart";
1193 reg = <0 0x00998000 0 0x4000>;
1194 clock-names = "se";
1195 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_uart6_default>;
1198 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1199 power-domains = <&rpmhpd RPMHPD_CX>;
1200 operating-points-v2 = <&qup_opp_table_100mhz>;
1201 status = "disabled";
1202 };
1203
1204 i2c7: i2c@99c000 {
1205 compatible = "qcom,geni-i2c";
1206 reg = <0 0x0099c000 0 0x4000>;
1207 clock-names = "se";
1208 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&qup_i2c7_default>;
1211 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1212 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1213 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1214 dma-names = "tx", "rx";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 status = "disabled";
1218 };
1219
1220 spi7: spi@99c000 {
1221 compatible = "qcom,geni-spi";
1222 reg = <0 0x0099c000 0 0x4000>;
1223 clock-names = "se";
1224 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1225 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1226 power-domains = <&rpmhpd RPMHPD_CX>;
1227 operating-points-v2 = <&qup_opp_table_100mhz>;
1228 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1229 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1230 dma-names = "tx", "rx";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1233 status = "disabled";
1234 };
1235 };
1236
1237 gpi_dma1: dma-controller@a00000 {
1238 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1239 reg = <0 0x00a00000 0 0x60000>;
1240 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1252 dma-channels = <12>;
1253 dma-channel-mask = <0xff>;
1254 iommus = <&apps_smmu 0x56 0x0>;
1255 #dma-cells = <3>;
1256 status = "disabled";
1257 };
1258
1259 qupv3_id_1: geniqup@ac0000 {
1260 compatible = "qcom,geni-se-qup";
1261 reg = <0x0 0x00ac0000 0x0 0x6000>;
1262 clock-names = "m-ahb", "s-ahb";
1263 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1264 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1265 iommus = <&apps_smmu 0x43 0>;
1266 #address-cells = <2>;
1267 #size-cells = <2>;
1268 ranges;
1269 status = "disabled";
1270
1271 i2c8: i2c@a80000 {
1272 compatible = "qcom,geni-i2c";
1273 reg = <0 0x00a80000 0 0x4000>;
1274 clock-names = "se";
1275 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&qup_i2c8_default>;
1278 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1279 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1280 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1281 dma-names = "tx", "rx";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 status = "disabled";
1285 };
1286
1287 spi8: spi@a80000 {
1288 compatible = "qcom,geni-spi";
1289 reg = <0 0x00a80000 0 0x4000>;
1290 clock-names = "se";
1291 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1292 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1293 power-domains = <&rpmhpd RPMHPD_CX>;
1294 operating-points-v2 = <&qup_opp_table_120mhz>;
1295 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1296 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1297 dma-names = "tx", "rx";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1300 status = "disabled";
1301 };
1302
1303 i2c9: i2c@a84000 {
1304 compatible = "qcom,geni-i2c";
1305 reg = <0 0x00a84000 0 0x4000>;
1306 clock-names = "se";
1307 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_i2c9_default>;
1310 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1311 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1312 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1313 dma-names = "tx", "rx";
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1316 status = "disabled";
1317 };
1318
1319 spi9: spi@a84000 {
1320 compatible = "qcom,geni-spi";
1321 reg = <0 0x00a84000 0 0x4000>;
1322 clock-names = "se";
1323 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1324 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains = <&rpmhpd RPMHPD_CX>;
1326 operating-points-v2 = <&qup_opp_table_100mhz>;
1327 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1328 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1329 dma-names = "tx", "rx";
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1332 status = "disabled";
1333 };
1334
1335 i2c10: i2c@a88000 {
1336 compatible = "qcom,geni-i2c";
1337 reg = <0 0x00a88000 0 0x4000>;
1338 clock-names = "se";
1339 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&qup_i2c10_default>;
1342 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1343 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1344 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1345 dma-names = "tx", "rx";
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1348 status = "disabled";
1349 };
1350
1351 spi10: spi@a88000 {
1352 compatible = "qcom,geni-spi";
1353 reg = <0 0x00a88000 0 0x4000>;
1354 clock-names = "se";
1355 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1356 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1357 power-domains = <&rpmhpd RPMHPD_CX>;
1358 operating-points-v2 = <&qup_opp_table_100mhz>;
1359 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1360 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1361 dma-names = "tx", "rx";
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 status = "disabled";
1365 };
1366
1367 i2c11: i2c@a8c000 {
1368 compatible = "qcom,geni-i2c";
1369 reg = <0 0x00a8c000 0 0x4000>;
1370 clock-names = "se";
1371 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&qup_i2c11_default>;
1374 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1375 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1376 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1377 dma-names = "tx", "rx";
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1380 status = "disabled";
1381 };
1382
1383 spi11: spi@a8c000 {
1384 compatible = "qcom,geni-spi";
1385 reg = <0 0x00a8c000 0 0x4000>;
1386 clock-names = "se";
1387 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1388 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1389 power-domains = <&rpmhpd RPMHPD_CX>;
1390 operating-points-v2 = <&qup_opp_table_100mhz>;
1391 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1392 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1393 dma-names = "tx", "rx";
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396 status = "disabled";
1397 };
1398
1399 i2c12: i2c@a90000 {
1400 compatible = "qcom,geni-i2c";
1401 reg = <0 0x00a90000 0 0x4000>;
1402 clock-names = "se";
1403 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1404 pinctrl-names = "default";
1405 pinctrl-0 = <&qup_i2c12_default>;
1406 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1407 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1408 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1409 dma-names = "tx", "rx";
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1412 status = "disabled";
1413 };
1414
1415 spi12: spi@a90000 {
1416 compatible = "qcom,geni-spi";
1417 reg = <0 0x00a90000 0 0x4000>;
1418 clock-names = "se";
1419 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1420 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1421 power-domains = <&rpmhpd RPMHPD_CX>;
1422 operating-points-v2 = <&qup_opp_table_100mhz>;
1423 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1424 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1425 dma-names = "tx", "rx";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428 status = "disabled";
1429 };
1430
1431 i2c13: i2c@a94000 {
1432 compatible = "qcom,geni-i2c";
1433 reg = <0 0x00a94000 0 0x4000>;
1434 clock-names = "se";
1435 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_i2c13_default>;
1438 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1439 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1440 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1441 dma-names = "tx", "rx";
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1444 status = "disabled";
1445 };
1446
1447 spi13: spi@a94000 {
1448 compatible = "qcom,geni-spi";
1449 reg = <0 0x00a94000 0 0x4000>;
1450 clock-names = "se";
1451 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1452 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1453 power-domains = <&rpmhpd RPMHPD_CX>;
1454 operating-points-v2 = <&qup_opp_table_100mhz>;
1455 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1456 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1457 dma-names = "tx", "rx";
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1460 status = "disabled";
1461 };
1462 };
1463
1464 rng: rng@10d3000 {
1465 compatible = "qcom,prng-ee";
1466 reg = <0 0x010d3000 0 0x1000>;
1467 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1468 clock-names = "core";
1469 };
1470
1471 config_noc: interconnect@1500000 {
1472 compatible = "qcom,sm8350-config-noc";
1473 reg = <0 0x01500000 0 0xa580>;
1474 #interconnect-cells = <2>;
1475 qcom,bcm-voters = <&apps_bcm_voter>;
1476 };
1477
1478 mc_virt: interconnect@1580000 {
1479 compatible = "qcom,sm8350-mc-virt";
1480 reg = <0 0x01580000 0 0x1000>;
1481 #interconnect-cells = <2>;
1482 qcom,bcm-voters = <&apps_bcm_voter>;
1483 };
1484
1485 system_noc: interconnect@1680000 {
1486 compatible = "qcom,sm8350-system-noc";
1487 reg = <0 0x01680000 0 0x1c200>;
1488 #interconnect-cells = <2>;
1489 qcom,bcm-voters = <&apps_bcm_voter>;
1490 };
1491
1492 aggre1_noc: interconnect@16e0000 {
1493 compatible = "qcom,sm8350-aggre1-noc";
1494 reg = <0 0x016e0000 0 0x1f180>;
1495 #interconnect-cells = <2>;
1496 qcom,bcm-voters = <&apps_bcm_voter>;
1497 };
1498
1499 aggre2_noc: interconnect@1700000 {
1500 compatible = "qcom,sm8350-aggre2-noc";
1501 reg = <0 0x01700000 0 0x33000>;
1502 #interconnect-cells = <2>;
1503 qcom,bcm-voters = <&apps_bcm_voter>;
1504 };
1505
1506 mmss_noc: interconnect@1740000 {
1507 compatible = "qcom,sm8350-mmss-noc";
1508 reg = <0 0x01740000 0 0x1f080>;
1509 #interconnect-cells = <2>;
1510 qcom,bcm-voters = <&apps_bcm_voter>;
1511 };
1512
1513 pcie0: pcie@1c00000 {
1514 compatible = "qcom,pcie-sm8350";
1515 reg = <0 0x01c00000 0 0x3000>,
1516 <0 0x60000000 0 0xf1d>,
1517 <0 0x60000f20 0 0xa8>,
1518 <0 0x60001000 0 0x1000>,
1519 <0 0x60100000 0 0x100000>;
1520 reg-names = "parf", "dbi", "elbi", "atu", "config";
1521 device_type = "pci";
1522 linux,pci-domain = <0>;
1523 bus-range = <0x00 0xff>;
1524 num-lanes = <1>;
1525
1526 #address-cells = <3>;
1527 #size-cells = <2>;
1528
1529 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1530 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1531
1532 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1540 interrupt-names = "msi0",
1541 "msi1",
1542 "msi2",
1543 "msi3",
1544 "msi4",
1545 "msi5",
1546 "msi6",
1547 "msi7";
1548 #interrupt-cells = <1>;
1549 interrupt-map-mask = <0 0 0 0x7>;
1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1551 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1552 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1553 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1554
1555 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1556 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1557 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1558 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1559 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1560 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1561 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1562 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1563 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1564 clock-names = "aux",
1565 "cfg",
1566 "bus_master",
1567 "bus_slave",
1568 "slave_q2a",
1569 "tbu",
1570 "ddrss_sf_tbu",
1571 "aggre1",
1572 "aggre0";
1573
1574 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1575 <0x100 &apps_smmu 0x1c01 0x1>;
1576
1577 resets = <&gcc GCC_PCIE_0_BCR>;
1578 reset-names = "pci";
1579
1580 power-domains = <&gcc PCIE_0_GDSC>;
1581
1582 phys = <&pcie0_phy>;
1583 phy-names = "pciephy";
1584
1585 status = "disabled";
1586
1587 pcie@0 {
1588 device_type = "pci";
1589 reg = <0x0 0x0 0x0 0x0 0x0>;
1590 bus-range = <0x01 0xff>;
1591
1592 #address-cells = <3>;
1593 #size-cells = <2>;
1594 ranges;
1595 };
1596 };
1597
1598 pcie0_phy: phy@1c06000 {
1599 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1600 reg = <0 0x01c06000 0 0x2000>;
1601 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1602 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1603 <&gcc GCC_PCIE_0_CLKREF_EN>,
1604 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1605 <&gcc GCC_PCIE_0_PIPE_CLK>;
1606 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1607
1608 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1609 reset-names = "phy";
1610
1611 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1612 assigned-clock-rates = <100000000>;
1613
1614 #clock-cells = <0>;
1615 clock-output-names = "pcie_0_pipe_clk";
1616
1617 #phy-cells = <0>;
1618
1619 status = "disabled";
1620 };
1621
1622 pcie1: pcie@1c08000 {
1623 compatible = "qcom,pcie-sm8350";
1624 reg = <0 0x01c08000 0 0x3000>,
1625 <0 0x40000000 0 0xf1d>,
1626 <0 0x40000f20 0 0xa8>,
1627 <0 0x40001000 0 0x1000>,
1628 <0 0x40100000 0 0x100000>;
1629 reg-names = "parf", "dbi", "elbi", "atu", "config";
1630 device_type = "pci";
1631 linux,pci-domain = <1>;
1632 bus-range = <0x00 0xff>;
1633 num-lanes = <2>;
1634
1635 #address-cells = <3>;
1636 #size-cells = <2>;
1637
1638 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1639 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1640
1641 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1642 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1643 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1648 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1649 interrupt-names = "msi0",
1650 "msi1",
1651 "msi2",
1652 "msi3",
1653 "msi4",
1654 "msi5",
1655 "msi6",
1656 "msi7";
1657 #interrupt-cells = <1>;
1658 interrupt-map-mask = <0 0 0 0x7>;
1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1660 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1661 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1662 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1663
1664 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1665 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1666 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1667 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1668 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1669 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1670 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1671 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1672 clock-names = "aux",
1673 "cfg",
1674 "bus_master",
1675 "bus_slave",
1676 "slave_q2a",
1677 "tbu",
1678 "ddrss_sf_tbu",
1679 "aggre1";
1680
1681 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1682 <0x100 &apps_smmu 0x1c81 0x1>;
1683
1684 resets = <&gcc GCC_PCIE_1_BCR>;
1685 reset-names = "pci";
1686
1687 power-domains = <&gcc PCIE_1_GDSC>;
1688
1689 phys = <&pcie1_phy>;
1690 phy-names = "pciephy";
1691
1692 status = "disabled";
1693
1694 pcie@0 {
1695 device_type = "pci";
1696 reg = <0x0 0x0 0x0 0x0 0x0>;
1697 bus-range = <0x01 0xff>;
1698
1699 #address-cells = <3>;
1700 #size-cells = <2>;
1701 ranges;
1702 };
1703 };
1704
1705 pcie1_phy: phy@1c0e000 {
1706 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1707 reg = <0 0x01c0e000 0 0x2000>;
1708 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1709 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1710 <&gcc GCC_PCIE_1_CLKREF_EN>,
1711 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1712 <&gcc GCC_PCIE_1_PIPE_CLK>;
1713 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1714
1715 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1716 reset-names = "phy";
1717
1718 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1719 assigned-clock-rates = <100000000>;
1720
1721 #clock-cells = <0>;
1722 clock-output-names = "pcie_1_pipe_clk";
1723
1724 #phy-cells = <0>;
1725
1726 status = "disabled";
1727 };
1728
1729 ufs_mem_hc: ufshc@1d84000 {
1730 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1731 "jedec,ufs-2.0";
1732 reg = <0 0x01d84000 0 0x3000>;
1733 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1734 phys = <&ufs_mem_phy>;
1735 phy-names = "ufsphy";
1736 lanes-per-direction = <2>;
1737 #reset-cells = <1>;
1738 resets = <&gcc GCC_UFS_PHY_BCR>;
1739 reset-names = "rst";
1740
1741 power-domains = <&gcc UFS_PHY_GDSC>;
1742
1743 iommus = <&apps_smmu 0xe0 0x0>;
1744 dma-coherent;
1745
1746 clock-names =
1747 "core_clk",
1748 "bus_aggr_clk",
1749 "iface_clk",
1750 "core_clk_unipro",
1751 "ref_clk",
1752 "tx_lane0_sync_clk",
1753 "rx_lane0_sync_clk",
1754 "rx_lane1_sync_clk";
1755 clocks =
1756 <&gcc GCC_UFS_PHY_AXI_CLK>,
1757 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1758 <&gcc GCC_UFS_PHY_AHB_CLK>,
1759 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1760 <&rpmhcc RPMH_CXO_CLK>,
1761 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1762 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1763 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1764 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
1765 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1766 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1767 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
1768 interconnect-names = "ufs-ddr", "cpu-ufs";
1769 freq-table-hz =
1770 <75000000 300000000>,
1771 <0 0>,
1772 <0 0>,
1773 <75000000 300000000>,
1774 <0 0>,
1775 <0 0>,
1776 <0 0>,
1777 <0 0>;
1778 status = "disabled";
1779 };
1780
1781 ufs_mem_phy: phy@1d87000 {
1782 compatible = "qcom,sm8350-qmp-ufs-phy";
1783 reg = <0 0x01d87000 0 0x1000>;
1784
1785 clocks = <&rpmhcc RPMH_CXO_CLK>,
1786 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1787 <&gcc GCC_UFS_1_CLKREF_EN>;
1788 clock-names = "ref",
1789 "ref_aux",
1790 "qref";
1791
1792 power-domains = <&gcc UFS_PHY_GDSC>;
1793
1794 resets = <&ufs_mem_hc 0>;
1795 reset-names = "ufsphy";
1796
1797 #clock-cells = <1>;
1798 #phy-cells = <0>;
1799
1800 status = "disabled";
1801 };
1802
1803 cryptobam: dma-controller@1dc4000 {
1804 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1805 reg = <0 0x01dc4000 0 0x24000>;
1806 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1807 #dma-cells = <1>;
1808 qcom,ee = <0>;
1809 qcom,controlled-remotely;
1810 iommus = <&apps_smmu 0x594 0x0011>,
1811 <&apps_smmu 0x596 0x0011>;
1812 /* FIXME: Probing BAM DMA causes some abort and system hang */
1813 status = "fail";
1814 };
1815
1816 crypto: crypto@1dfa000 {
1817 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1818 reg = <0 0x01dfa000 0 0x6000>;
1819 dmas = <&cryptobam 4>, <&cryptobam 5>;
1820 dma-names = "rx", "tx";
1821 iommus = <&apps_smmu 0x594 0x0011>,
1822 <&apps_smmu 0x596 0x0011>;
1823 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1824 interconnect-names = "memory";
1825 /* FIXME: dependency BAM DMA is disabled */
1826 status = "disabled";
1827 };
1828
1829 ipa: ipa@1e40000 {
1830 compatible = "qcom,sm8350-ipa";
1831
1832 iommus = <&apps_smmu 0x5c0 0x0>,
1833 <&apps_smmu 0x5c2 0x0>;
1834 reg = <0 0x01e40000 0 0x8000>,
1835 <0 0x01e50000 0 0x4b20>,
1836 <0 0x01e04000 0 0x23000>;
1837 reg-names = "ipa-reg",
1838 "ipa-shared",
1839 "gsi";
1840
1841 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1842 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1843 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1844 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1845 interrupt-names = "ipa",
1846 "gsi",
1847 "ipa-clock-query",
1848 "ipa-setup-ready";
1849
1850 clocks = <&rpmhcc RPMH_IPA_CLK>;
1851 clock-names = "core";
1852
1853 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1855 interconnect-names = "memory",
1856 "config";
1857
1858 qcom,qmp = <&aoss_qmp>;
1859
1860 qcom,smem-states = <&ipa_smp2p_out 0>,
1861 <&ipa_smp2p_out 1>;
1862 qcom,smem-state-names = "ipa-clock-enabled-valid",
1863 "ipa-clock-enabled";
1864
1865 status = "disabled";
1866 };
1867
1868 tcsr_mutex: hwlock@1f40000 {
1869 compatible = "qcom,tcsr-mutex";
1870 reg = <0x0 0x01f40000 0x0 0x40000>;
1871 #hwlock-cells = <1>;
1872 };
1873
1874 tcsr: syscon@1fc0000 {
1875 compatible = "qcom,sm8350-tcsr", "syscon";
1876 reg = <0x0 0x1fc0000 0x0 0x30000>;
1877 };
1878
1879 lpass_tlmm: pinctrl@33c0000 {
1880 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
1881 reg = <0 0x033c0000 0 0x20000>,
1882 <0 0x03550000 0 0x10000>;
1883
1884 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1885 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1886 clock-names = "core", "audio";
1887
1888 gpio-controller;
1889 #gpio-cells = <2>;
1890 gpio-ranges = <&lpass_tlmm 0 0 15>;
1891 };
1892
1893 gpu: gpu@3d00000 {
1894 compatible = "qcom,adreno-660.1", "qcom,adreno";
1895
1896 reg = <0 0x03d00000 0 0x40000>,
1897 <0 0x03d9e000 0 0x1000>,
1898 <0 0x03d61000 0 0x800>;
1899 reg-names = "kgsl_3d0_reg_memory",
1900 "cx_mem",
1901 "cx_dbgc";
1902
1903 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1904
1905 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1906
1907 operating-points-v2 = <&gpu_opp_table>;
1908
1909 qcom,gmu = <&gmu>;
1910 #cooling-cells = <2>;
1911
1912 status = "disabled";
1913
1914 zap-shader {
1915 memory-region = <&pil_gpu_mem>;
1916 };
1917
1918 /* note: downstream checks gpu binning for 670 Mhz */
1919 gpu_opp_table: opp-table {
1920 compatible = "operating-points-v2";
1921
1922 opp-840000000 {
1923 opp-hz = /bits/ 64 <840000000>;
1924 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1925 };
1926
1927 opp-778000000 {
1928 opp-hz = /bits/ 64 <778000000>;
1929 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1930 };
1931
1932 opp-738000000 {
1933 opp-hz = /bits/ 64 <738000000>;
1934 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1935 };
1936
1937 opp-676000000 {
1938 opp-hz = /bits/ 64 <676000000>;
1939 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1940 };
1941
1942 opp-608000000 {
1943 opp-hz = /bits/ 64 <608000000>;
1944 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1945 };
1946
1947 opp-540000000 {
1948 opp-hz = /bits/ 64 <540000000>;
1949 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1950 };
1951
1952 opp-491000000 {
1953 opp-hz = /bits/ 64 <491000000>;
1954 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1955 };
1956
1957 opp-443000000 {
1958 opp-hz = /bits/ 64 <443000000>;
1959 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1960 };
1961
1962 opp-379000000 {
1963 opp-hz = /bits/ 64 <379000000>;
1964 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1965 };
1966
1967 opp-315000000 {
1968 opp-hz = /bits/ 64 <315000000>;
1969 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1970 };
1971 };
1972 };
1973
1974 gmu: gmu@3d6a000 {
1975 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1976
1977 reg = <0 0x03d6a000 0 0x34000>,
1978 <0 0x03de0000 0 0x10000>,
1979 <0 0x0b290000 0 0x10000>;
1980 reg-names = "gmu", "rscc", "gmu_pdc";
1981
1982 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1984 interrupt-names = "hfi", "gmu";
1985
1986 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1987 <&gpucc GPU_CC_CXO_CLK>,
1988 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1989 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1990 <&gpucc GPU_CC_AHB_CLK>,
1991 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1992 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
1993 clock-names = "gmu",
1994 "cxo",
1995 "axi",
1996 "memnoc",
1997 "ahb",
1998 "hub",
1999 "smmu_vote";
2000
2001 power-domains = <&gpucc GPU_CX_GDSC>,
2002 <&gpucc GPU_GX_GDSC>;
2003 power-domain-names = "cx",
2004 "gx";
2005
2006 iommus = <&adreno_smmu 5 0x400>;
2007
2008 operating-points-v2 = <&gmu_opp_table>;
2009
2010 gmu_opp_table: opp-table {
2011 compatible = "operating-points-v2";
2012
2013 opp-200000000 {
2014 opp-hz = /bits/ 64 <200000000>;
2015 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2016 };
2017 };
2018 };
2019
2020 gpucc: clock-controller@3d90000 {
2021 compatible = "qcom,sm8350-gpucc";
2022 reg = <0 0x03d90000 0 0x9000>;
2023 clocks = <&rpmhcc RPMH_CXO_CLK>,
2024 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2025 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2026 clock-names = "bi_tcxo",
2027 "gcc_gpu_gpll0_clk_src",
2028 "gcc_gpu_gpll0_div_clk_src";
2029 #clock-cells = <1>;
2030 #reset-cells = <1>;
2031 #power-domain-cells = <1>;
2032 };
2033
2034 adreno_smmu: iommu@3da0000 {
2035 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
2036 "qcom,smmu-500", "arm,mmu-500";
2037 reg = <0 0x03da0000 0 0x20000>;
2038 #iommu-cells = <2>;
2039 #global-interrupts = <2>;
2040 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2044 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2045 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2046 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2047 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2048 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2049 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2051 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2052
2053 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2054 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2055 <&gpucc GPU_CC_AHB_CLK>,
2056 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2057 <&gpucc GPU_CC_CX_GMU_CLK>,
2058 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2059 <&gpucc GPU_CC_HUB_AON_CLK>;
2060 clock-names = "bus",
2061 "iface",
2062 "ahb",
2063 "hlos1_vote_gpu_smmu",
2064 "cx_gmu",
2065 "hub_cx_int",
2066 "hub_aon";
2067
2068 power-domains = <&gpucc GPU_CX_GDSC>;
2069 dma-coherent;
2070 };
2071
2072 lpass_ag_noc: interconnect@3c40000 {
2073 compatible = "qcom,sm8350-lpass-ag-noc";
2074 reg = <0 0x03c40000 0 0xf080>;
2075 #interconnect-cells = <2>;
2076 qcom,bcm-voters = <&apps_bcm_voter>;
2077 };
2078
2079 mpss: remoteproc@4080000 {
2080 compatible = "qcom,sm8350-mpss-pas";
2081 reg = <0x0 0x04080000 0x0 0x4040>;
2082
2083 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2084 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2085 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2086 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2087 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2088 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2089 interrupt-names = "wdog", "fatal", "ready", "handover",
2090 "stop-ack", "shutdown-ack";
2091
2092 clocks = <&rpmhcc RPMH_CXO_CLK>;
2093 clock-names = "xo";
2094
2095 power-domains = <&rpmhpd RPMHPD_CX>,
2096 <&rpmhpd RPMHPD_MSS>;
2097 power-domain-names = "cx", "mss";
2098
2099 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2100
2101 memory-region = <&pil_modem_mem>;
2102
2103 qcom,qmp = <&aoss_qmp>;
2104
2105 qcom,smem-states = <&smp2p_modem_out 0>;
2106 qcom,smem-state-names = "stop";
2107
2108 status = "disabled";
2109
2110 glink-edge {
2111 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2112 IPCC_MPROC_SIGNAL_GLINK_QMP
2113 IRQ_TYPE_EDGE_RISING>;
2114 mboxes = <&ipcc IPCC_CLIENT_MPSS
2115 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2116 label = "modem";
2117 qcom,remote-pid = <1>;
2118 };
2119 };
2120
2121 slpi: remoteproc@5c00000 {
2122 compatible = "qcom,sm8350-slpi-pas";
2123 reg = <0 0x05c00000 0 0x4000>;
2124
2125 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2126 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2127 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2128 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2129 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2130 interrupt-names = "wdog", "fatal", "ready",
2131 "handover", "stop-ack";
2132
2133 clocks = <&rpmhcc RPMH_CXO_CLK>;
2134 clock-names = "xo";
2135
2136 power-domains = <&rpmhpd RPMHPD_LCX>,
2137 <&rpmhpd RPMHPD_LMX>;
2138 power-domain-names = "lcx", "lmx";
2139
2140 memory-region = <&pil_slpi_mem>;
2141
2142 qcom,qmp = <&aoss_qmp>;
2143
2144 qcom,smem-states = <&smp2p_slpi_out 0>;
2145 qcom,smem-state-names = "stop";
2146
2147 status = "disabled";
2148
2149 glink-edge {
2150 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2151 IPCC_MPROC_SIGNAL_GLINK_QMP
2152 IRQ_TYPE_EDGE_RISING>;
2153 mboxes = <&ipcc IPCC_CLIENT_SLPI
2154 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2155
2156 label = "slpi";
2157 qcom,remote-pid = <3>;
2158
2159 fastrpc {
2160 compatible = "qcom,fastrpc";
2161 qcom,glink-channels = "fastrpcglink-apps-dsp";
2162 label = "sdsp";
2163 qcom,non-secure-domain;
2164 #address-cells = <1>;
2165 #size-cells = <0>;
2166
2167 compute-cb@1 {
2168 compatible = "qcom,fastrpc-compute-cb";
2169 reg = <1>;
2170 iommus = <&apps_smmu 0x0541 0x0>;
2171 };
2172
2173 compute-cb@2 {
2174 compatible = "qcom,fastrpc-compute-cb";
2175 reg = <2>;
2176 iommus = <&apps_smmu 0x0542 0x0>;
2177 };
2178
2179 compute-cb@3 {
2180 compatible = "qcom,fastrpc-compute-cb";
2181 reg = <3>;
2182 iommus = <&apps_smmu 0x0543 0x0>;
2183 /* note: shared-cb = <4> in downstream */
2184 };
2185 };
2186 };
2187 };
2188
2189 sdhc_2: mmc@8804000 {
2190 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2191 reg = <0 0x08804000 0 0x1000>;
2192
2193 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2194 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2195 interrupt-names = "hc_irq", "pwr_irq";
2196
2197 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2198 <&gcc GCC_SDCC2_APPS_CLK>,
2199 <&rpmhcc RPMH_CXO_CLK>;
2200 clock-names = "iface", "core", "xo";
2201 resets = <&gcc GCC_SDCC2_BCR>;
2202 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2204 interconnect-names = "sdhc-ddr","cpu-sdhc";
2205 iommus = <&apps_smmu 0x4a0 0x0>;
2206 power-domains = <&rpmhpd RPMHPD_CX>;
2207 operating-points-v2 = <&sdhc2_opp_table>;
2208 bus-width = <4>;
2209 dma-coherent;
2210
2211 status = "disabled";
2212
2213 sdhc2_opp_table: opp-table {
2214 compatible = "operating-points-v2";
2215
2216 opp-100000000 {
2217 opp-hz = /bits/ 64 <100000000>;
2218 required-opps = <&rpmhpd_opp_low_svs>;
2219 };
2220
2221 opp-202000000 {
2222 opp-hz = /bits/ 64 <202000000>;
2223 required-opps = <&rpmhpd_opp_svs_l1>;
2224 };
2225 };
2226 };
2227
2228 usb_1_hsphy: phy@88e3000 {
2229 compatible = "qcom,sm8350-usb-hs-phy",
2230 "qcom,usb-snps-hs-7nm-phy";
2231 reg = <0 0x088e3000 0 0x400>;
2232 status = "disabled";
2233 #phy-cells = <0>;
2234
2235 clocks = <&rpmhcc RPMH_CXO_CLK>;
2236 clock-names = "ref";
2237
2238 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2239 };
2240
2241 usb_2_hsphy: phy@88e4000 {
2242 compatible = "qcom,sm8250-usb-hs-phy",
2243 "qcom,usb-snps-hs-7nm-phy";
2244 reg = <0 0x088e4000 0 0x400>;
2245 status = "disabled";
2246 #phy-cells = <0>;
2247
2248 clocks = <&rpmhcc RPMH_CXO_CLK>;
2249 clock-names = "ref";
2250
2251 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2252 };
2253
2254 refgen: regulator@88e7000 {
2255 compatible = "qcom,sm8350-refgen-regulator",
2256 "qcom,sm8250-refgen-regulator";
2257 reg = <0x0 0x088e7000 0x0 0x84>;
2258 };
2259
2260 usb_1_qmpphy: phy@88e8000 {
2261 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2262 reg = <0 0x088e8000 0 0x3000>;
2263
2264 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2265 <&rpmhcc RPMH_CXO_CLK>,
2266 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2267 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2268 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2269
2270 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2271 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2272 reset-names = "phy", "common";
2273
2274 #clock-cells = <1>;
2275 #phy-cells = <1>;
2276
2277 orientation-switch;
2278
2279 status = "disabled";
2280
2281 ports {
2282 #address-cells = <1>;
2283 #size-cells = <0>;
2284
2285 port@0 {
2286 reg = <0>;
2287
2288 usb_1_qmpphy_out: endpoint {
2289 };
2290 };
2291
2292 port@1 {
2293 reg = <1>;
2294
2295 usb_1_qmpphy_usb_ss_in: endpoint {
2296 remote-endpoint = <&usb_1_dwc3_ss>;
2297 };
2298 };
2299
2300 port@2 {
2301 reg = <2>;
2302
2303 usb_1_qmpphy_dp_in: endpoint {
2304 remote-endpoint = <&mdss_dp_out>;
2305 };
2306 };
2307 };
2308 };
2309
2310 usb_2_qmpphy: phy@88eb000 {
2311 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2312 reg = <0 0x088eb000 0 0x2000>;
2313 status = "disabled";
2314
2315 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2316 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2317 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2318 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2319 clock-names = "aux",
2320 "ref",
2321 "com_aux",
2322 "pipe";
2323 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2324 #clock-cells = <0>;
2325 #phy-cells = <0>;
2326
2327 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2328 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
2329 reset-names = "phy",
2330 "phy_phy";
2331 };
2332
2333 dc_noc: interconnect@90c0000 {
2334 compatible = "qcom,sm8350-dc-noc";
2335 reg = <0 0x090c0000 0 0x4200>;
2336 #interconnect-cells = <2>;
2337 qcom,bcm-voters = <&apps_bcm_voter>;
2338 };
2339
2340 gem_noc: interconnect@9100000 {
2341 compatible = "qcom,sm8350-gem-noc";
2342 reg = <0 0x09100000 0 0xb4000>;
2343 #interconnect-cells = <2>;
2344 qcom,bcm-voters = <&apps_bcm_voter>;
2345 };
2346
2347 system-cache-controller@9200000 {
2348 compatible = "qcom,sm8350-llcc";
2349 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2350 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2351 <0 0x09600000 0 0x58000>;
2352 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2353 "llcc3_base", "llcc_broadcast_base";
2354 };
2355
2356 compute_noc: interconnect@a0c0000 {
2357 compatible = "qcom,sm8350-compute-noc";
2358 reg = <0 0x0a0c0000 0 0xa180>;
2359 #interconnect-cells = <2>;
2360 qcom,bcm-voters = <&apps_bcm_voter>;
2361 };
2362
2363 usb_1: usb@a6f8800 {
2364 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2365 reg = <0 0x0a6f8800 0 0x400>;
2366 status = "disabled";
2367 #address-cells = <2>;
2368 #size-cells = <2>;
2369 ranges;
2370
2371 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2372 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2373 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2374 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2375 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2376 clock-names = "cfg_noc",
2377 "core",
2378 "iface",
2379 "sleep",
2380 "mock_utmi";
2381
2382 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2383 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2384 assigned-clock-rates = <19200000>, <200000000>;
2385
2386 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2387 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2388 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2389 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2390 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2391 interrupt-names = "pwr_event",
2392 "hs_phy_irq",
2393 "dp_hs_phy_irq",
2394 "dm_hs_phy_irq",
2395 "ss_phy_irq";
2396
2397 power-domains = <&gcc USB30_PRIM_GDSC>;
2398
2399 resets = <&gcc GCC_USB30_PRIM_BCR>;
2400
2401 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2402 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2403 interconnect-names = "usb-ddr", "apps-usb";
2404
2405 usb_1_dwc3: usb@a600000 {
2406 compatible = "snps,dwc3";
2407 reg = <0 0x0a600000 0 0xcd00>;
2408 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2409 iommus = <&apps_smmu 0x0 0x0>;
2410 snps,dis_u2_susphy_quirk;
2411 snps,dis_enblslpm_quirk;
2412 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
2413 phy-names = "usb2-phy", "usb3-phy";
2414
2415 ports {
2416 #address-cells = <1>;
2417 #size-cells = <0>;
2418
2419 port@0 {
2420 reg = <0>;
2421
2422 usb_1_dwc3_hs: endpoint {
2423 };
2424 };
2425
2426 port@1 {
2427 reg = <1>;
2428
2429 usb_1_dwc3_ss: endpoint {
2430 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
2431 };
2432 };
2433 };
2434 };
2435 };
2436
2437 usb_2: usb@a8f8800 {
2438 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2439 reg = <0 0x0a8f8800 0 0x400>;
2440 status = "disabled";
2441 #address-cells = <2>;
2442 #size-cells = <2>;
2443 ranges;
2444
2445 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2446 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2447 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2448 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2449 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2450 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2451 clock-names = "cfg_noc",
2452 "core",
2453 "iface",
2454 "sleep",
2455 "mock_utmi",
2456 "xo";
2457
2458 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2459 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2460 assigned-clock-rates = <19200000>, <200000000>;
2461
2462 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2463 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2464 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2465 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2466 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2467 interrupt-names = "pwr_event",
2468 "hs_phy_irq",
2469 "dp_hs_phy_irq",
2470 "dm_hs_phy_irq",
2471 "ss_phy_irq";
2472
2473 power-domains = <&gcc USB30_SEC_GDSC>;
2474
2475 resets = <&gcc GCC_USB30_SEC_BCR>;
2476
2477 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2478 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2479 interconnect-names = "usb-ddr", "apps-usb";
2480
2481 usb_2_dwc3: usb@a800000 {
2482 compatible = "snps,dwc3";
2483 reg = <0 0x0a800000 0 0xcd00>;
2484 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2485 iommus = <&apps_smmu 0x20 0x0>;
2486 snps,dis_u2_susphy_quirk;
2487 snps,dis_enblslpm_quirk;
2488 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
2489 phy-names = "usb2-phy", "usb3-phy";
2490 };
2491 };
2492
2493 mdss: display-subsystem@ae00000 {
2494 compatible = "qcom,sm8350-mdss";
2495 reg = <0 0x0ae00000 0 0x1000>;
2496 reg-names = "mdss";
2497
2498 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2499 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
2500 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2501 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2502 interconnect-names = "mdp0-mem",
2503 "mdp1-mem",
2504 "cpu-cfg";
2505
2506 power-domains = <&dispcc MDSS_GDSC>;
2507 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2508
2509 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2510 <&gcc GCC_DISP_HF_AXI_CLK>,
2511 <&gcc GCC_DISP_SF_AXI_CLK>,
2512 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2513 clock-names = "iface", "bus", "nrt_bus", "core";
2514
2515 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2516 interrupt-controller;
2517 #interrupt-cells = <1>;
2518
2519 iommus = <&apps_smmu 0x820 0x402>;
2520
2521 status = "disabled";
2522
2523 #address-cells = <2>;
2524 #size-cells = <2>;
2525 ranges;
2526
2527 mdss_mdp: display-controller@ae01000 {
2528 compatible = "qcom,sm8350-dpu";
2529 reg = <0 0x0ae01000 0 0x8f000>,
2530 <0 0x0aeb0000 0 0x2008>;
2531 reg-names = "mdp", "vbif";
2532
2533 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2534 <&gcc GCC_DISP_SF_AXI_CLK>,
2535 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2536 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2537 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2538 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2539 clock-names = "bus",
2540 "nrt_bus",
2541 "iface",
2542 "lut",
2543 "core",
2544 "vsync";
2545
2546 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2547 assigned-clock-rates = <19200000>;
2548
2549 operating-points-v2 = <&dpu_opp_table>;
2550 power-domains = <&rpmhpd RPMHPD_MMCX>;
2551
2552 interrupt-parent = <&mdss>;
2553 interrupts = <0>;
2554
2555 dpu_opp_table: opp-table {
2556 compatible = "operating-points-v2";
2557
2558 /* TODO: opp-200000000 should work with
2559 * &rpmhpd_opp_low_svs, but one some of
2560 * sm8350_hdk boards reboot using this
2561 * opp.
2562 */
2563 opp-200000000 {
2564 opp-hz = /bits/ 64 <200000000>;
2565 required-opps = <&rpmhpd_opp_svs>;
2566 };
2567
2568 opp-300000000 {
2569 opp-hz = /bits/ 64 <300000000>;
2570 required-opps = <&rpmhpd_opp_svs>;
2571 };
2572
2573 opp-345000000 {
2574 opp-hz = /bits/ 64 <345000000>;
2575 required-opps = <&rpmhpd_opp_svs_l1>;
2576 };
2577
2578 opp-460000000 {
2579 opp-hz = /bits/ 64 <460000000>;
2580 required-opps = <&rpmhpd_opp_nom>;
2581 };
2582 };
2583
2584 ports {
2585 #address-cells = <1>;
2586 #size-cells = <0>;
2587
2588 port@0 {
2589 reg = <0>;
2590 dpu_intf1_out: endpoint {
2591 remote-endpoint = <&mdss_dsi0_in>;
2592 };
2593 };
2594
2595 port@1 {
2596 reg = <1>;
2597 dpu_intf2_out: endpoint {
2598 remote-endpoint = <&mdss_dsi1_in>;
2599 };
2600 };
2601
2602 port@2 {
2603 reg = <2>;
2604 dpu_intf0_out: endpoint {
2605 remote-endpoint = <&mdss_dp_in>;
2606 };
2607 };
2608 };
2609 };
2610
2611 mdss_dp: displayport-controller@ae90000 {
2612 compatible = "qcom,sm8350-dp";
2613 reg = <0 0xae90000 0 0x200>,
2614 <0 0xae90200 0 0x200>,
2615 <0 0xae90400 0 0x600>,
2616 <0 0xae91000 0 0x400>,
2617 <0 0xae91400 0 0x400>;
2618 interrupt-parent = <&mdss>;
2619 interrupts = <12>;
2620 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2621 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2622 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2623 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2624 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2625 clock-names = "core_iface",
2626 "core_aux",
2627 "ctrl_link",
2628 "ctrl_link_iface",
2629 "stream_pixel";
2630
2631 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2632 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2633 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2634 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2635
2636 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2637 phy-names = "dp";
2638
2639 #sound-dai-cells = <0>;
2640
2641 operating-points-v2 = <&dp_opp_table>;
2642 power-domains = <&rpmhpd RPMHPD_MMCX>;
2643
2644 status = "disabled";
2645
2646 ports {
2647 #address-cells = <1>;
2648 #size-cells = <0>;
2649
2650 port@0 {
2651 reg = <0>;
2652 mdss_dp_in: endpoint {
2653 remote-endpoint = <&dpu_intf0_out>;
2654 };
2655 };
2656
2657 port@1 {
2658 reg = <1>;
2659
2660 mdss_dp_out: endpoint {
2661 remote-endpoint = <&usb_1_qmpphy_dp_in>;
2662 };
2663 };
2664 };
2665
2666 dp_opp_table: opp-table {
2667 compatible = "operating-points-v2";
2668
2669 opp-160000000 {
2670 opp-hz = /bits/ 64 <160000000>;
2671 required-opps = <&rpmhpd_opp_low_svs>;
2672 };
2673
2674 opp-270000000 {
2675 opp-hz = /bits/ 64 <270000000>;
2676 required-opps = <&rpmhpd_opp_svs>;
2677 };
2678
2679 opp-540000000 {
2680 opp-hz = /bits/ 64 <540000000>;
2681 required-opps = <&rpmhpd_opp_svs_l1>;
2682 };
2683
2684 opp-810000000 {
2685 opp-hz = /bits/ 64 <810000000>;
2686 required-opps = <&rpmhpd_opp_nom>;
2687 };
2688 };
2689 };
2690
2691 mdss_dsi0: dsi@ae94000 {
2692 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2693 reg = <0 0x0ae94000 0 0x400>;
2694 reg-names = "dsi_ctrl";
2695
2696 interrupt-parent = <&mdss>;
2697 interrupts = <4>;
2698
2699 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2700 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2701 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2702 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2703 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2704 <&gcc GCC_DISP_HF_AXI_CLK>;
2705 clock-names = "byte",
2706 "byte_intf",
2707 "pixel",
2708 "core",
2709 "iface",
2710 "bus";
2711
2712 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2713 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2714 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2715 <&mdss_dsi0_phy 1>;
2716
2717 operating-points-v2 = <&dsi0_opp_table>;
2718 power-domains = <&rpmhpd RPMHPD_MMCX>;
2719 refgen-supply = <&refgen>;
2720
2721 phys = <&mdss_dsi0_phy>;
2722
2723 #address-cells = <1>;
2724 #size-cells = <0>;
2725
2726 status = "disabled";
2727
2728 dsi0_opp_table: opp-table {
2729 compatible = "operating-points-v2";
2730
2731 /* TODO: opp-187500000 should work with
2732 * &rpmhpd_opp_low_svs, but one some of
2733 * sm8350_hdk boards reboot using this
2734 * opp.
2735 */
2736 opp-187500000 {
2737 opp-hz = /bits/ 64 <187500000>;
2738 required-opps = <&rpmhpd_opp_svs>;
2739 };
2740
2741 opp-300000000 {
2742 opp-hz = /bits/ 64 <300000000>;
2743 required-opps = <&rpmhpd_opp_svs>;
2744 };
2745
2746 opp-358000000 {
2747 opp-hz = /bits/ 64 <358000000>;
2748 required-opps = <&rpmhpd_opp_svs_l1>;
2749 };
2750 };
2751
2752 ports {
2753 #address-cells = <1>;
2754 #size-cells = <0>;
2755
2756 port@0 {
2757 reg = <0>;
2758 mdss_dsi0_in: endpoint {
2759 remote-endpoint = <&dpu_intf1_out>;
2760 };
2761 };
2762
2763 port@1 {
2764 reg = <1>;
2765 mdss_dsi0_out: endpoint {
2766 };
2767 };
2768 };
2769 };
2770
2771 mdss_dsi0_phy: phy@ae94400 {
2772 compatible = "qcom,sm8350-dsi-phy-5nm";
2773 reg = <0 0x0ae94400 0 0x200>,
2774 <0 0x0ae94600 0 0x280>,
2775 <0 0x0ae94900 0 0x27c>;
2776 reg-names = "dsi_phy",
2777 "dsi_phy_lane",
2778 "dsi_pll";
2779
2780 #clock-cells = <1>;
2781 #phy-cells = <0>;
2782
2783 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2784 <&rpmhcc RPMH_CXO_CLK>;
2785 clock-names = "iface", "ref";
2786
2787 status = "disabled";
2788 };
2789
2790 mdss_dsi1: dsi@ae96000 {
2791 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2792 reg = <0 0x0ae96000 0 0x400>;
2793 reg-names = "dsi_ctrl";
2794
2795 interrupt-parent = <&mdss>;
2796 interrupts = <5>;
2797
2798 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2799 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2800 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2801 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2802 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2803 <&gcc GCC_DISP_HF_AXI_CLK>;
2804 clock-names = "byte",
2805 "byte_intf",
2806 "pixel",
2807 "core",
2808 "iface",
2809 "bus";
2810
2811 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2812 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2813 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2814 <&mdss_dsi1_phy 1>;
2815
2816 operating-points-v2 = <&dsi1_opp_table>;
2817 power-domains = <&rpmhpd RPMHPD_MMCX>;
2818 refgen-supply = <&refgen>;
2819
2820 phys = <&mdss_dsi1_phy>;
2821
2822 #address-cells = <1>;
2823 #size-cells = <0>;
2824
2825 status = "disabled";
2826
2827 dsi1_opp_table: opp-table {
2828 compatible = "operating-points-v2";
2829
2830 /* TODO: opp-187500000 should work with
2831 * &rpmhpd_opp_low_svs, but one some of
2832 * sm8350_hdk boards reboot using this
2833 * opp.
2834 */
2835 opp-187500000 {
2836 opp-hz = /bits/ 64 <187500000>;
2837 required-opps = <&rpmhpd_opp_svs>;
2838 };
2839
2840 opp-300000000 {
2841 opp-hz = /bits/ 64 <300000000>;
2842 required-opps = <&rpmhpd_opp_svs>;
2843 };
2844
2845 opp-358000000 {
2846 opp-hz = /bits/ 64 <358000000>;
2847 required-opps = <&rpmhpd_opp_svs_l1>;
2848 };
2849 };
2850
2851 ports {
2852 #address-cells = <1>;
2853 #size-cells = <0>;
2854
2855 port@0 {
2856 reg = <0>;
2857 mdss_dsi1_in: endpoint {
2858 remote-endpoint = <&dpu_intf2_out>;
2859 };
2860 };
2861
2862 port@1 {
2863 reg = <1>;
2864 mdss_dsi1_out: endpoint {
2865 };
2866 };
2867 };
2868 };
2869
2870 mdss_dsi1_phy: phy@ae96400 {
2871 compatible = "qcom,sm8350-dsi-phy-5nm";
2872 reg = <0 0x0ae96400 0 0x200>,
2873 <0 0x0ae96600 0 0x280>,
2874 <0 0x0ae96900 0 0x27c>;
2875 reg-names = "dsi_phy",
2876 "dsi_phy_lane",
2877 "dsi_pll";
2878
2879 #clock-cells = <1>;
2880 #phy-cells = <0>;
2881
2882 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2883 <&rpmhcc RPMH_CXO_CLK>;
2884 clock-names = "iface", "ref";
2885
2886 status = "disabled";
2887 };
2888 };
2889
2890 dispcc: clock-controller@af00000 {
2891 compatible = "qcom,sm8350-dispcc";
2892 reg = <0 0x0af00000 0 0x10000>;
2893 clocks = <&rpmhcc RPMH_CXO_CLK>,
2894 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2895 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2896 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2897 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2898 clock-names = "bi_tcxo",
2899 "dsi0_phy_pll_out_byteclk",
2900 "dsi0_phy_pll_out_dsiclk",
2901 "dsi1_phy_pll_out_byteclk",
2902 "dsi1_phy_pll_out_dsiclk",
2903 "dp_phy_pll_link_clk",
2904 "dp_phy_pll_vco_div_clk";
2905 #clock-cells = <1>;
2906 #reset-cells = <1>;
2907 #power-domain-cells = <1>;
2908
2909 power-domains = <&rpmhpd RPMHPD_MMCX>;
2910 };
2911
2912 pdc: interrupt-controller@b220000 {
2913 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2914 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2915 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2916 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
2917 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
2918 <156 716 12>;
2919 #interrupt-cells = <2>;
2920 interrupt-parent = <&intc>;
2921 interrupt-controller;
2922 };
2923
2924 tsens0: thermal-sensor@c263000 {
2925 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2926 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2927 <0 0x0c222000 0 0x8>; /* SROT */
2928 #qcom,sensors = <15>;
2929 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2930 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2931 interrupt-names = "uplow", "critical";
2932 #thermal-sensor-cells = <1>;
2933 };
2934
2935 tsens1: thermal-sensor@c265000 {
2936 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2937 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2938 <0 0x0c223000 0 0x8>; /* SROT */
2939 #qcom,sensors = <14>;
2940 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2941 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2942 interrupt-names = "uplow", "critical";
2943 #thermal-sensor-cells = <1>;
2944 };
2945
2946 aoss_qmp: power-management@c300000 {
2947 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2948 reg = <0 0x0c300000 0 0x400>;
2949 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2950 IRQ_TYPE_EDGE_RISING>;
2951 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2952
2953 #clock-cells = <0>;
2954 };
2955
2956 sram@c3f0000 {
2957 compatible = "qcom,rpmh-stats";
2958 reg = <0 0x0c3f0000 0 0x400>;
2959 };
2960
2961 spmi_bus: spmi@c440000 {
2962 compatible = "qcom,spmi-pmic-arb";
2963 reg = <0x0 0x0c440000 0x0 0x1100>,
2964 <0x0 0x0c600000 0x0 0x2000000>,
2965 <0x0 0x0e600000 0x0 0x100000>,
2966 <0x0 0x0e700000 0x0 0xa0000>,
2967 <0x0 0x0c40a000 0x0 0x26000>;
2968 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2969 interrupt-names = "periph_irq";
2970 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2971 qcom,ee = <0>;
2972 qcom,channel = <0>;
2973 #address-cells = <2>;
2974 #size-cells = <0>;
2975 interrupt-controller;
2976 #interrupt-cells = <4>;
2977 };
2978
2979 tlmm: pinctrl@f100000 {
2980 compatible = "qcom,sm8350-tlmm";
2981 reg = <0 0x0f100000 0 0x300000>;
2982 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2983 gpio-controller;
2984 #gpio-cells = <2>;
2985 interrupt-controller;
2986 #interrupt-cells = <2>;
2987 gpio-ranges = <&tlmm 0 0 204>;
2988 wakeup-parent = <&pdc>;
2989
2990 sdc2_default_state: sdc2-default-state {
2991 clk-pins {
2992 pins = "sdc2_clk";
2993 drive-strength = <16>;
2994 bias-disable;
2995 };
2996
2997 cmd-pins {
2998 pins = "sdc2_cmd";
2999 drive-strength = <16>;
3000 bias-pull-up;
3001 };
3002
3003 data-pins {
3004 pins = "sdc2_data";
3005 drive-strength = <16>;
3006 bias-pull-up;
3007 };
3008 };
3009
3010 sdc2_sleep_state: sdc2-sleep-state {
3011 clk-pins {
3012 pins = "sdc2_clk";
3013 drive-strength = <2>;
3014 bias-disable;
3015 };
3016
3017 cmd-pins {
3018 pins = "sdc2_cmd";
3019 drive-strength = <2>;
3020 bias-pull-up;
3021 };
3022
3023 data-pins {
3024 pins = "sdc2_data";
3025 drive-strength = <2>;
3026 bias-pull-up;
3027 };
3028 };
3029
3030 qup_uart3_default_state: qup-uart3-default-state {
3031 rx-pins {
3032 pins = "gpio18";
3033 function = "qup3";
3034 };
3035 tx-pins {
3036 pins = "gpio19";
3037 function = "qup3";
3038 };
3039 };
3040
3041 qup_uart6_default: qup-uart6-default-state {
3042 pins = "gpio30", "gpio31";
3043 function = "qup6";
3044 drive-strength = <2>;
3045 bias-disable;
3046 };
3047
3048 qup_uart18_default: qup-uart18-default-state {
3049 pins = "gpio68", "gpio69";
3050 function = "qup18";
3051 drive-strength = <2>;
3052 bias-disable;
3053 };
3054
3055 qup_i2c0_default: qup-i2c0-default-state {
3056 pins = "gpio4", "gpio5";
3057 function = "qup0";
3058 drive-strength = <2>;
3059 bias-pull-up;
3060 };
3061
3062 qup_i2c1_default: qup-i2c1-default-state {
3063 pins = "gpio8", "gpio9";
3064 function = "qup1";
3065 drive-strength = <2>;
3066 bias-pull-up;
3067 };
3068
3069 qup_i2c2_default: qup-i2c2-default-state {
3070 pins = "gpio12", "gpio13";
3071 function = "qup2";
3072 drive-strength = <2>;
3073 bias-pull-up;
3074 };
3075
3076 qup_i2c4_default: qup-i2c4-default-state {
3077 pins = "gpio20", "gpio21";
3078 function = "qup4";
3079 drive-strength = <2>;
3080 bias-pull-up;
3081 };
3082
3083 qup_i2c5_default: qup-i2c5-default-state {
3084 pins = "gpio24", "gpio25";
3085 function = "qup5";
3086 drive-strength = <2>;
3087 bias-pull-up;
3088 };
3089
3090 qup_i2c6_default: qup-i2c6-default-state {
3091 pins = "gpio28", "gpio29";
3092 function = "qup6";
3093 drive-strength = <2>;
3094 bias-pull-up;
3095 };
3096
3097 qup_i2c7_default: qup-i2c7-default-state {
3098 pins = "gpio32", "gpio33";
3099 function = "qup7";
3100 drive-strength = <2>;
3101 bias-disable;
3102 };
3103
3104 qup_i2c8_default: qup-i2c8-default-state {
3105 pins = "gpio36", "gpio37";
3106 function = "qup8";
3107 drive-strength = <2>;
3108 bias-pull-up;
3109 };
3110
3111 qup_i2c9_default: qup-i2c9-default-state {
3112 pins = "gpio40", "gpio41";
3113 function = "qup9";
3114 drive-strength = <2>;
3115 bias-pull-up;
3116 };
3117
3118 qup_i2c10_default: qup-i2c10-default-state {
3119 pins = "gpio44", "gpio45";
3120 function = "qup10";
3121 drive-strength = <2>;
3122 bias-pull-up;
3123 };
3124
3125 qup_i2c11_default: qup-i2c11-default-state {
3126 pins = "gpio48", "gpio49";
3127 function = "qup11";
3128 drive-strength = <2>;
3129 bias-pull-up;
3130 };
3131
3132 qup_i2c12_default: qup-i2c12-default-state {
3133 pins = "gpio52", "gpio53";
3134 function = "qup12";
3135 drive-strength = <2>;
3136 bias-pull-up;
3137 };
3138
3139 qup_i2c13_default: qup-i2c13-default-state {
3140 pins = "gpio0", "gpio1";
3141 function = "qup13";
3142 drive-strength = <2>;
3143 bias-pull-up;
3144 };
3145
3146 qup_i2c14_default: qup-i2c14-default-state {
3147 pins = "gpio56", "gpio57";
3148 function = "qup14";
3149 drive-strength = <2>;
3150 bias-disable;
3151 };
3152
3153 qup_i2c15_default: qup-i2c15-default-state {
3154 pins = "gpio60", "gpio61";
3155 function = "qup15";
3156 drive-strength = <2>;
3157 bias-disable;
3158 };
3159
3160 qup_i2c16_default: qup-i2c16-default-state {
3161 pins = "gpio64", "gpio65";
3162 function = "qup16";
3163 drive-strength = <2>;
3164 bias-disable;
3165 };
3166
3167 qup_i2c17_default: qup-i2c17-default-state {
3168 pins = "gpio72", "gpio73";
3169 function = "qup17";
3170 drive-strength = <2>;
3171 bias-disable;
3172 };
3173
3174 qup_i2c19_default: qup-i2c19-default-state {
3175 pins = "gpio76", "gpio77";
3176 function = "qup19";
3177 drive-strength = <2>;
3178 bias-disable;
3179 };
3180 };
3181
3182 apps_smmu: iommu@15000000 {
3183 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3184 reg = <0 0x15000000 0 0x100000>;
3185 #iommu-cells = <2>;
3186 #global-interrupts = <2>;
3187 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3188 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3189 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3190 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3192 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3193 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3194 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3195 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3196 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3197 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3198 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3199 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3200 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3201 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3202 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3203 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3204 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3205 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3206 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3207 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3208 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3209 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3210 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3211 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3212 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3213 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3214 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3215 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3216 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3217 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3218 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3219 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3220 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3221 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3222 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3223 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3224 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3225 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3226 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3227 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3228 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3229 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3230 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3231 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3232 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3233 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3234 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3235 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3236 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3237 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3238 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3239 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3251 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3252 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3253 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3254 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3255 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3256 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3257 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3258 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3259 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3260 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3261 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3262 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3263 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3264 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3265 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3266 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3267 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3268 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3269 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3270 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3271 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3272 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3273 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3274 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3275 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3276 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3277 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3278 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3279 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3280 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3281 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3282 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3283 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3284 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3285 };
3286
3287 adsp: remoteproc@17300000 {
3288 compatible = "qcom,sm8350-adsp-pas";
3289 reg = <0 0x17300000 0 0x100>;
3290
3291 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3292 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3293 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3294 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3295 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3296 interrupt-names = "wdog", "fatal", "ready",
3297 "handover", "stop-ack";
3298
3299 clocks = <&rpmhcc RPMH_CXO_CLK>;
3300 clock-names = "xo";
3301
3302 power-domains = <&rpmhpd RPMHPD_LCX>,
3303 <&rpmhpd RPMHPD_LMX>;
3304 power-domain-names = "lcx", "lmx";
3305
3306 memory-region = <&pil_adsp_mem>;
3307
3308 qcom,qmp = <&aoss_qmp>;
3309
3310 qcom,smem-states = <&smp2p_adsp_out 0>;
3311 qcom,smem-state-names = "stop";
3312
3313 status = "disabled";
3314
3315 glink-edge {
3316 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3317 IPCC_MPROC_SIGNAL_GLINK_QMP
3318 IRQ_TYPE_EDGE_RISING>;
3319 mboxes = <&ipcc IPCC_CLIENT_LPASS
3320 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3321
3322 label = "lpass";
3323 qcom,remote-pid = <2>;
3324
3325 apr {
3326 compatible = "qcom,apr-v2";
3327 qcom,glink-channels = "apr_audio_svc";
3328 qcom,domain = <APR_DOMAIN_ADSP>;
3329 #address-cells = <1>;
3330 #size-cells = <0>;
3331
3332 service@3 {
3333 reg = <APR_SVC_ADSP_CORE>;
3334 compatible = "qcom,q6core";
3335 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3336 };
3337
3338 q6afe: service@4 {
3339 compatible = "qcom,q6afe";
3340 reg = <APR_SVC_AFE>;
3341 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3342
3343 q6afedai: dais {
3344 compatible = "qcom,q6afe-dais";
3345 #address-cells = <1>;
3346 #size-cells = <0>;
3347 #sound-dai-cells = <1>;
3348 };
3349
3350 q6afecc: clock-controller {
3351 compatible = "qcom,q6afe-clocks";
3352 #clock-cells = <2>;
3353 };
3354 };
3355
3356 q6asm: service@7 {
3357 compatible = "qcom,q6asm";
3358 reg = <APR_SVC_ASM>;
3359 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3360
3361 q6asmdai: dais {
3362 compatible = "qcom,q6asm-dais";
3363 #address-cells = <1>;
3364 #size-cells = <0>;
3365 #sound-dai-cells = <1>;
3366 iommus = <&apps_smmu 0x1801 0x0>;
3367
3368 dai@0 {
3369 reg = <0>;
3370 };
3371
3372 dai@1 {
3373 reg = <1>;
3374 };
3375
3376 dai@2 {
3377 reg = <2>;
3378 };
3379 };
3380 };
3381
3382 q6adm: service@8 {
3383 compatible = "qcom,q6adm";
3384 reg = <APR_SVC_ADM>;
3385 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3386
3387 q6routing: routing {
3388 compatible = "qcom,q6adm-routing";
3389 #sound-dai-cells = <0>;
3390 };
3391 };
3392 };
3393
3394 fastrpc {
3395 compatible = "qcom,fastrpc";
3396 qcom,glink-channels = "fastrpcglink-apps-dsp";
3397 label = "adsp";
3398 qcom,non-secure-domain;
3399 #address-cells = <1>;
3400 #size-cells = <0>;
3401
3402 compute-cb@3 {
3403 compatible = "qcom,fastrpc-compute-cb";
3404 reg = <3>;
3405 iommus = <&apps_smmu 0x1803 0x0>;
3406 };
3407
3408 compute-cb@4 {
3409 compatible = "qcom,fastrpc-compute-cb";
3410 reg = <4>;
3411 iommus = <&apps_smmu 0x1804 0x0>;
3412 };
3413
3414 compute-cb@5 {
3415 compatible = "qcom,fastrpc-compute-cb";
3416 reg = <5>;
3417 iommus = <&apps_smmu 0x1805 0x0>;
3418 };
3419 };
3420 };
3421 };
3422
3423 intc: interrupt-controller@17a00000 {
3424 compatible = "arm,gic-v3";
3425 #interrupt-cells = <3>;
3426 interrupt-controller;
3427 #redistributor-regions = <1>;
3428 redistributor-stride = <0 0x20000>;
3429 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3430 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3431 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3432 };
3433
3434 timer@17c20000 {
3435 compatible = "arm,armv7-timer-mem";
3436 #address-cells = <1>;
3437 #size-cells = <1>;
3438 ranges = <0 0 0 0x20000000>;
3439 reg = <0x0 0x17c20000 0x0 0x1000>;
3440 clock-frequency = <19200000>;
3441
3442 frame@17c21000 {
3443 frame-number = <0>;
3444 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3445 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3446 reg = <0x17c21000 0x1000>,
3447 <0x17c22000 0x1000>;
3448 };
3449
3450 frame@17c23000 {
3451 frame-number = <1>;
3452 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3453 reg = <0x17c23000 0x1000>;
3454 status = "disabled";
3455 };
3456
3457 frame@17c25000 {
3458 frame-number = <2>;
3459 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3460 reg = <0x17c25000 0x1000>;
3461 status = "disabled";
3462 };
3463
3464 frame@17c27000 {
3465 frame-number = <3>;
3466 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3467 reg = <0x17c27000 0x1000>;
3468 status = "disabled";
3469 };
3470
3471 frame@17c29000 {
3472 frame-number = <4>;
3473 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3474 reg = <0x17c29000 0x1000>;
3475 status = "disabled";
3476 };
3477
3478 frame@17c2b000 {
3479 frame-number = <5>;
3480 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3481 reg = <0x17c2b000 0x1000>;
3482 status = "disabled";
3483 };
3484
3485 frame@17c2d000 {
3486 frame-number = <6>;
3487 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3488 reg = <0x17c2d000 0x1000>;
3489 status = "disabled";
3490 };
3491 };
3492
3493 apps_rsc: rsc@18200000 {
3494 label = "apps_rsc";
3495 compatible = "qcom,rpmh-rsc";
3496 reg = <0x0 0x18200000 0x0 0x10000>,
3497 <0x0 0x18210000 0x0 0x10000>,
3498 <0x0 0x18220000 0x0 0x10000>;
3499 reg-names = "drv-0", "drv-1", "drv-2";
3500 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3501 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3502 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3503 qcom,tcs-offset = <0xd00>;
3504 qcom,drv-id = <2>;
3505 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3506 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3507 power-domains = <&CLUSTER_PD>;
3508
3509 rpmhcc: clock-controller {
3510 compatible = "qcom,sm8350-rpmh-clk";
3511 #clock-cells = <1>;
3512 clock-names = "xo";
3513 clocks = <&xo_board>;
3514 };
3515
3516 rpmhpd: power-controller {
3517 compatible = "qcom,sm8350-rpmhpd";
3518 #power-domain-cells = <1>;
3519 operating-points-v2 = <&rpmhpd_opp_table>;
3520
3521 rpmhpd_opp_table: opp-table {
3522 compatible = "operating-points-v2";
3523
3524 rpmhpd_opp_ret: opp1 {
3525 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3526 };
3527
3528 rpmhpd_opp_min_svs: opp2 {
3529 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3530 };
3531
3532 rpmhpd_opp_low_svs: opp3 {
3533 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3534 };
3535
3536 rpmhpd_opp_svs: opp4 {
3537 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3538 };
3539
3540 rpmhpd_opp_svs_l1: opp5 {
3541 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3542 };
3543
3544 rpmhpd_opp_nom: opp6 {
3545 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3546 };
3547
3548 rpmhpd_opp_nom_l1: opp7 {
3549 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3550 };
3551
3552 rpmhpd_opp_nom_l2: opp8 {
3553 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3554 };
3555
3556 rpmhpd_opp_turbo: opp9 {
3557 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3558 };
3559
3560 rpmhpd_opp_turbo_l1: opp10 {
3561 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3562 };
3563 };
3564 };
3565
3566 apps_bcm_voter: bcm-voter {
3567 compatible = "qcom,bcm-voter";
3568 };
3569 };
3570
3571 cpufreq_hw: cpufreq@18591000 {
3572 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3573 reg = <0 0x18591000 0 0x1000>,
3574 <0 0x18592000 0 0x1000>,
3575 <0 0x18593000 0 0x1000>;
3576 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3577
3578 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3581 interrupt-names = "dcvsh-irq-0",
3582 "dcvsh-irq-1",
3583 "dcvsh-irq-2";
3584
3585 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3586 clock-names = "xo", "alternate";
3587
3588 #freq-domain-cells = <1>;
3589 #clock-cells = <1>;
3590 };
3591
3592 cdsp: remoteproc@98900000 {
3593 compatible = "qcom,sm8350-cdsp-pas";
3594 reg = <0 0x98900000 0 0x1400000>;
3595
3596 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3597 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3598 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3599 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3600 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3601 interrupt-names = "wdog", "fatal", "ready",
3602 "handover", "stop-ack";
3603
3604 clocks = <&rpmhcc RPMH_CXO_CLK>;
3605 clock-names = "xo";
3606
3607 power-domains = <&rpmhpd RPMHPD_CX>,
3608 <&rpmhpd RPMHPD_MXC>;
3609 power-domain-names = "cx", "mxc";
3610
3611 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3612
3613 memory-region = <&pil_cdsp_mem>;
3614
3615 qcom,qmp = <&aoss_qmp>;
3616
3617 qcom,smem-states = <&smp2p_cdsp_out 0>;
3618 qcom,smem-state-names = "stop";
3619
3620 status = "disabled";
3621
3622 glink-edge {
3623 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3624 IPCC_MPROC_SIGNAL_GLINK_QMP
3625 IRQ_TYPE_EDGE_RISING>;
3626 mboxes = <&ipcc IPCC_CLIENT_CDSP
3627 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3628
3629 label = "cdsp";
3630 qcom,remote-pid = <5>;
3631
3632 fastrpc {
3633 compatible = "qcom,fastrpc";
3634 qcom,glink-channels = "fastrpcglink-apps-dsp";
3635 label = "cdsp";
3636 qcom,non-secure-domain;
3637 #address-cells = <1>;
3638 #size-cells = <0>;
3639
3640 compute-cb@1 {
3641 compatible = "qcom,fastrpc-compute-cb";
3642 reg = <1>;
3643 iommus = <&apps_smmu 0x2161 0x0400>,
3644 <&apps_smmu 0x1181 0x0420>;
3645 };
3646
3647 compute-cb@2 {
3648 compatible = "qcom,fastrpc-compute-cb";
3649 reg = <2>;
3650 iommus = <&apps_smmu 0x2162 0x0400>,
3651 <&apps_smmu 0x1182 0x0420>;
3652 };
3653
3654 compute-cb@3 {
3655 compatible = "qcom,fastrpc-compute-cb";
3656 reg = <3>;
3657 iommus = <&apps_smmu 0x2163 0x0400>,
3658 <&apps_smmu 0x1183 0x0420>;
3659 };
3660
3661 compute-cb@4 {
3662 compatible = "qcom,fastrpc-compute-cb";
3663 reg = <4>;
3664 iommus = <&apps_smmu 0x2164 0x0400>,
3665 <&apps_smmu 0x1184 0x0420>;
3666 };
3667
3668 compute-cb@5 {
3669 compatible = "qcom,fastrpc-compute-cb";
3670 reg = <5>;
3671 iommus = <&apps_smmu 0x2165 0x0400>,
3672 <&apps_smmu 0x1185 0x0420>;
3673 };
3674
3675 compute-cb@6 {
3676 compatible = "qcom,fastrpc-compute-cb";
3677 reg = <6>;
3678 iommus = <&apps_smmu 0x2166 0x0400>,
3679 <&apps_smmu 0x1186 0x0420>;
3680 };
3681
3682 compute-cb@7 {
3683 compatible = "qcom,fastrpc-compute-cb";
3684 reg = <7>;
3685 iommus = <&apps_smmu 0x2167 0x0400>,
3686 <&apps_smmu 0x1187 0x0420>;
3687 };
3688
3689 compute-cb@8 {
3690 compatible = "qcom,fastrpc-compute-cb";
3691 reg = <8>;
3692 iommus = <&apps_smmu 0x2168 0x0400>,
3693 <&apps_smmu 0x1188 0x0420>;
3694 };
3695
3696 /* note: secure cb9 in downstream */
3697 };
3698 };
3699 };
3700 };
3701
3702 thermal_zones: thermal-zones {
3703 cpu0-thermal {
3704 polling-delay-passive = <250>;
3705
3706 thermal-sensors = <&tsens0 1>;
3707
3708 trips {
3709 cpu0_alert0: trip-point0 {
3710 temperature = <90000>;
3711 hysteresis = <2000>;
3712 type = "passive";
3713 };
3714
3715 cpu0_alert1: trip-point1 {
3716 temperature = <95000>;
3717 hysteresis = <2000>;
3718 type = "passive";
3719 };
3720
3721 cpu0_crit: cpu-crit {
3722 temperature = <110000>;
3723 hysteresis = <1000>;
3724 type = "critical";
3725 };
3726 };
3727
3728 cooling-maps {
3729 map0 {
3730 trip = <&cpu0_alert0>;
3731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3732 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3733 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3734 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3735 };
3736 map1 {
3737 trip = <&cpu0_alert1>;
3738 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3739 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3740 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3741 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3742 };
3743 };
3744 };
3745
3746 cpu1-thermal {
3747 polling-delay-passive = <250>;
3748
3749 thermal-sensors = <&tsens0 2>;
3750
3751 trips {
3752 cpu1_alert0: trip-point0 {
3753 temperature = <90000>;
3754 hysteresis = <2000>;
3755 type = "passive";
3756 };
3757
3758 cpu1_alert1: trip-point1 {
3759 temperature = <95000>;
3760 hysteresis = <2000>;
3761 type = "passive";
3762 };
3763
3764 cpu1_crit: cpu-crit {
3765 temperature = <110000>;
3766 hysteresis = <1000>;
3767 type = "critical";
3768 };
3769 };
3770
3771 cooling-maps {
3772 map0 {
3773 trip = <&cpu1_alert0>;
3774 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3775 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3776 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3778 };
3779 map1 {
3780 trip = <&cpu1_alert1>;
3781 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3782 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3783 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3784 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3785 };
3786 };
3787 };
3788
3789 cpu2-thermal {
3790 polling-delay-passive = <250>;
3791
3792 thermal-sensors = <&tsens0 3>;
3793
3794 trips {
3795 cpu2_alert0: trip-point0 {
3796 temperature = <90000>;
3797 hysteresis = <2000>;
3798 type = "passive";
3799 };
3800
3801 cpu2_alert1: trip-point1 {
3802 temperature = <95000>;
3803 hysteresis = <2000>;
3804 type = "passive";
3805 };
3806
3807 cpu2_crit: cpu-crit {
3808 temperature = <110000>;
3809 hysteresis = <1000>;
3810 type = "critical";
3811 };
3812 };
3813
3814 cooling-maps {
3815 map0 {
3816 trip = <&cpu2_alert0>;
3817 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3818 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3819 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3820 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3821 };
3822 map1 {
3823 trip = <&cpu2_alert1>;
3824 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3825 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3826 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3827 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 };
3829 };
3830 };
3831
3832 cpu3-thermal {
3833 polling-delay-passive = <250>;
3834
3835 thermal-sensors = <&tsens0 4>;
3836
3837 trips {
3838 cpu3_alert0: trip-point0 {
3839 temperature = <90000>;
3840 hysteresis = <2000>;
3841 type = "passive";
3842 };
3843
3844 cpu3_alert1: trip-point1 {
3845 temperature = <95000>;
3846 hysteresis = <2000>;
3847 type = "passive";
3848 };
3849
3850 cpu3_crit: cpu-crit {
3851 temperature = <110000>;
3852 hysteresis = <1000>;
3853 type = "critical";
3854 };
3855 };
3856
3857 cooling-maps {
3858 map0 {
3859 trip = <&cpu3_alert0>;
3860 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3861 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3862 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3863 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3864 };
3865 map1 {
3866 trip = <&cpu3_alert1>;
3867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3868 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3869 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3870 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3871 };
3872 };
3873 };
3874
3875 cpu4-top-thermal {
3876 polling-delay-passive = <250>;
3877
3878 thermal-sensors = <&tsens0 7>;
3879
3880 trips {
3881 cpu4_top_alert0: trip-point0 {
3882 temperature = <90000>;
3883 hysteresis = <2000>;
3884 type = "passive";
3885 };
3886
3887 cpu4_top_alert1: trip-point1 {
3888 temperature = <95000>;
3889 hysteresis = <2000>;
3890 type = "passive";
3891 };
3892
3893 cpu4_top_crit: cpu-crit {
3894 temperature = <110000>;
3895 hysteresis = <1000>;
3896 type = "critical";
3897 };
3898 };
3899
3900 cooling-maps {
3901 map0 {
3902 trip = <&cpu4_top_alert0>;
3903 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3904 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3905 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3906 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3907 };
3908 map1 {
3909 trip = <&cpu4_top_alert1>;
3910 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3911 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3912 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3913 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3914 };
3915 };
3916 };
3917
3918 cpu5-top-thermal {
3919 polling-delay-passive = <250>;
3920
3921 thermal-sensors = <&tsens0 8>;
3922
3923 trips {
3924 cpu5_top_alert0: trip-point0 {
3925 temperature = <90000>;
3926 hysteresis = <2000>;
3927 type = "passive";
3928 };
3929
3930 cpu5_top_alert1: trip-point1 {
3931 temperature = <95000>;
3932 hysteresis = <2000>;
3933 type = "passive";
3934 };
3935
3936 cpu5_top_crit: cpu-crit {
3937 temperature = <110000>;
3938 hysteresis = <1000>;
3939 type = "critical";
3940 };
3941 };
3942
3943 cooling-maps {
3944 map0 {
3945 trip = <&cpu5_top_alert0>;
3946 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3947 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3948 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3949 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3950 };
3951 map1 {
3952 trip = <&cpu5_top_alert1>;
3953 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3954 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3955 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3956 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3957 };
3958 };
3959 };
3960
3961 cpu6-top-thermal {
3962 polling-delay-passive = <250>;
3963
3964 thermal-sensors = <&tsens0 9>;
3965
3966 trips {
3967 cpu6_top_alert0: trip-point0 {
3968 temperature = <90000>;
3969 hysteresis = <2000>;
3970 type = "passive";
3971 };
3972
3973 cpu6_top_alert1: trip-point1 {
3974 temperature = <95000>;
3975 hysteresis = <2000>;
3976 type = "passive";
3977 };
3978
3979 cpu6_top_crit: cpu-crit {
3980 temperature = <110000>;
3981 hysteresis = <1000>;
3982 type = "critical";
3983 };
3984 };
3985
3986 cooling-maps {
3987 map0 {
3988 trip = <&cpu6_top_alert0>;
3989 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3990 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3991 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3992 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3993 };
3994 map1 {
3995 trip = <&cpu6_top_alert1>;
3996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3997 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4000 };
4001 };
4002 };
4003
4004 cpu7-top-thermal {
4005 polling-delay-passive = <250>;
4006
4007 thermal-sensors = <&tsens0 10>;
4008
4009 trips {
4010 cpu7_top_alert0: trip-point0 {
4011 temperature = <90000>;
4012 hysteresis = <2000>;
4013 type = "passive";
4014 };
4015
4016 cpu7_top_alert1: trip-point1 {
4017 temperature = <95000>;
4018 hysteresis = <2000>;
4019 type = "passive";
4020 };
4021
4022 cpu7_top_crit: cpu-crit {
4023 temperature = <110000>;
4024 hysteresis = <1000>;
4025 type = "critical";
4026 };
4027 };
4028
4029 cooling-maps {
4030 map0 {
4031 trip = <&cpu7_top_alert0>;
4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4033 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4034 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4036 };
4037 map1 {
4038 trip = <&cpu7_top_alert1>;
4039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4041 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4042 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4043 };
4044 };
4045 };
4046
4047 cpu4-bottom-thermal {
4048 polling-delay-passive = <250>;
4049
4050 thermal-sensors = <&tsens0 11>;
4051
4052 trips {
4053 cpu4_bottom_alert0: trip-point0 {
4054 temperature = <90000>;
4055 hysteresis = <2000>;
4056 type = "passive";
4057 };
4058
4059 cpu4_bottom_alert1: trip-point1 {
4060 temperature = <95000>;
4061 hysteresis = <2000>;
4062 type = "passive";
4063 };
4064
4065 cpu4_bottom_crit: cpu-crit {
4066 temperature = <110000>;
4067 hysteresis = <1000>;
4068 type = "critical";
4069 };
4070 };
4071
4072 cooling-maps {
4073 map0 {
4074 trip = <&cpu4_bottom_alert0>;
4075 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4079 };
4080 map1 {
4081 trip = <&cpu4_bottom_alert1>;
4082 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4083 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4084 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4085 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4086 };
4087 };
4088 };
4089
4090 cpu5-bottom-thermal {
4091 polling-delay-passive = <250>;
4092
4093 thermal-sensors = <&tsens0 12>;
4094
4095 trips {
4096 cpu5_bottom_alert0: trip-point0 {
4097 temperature = <90000>;
4098 hysteresis = <2000>;
4099 type = "passive";
4100 };
4101
4102 cpu5_bottom_alert1: trip-point1 {
4103 temperature = <95000>;
4104 hysteresis = <2000>;
4105 type = "passive";
4106 };
4107
4108 cpu5_bottom_crit: cpu-crit {
4109 temperature = <110000>;
4110 hysteresis = <1000>;
4111 type = "critical";
4112 };
4113 };
4114
4115 cooling-maps {
4116 map0 {
4117 trip = <&cpu5_bottom_alert0>;
4118 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4120 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4121 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4122 };
4123 map1 {
4124 trip = <&cpu5_bottom_alert1>;
4125 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 };
4130 };
4131 };
4132
4133 cpu6-bottom-thermal {
4134 polling-delay-passive = <250>;
4135
4136 thermal-sensors = <&tsens0 13>;
4137
4138 trips {
4139 cpu6_bottom_alert0: trip-point0 {
4140 temperature = <90000>;
4141 hysteresis = <2000>;
4142 type = "passive";
4143 };
4144
4145 cpu6_bottom_alert1: trip-point1 {
4146 temperature = <95000>;
4147 hysteresis = <2000>;
4148 type = "passive";
4149 };
4150
4151 cpu6_bottom_crit: cpu-crit {
4152 temperature = <110000>;
4153 hysteresis = <1000>;
4154 type = "critical";
4155 };
4156 };
4157
4158 cooling-maps {
4159 map0 {
4160 trip = <&cpu6_bottom_alert0>;
4161 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4162 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4165 };
4166 map1 {
4167 trip = <&cpu6_bottom_alert1>;
4168 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4169 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4170 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4171 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4172 };
4173 };
4174 };
4175
4176 cpu7-bottom-thermal {
4177 polling-delay-passive = <250>;
4178
4179 thermal-sensors = <&tsens0 14>;
4180
4181 trips {
4182 cpu7_bottom_alert0: trip-point0 {
4183 temperature = <90000>;
4184 hysteresis = <2000>;
4185 type = "passive";
4186 };
4187
4188 cpu7_bottom_alert1: trip-point1 {
4189 temperature = <95000>;
4190 hysteresis = <2000>;
4191 type = "passive";
4192 };
4193
4194 cpu7_bottom_crit: cpu-crit {
4195 temperature = <110000>;
4196 hysteresis = <1000>;
4197 type = "critical";
4198 };
4199 };
4200
4201 cooling-maps {
4202 map0 {
4203 trip = <&cpu7_bottom_alert0>;
4204 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4205 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4206 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4207 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4208 };
4209 map1 {
4210 trip = <&cpu7_bottom_alert1>;
4211 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4215 };
4216 };
4217 };
4218
4219 aoss0-thermal {
4220 polling-delay-passive = <250>;
4221
4222 thermal-sensors = <&tsens0 0>;
4223
4224 trips {
4225 aoss0_alert0: trip-point0 {
4226 temperature = <90000>;
4227 hysteresis = <2000>;
4228 type = "hot";
4229 };
4230 };
4231 };
4232
4233 cluster0-thermal {
4234 polling-delay-passive = <250>;
4235
4236 thermal-sensors = <&tsens0 5>;
4237
4238 trips {
4239 cluster0_alert0: trip-point0 {
4240 temperature = <90000>;
4241 hysteresis = <2000>;
4242 type = "hot";
4243 };
4244 cluster0_crit: cluster0-crit {
4245 temperature = <110000>;
4246 hysteresis = <2000>;
4247 type = "critical";
4248 };
4249 };
4250 };
4251
4252 cluster1-thermal {
4253 polling-delay-passive = <250>;
4254
4255 thermal-sensors = <&tsens0 6>;
4256
4257 trips {
4258 cluster1_alert0: trip-point0 {
4259 temperature = <90000>;
4260 hysteresis = <2000>;
4261 type = "hot";
4262 };
4263 cluster1_crit: cluster1-crit {
4264 temperature = <110000>;
4265 hysteresis = <2000>;
4266 type = "critical";
4267 };
4268 };
4269 };
4270
4271 aoss1-thermal {
4272 polling-delay-passive = <250>;
4273
4274 thermal-sensors = <&tsens1 0>;
4275
4276 trips {
4277 aoss1_alert0: trip-point0 {
4278 temperature = <90000>;
4279 hysteresis = <2000>;
4280 type = "hot";
4281 };
4282 };
4283 };
4284
4285 gpu-top-thermal {
4286 polling-delay-passive = <250>;
4287
4288 thermal-sensors = <&tsens1 1>;
4289
4290 cooling-maps {
4291 map0 {
4292 trip = <&gpu_top_alert0>;
4293 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4294 };
4295 };
4296
4297 trips {
4298 gpu_top_alert0: trip-point0 {
4299 temperature = <85000>;
4300 hysteresis = <1000>;
4301 type = "passive";
4302 };
4303
4304 trip-point1 {
4305 temperature = <90000>;
4306 hysteresis = <1000>;
4307 type = "hot";
4308 };
4309
4310 trip-point2 {
4311 temperature = <110000>;
4312 hysteresis = <1000>;
4313 type = "critical";
4314 };
4315 };
4316 };
4317
4318 gpu-bottom-thermal {
4319 polling-delay-passive = <250>;
4320
4321 thermal-sensors = <&tsens1 2>;
4322
4323 cooling-maps {
4324 map0 {
4325 trip = <&gpu_bottom_alert0>;
4326 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4327 };
4328 };
4329
4330 trips {
4331 gpu_bottom_alert0: trip-point0 {
4332 temperature = <85000>;
4333 hysteresis = <1000>;
4334 type = "passive";
4335 };
4336
4337 trip-point1 {
4338 temperature = <90000>;
4339 hysteresis = <1000>;
4340 type = "hot";
4341 };
4342
4343 trip-point2 {
4344 temperature = <110000>;
4345 hysteresis = <1000>;
4346 type = "critical";
4347 };
4348 };
4349 };
4350
4351 nspss1-thermal {
4352 polling-delay-passive = <250>;
4353
4354 thermal-sensors = <&tsens1 3>;
4355
4356 trips {
4357 nspss1_alert0: trip-point0 {
4358 temperature = <90000>;
4359 hysteresis = <1000>;
4360 type = "hot";
4361 };
4362 };
4363 };
4364
4365 nspss2-thermal {
4366 polling-delay-passive = <250>;
4367
4368 thermal-sensors = <&tsens1 4>;
4369
4370 trips {
4371 nspss2_alert0: trip-point0 {
4372 temperature = <90000>;
4373 hysteresis = <1000>;
4374 type = "hot";
4375 };
4376 };
4377 };
4378
4379 nspss3-thermal {
4380 polling-delay-passive = <250>;
4381
4382 thermal-sensors = <&tsens1 5>;
4383
4384 trips {
4385 nspss3_alert0: trip-point0 {
4386 temperature = <90000>;
4387 hysteresis = <1000>;
4388 type = "hot";
4389 };
4390 };
4391 };
4392
4393 video-thermal {
4394 polling-delay-passive = <250>;
4395
4396 thermal-sensors = <&tsens1 6>;
4397
4398 trips {
4399 video_alert0: trip-point0 {
4400 temperature = <90000>;
4401 hysteresis = <2000>;
4402 type = "hot";
4403 };
4404 };
4405 };
4406
4407 mem-thermal {
4408 polling-delay-passive = <250>;
4409
4410 thermal-sensors = <&tsens1 7>;
4411
4412 trips {
4413 mem_alert0: trip-point0 {
4414 temperature = <90000>;
4415 hysteresis = <2000>;
4416 type = "hot";
4417 };
4418 };
4419 };
4420
4421 modem1-top-thermal {
4422 polling-delay-passive = <250>;
4423
4424 thermal-sensors = <&tsens1 8>;
4425
4426 trips {
4427 modem1_alert0: trip-point0 {
4428 temperature = <90000>;
4429 hysteresis = <2000>;
4430 type = "hot";
4431 };
4432 };
4433 };
4434
4435 modem2-top-thermal {
4436 polling-delay-passive = <250>;
4437
4438 thermal-sensors = <&tsens1 9>;
4439
4440 trips {
4441 modem2_alert0: trip-point0 {
4442 temperature = <90000>;
4443 hysteresis = <2000>;
4444 type = "hot";
4445 };
4446 };
4447 };
4448
4449 modem3-top-thermal {
4450 polling-delay-passive = <250>;
4451
4452 thermal-sensors = <&tsens1 10>;
4453
4454 trips {
4455 modem3_alert0: trip-point0 {
4456 temperature = <90000>;
4457 hysteresis = <2000>;
4458 type = "hot";
4459 };
4460 };
4461 };
4462
4463 modem4-top-thermal {
4464 polling-delay-passive = <250>;
4465
4466 thermal-sensors = <&tsens1 11>;
4467
4468 trips {
4469 modem4_alert0: trip-point0 {
4470 temperature = <90000>;
4471 hysteresis = <2000>;
4472 type = "hot";
4473 };
4474 };
4475 };
4476
4477 camera-top-thermal {
4478 polling-delay-passive = <250>;
4479
4480 thermal-sensors = <&tsens1 12>;
4481
4482 trips {
4483 camera1_alert0: trip-point0 {
4484 temperature = <90000>;
4485 hysteresis = <2000>;
4486 type = "hot";
4487 };
4488 };
4489 };
4490
4491 cam-bottom-thermal {
4492 polling-delay-passive = <250>;
4493
4494 thermal-sensors = <&tsens1 13>;
4495
4496 trips {
4497 camera2_alert0: trip-point0 {
4498 temperature = <90000>;
4499 hysteresis = <2000>;
4500 type = "hot";
4501 };
4502 };
4503 };
4504 };
4505
4506 timer {
4507 compatible = "arm,armv8-timer";
4508 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4509 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4510 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4511 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4512 };
4513 };
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