1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23
24 / {
25 interrupt-parent = <&intc>;
26
27 #address-cells = <2>;
28 #size-cells = <2>;
29
30 chosen { };
31
32 clocks {
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 clock-frequency = <76800000>;
36 #clock-cells = <0>;
37 };
38
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 clock-frequency = <32000>;
42 #clock-cells = <0>;
43 };
44
45 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-factor-clock";
47 #clock-cells = <0>;
48
49 clocks = <&rpmhcc RPMH_CXO_CLK>;
50 clock-mult = <1>;
51 clock-div = <2>;
52 };
53
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-factor-clock";
56 #clock-cells = <0>;
57
58 clocks = <&rpmhcc RPMH_CXO_CLK_A>;
59 clock-mult = <1>;
60 clock-div = <2>;
61 };
62 };
63
64 cpus {
65 #address-cells = <2>;
66 #size-cells = <0>;
67
68 CPU0: cpu@0 {
69 device_type = "cpu";
70 compatible = "qcom,oryon";
71 reg = <0x0 0x0>;
72 enable-method = "psci";
73 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_PD0>;
75 power-domain-names = "psci";
76 cpu-idle-states = <&CLUSTER_C4>;
77
78 L2_0: l2-cache {
79 compatible = "cache";
80 cache-level = <2>;
81 cache-unified;
82 };
83 };
84
85 CPU1: cpu@100 {
86 device_type = "cpu";
87 compatible = "qcom,oryon";
88 reg = <0x0 0x100>;
89 enable-method = "psci";
90 next-level-cache = <&L2_0>;
91 power-domains = <&CPU_PD1>;
92 power-domain-names = "psci";
93 cpu-idle-states = <&CLUSTER_C4>;
94 };
95
96 CPU2: cpu@200 {
97 device_type = "cpu";
98 compatible = "qcom,oryon";
99 reg = <0x0 0x200>;
100 enable-method = "psci";
101 next-level-cache = <&L2_0>;
102 power-domains = <&CPU_PD2>;
103 power-domain-names = "psci";
104 cpu-idle-states = <&CLUSTER_C4>;
105 };
106
107 CPU3: cpu@300 {
108 device_type = "cpu";
109 compatible = "qcom,oryon";
110 reg = <0x0 0x300>;
111 enable-method = "psci";
112 next-level-cache = <&L2_0>;
113 power-domains = <&CPU_PD3>;
114 power-domain-names = "psci";
115 cpu-idle-states = <&CLUSTER_C4>;
116 };
117
118 CPU4: cpu@10000 {
119 device_type = "cpu";
120 compatible = "qcom,oryon";
121 reg = <0x0 0x10000>;
122 enable-method = "psci";
123 next-level-cache = <&L2_1>;
124 power-domains = <&CPU_PD4>;
125 power-domain-names = "psci";
126 cpu-idle-states = <&CLUSTER_C4>;
127
128 L2_1: l2-cache {
129 compatible = "cache";
130 cache-level = <2>;
131 cache-unified;
132 };
133 };
134
135 CPU5: cpu@10100 {
136 device_type = "cpu";
137 compatible = "qcom,oryon";
138 reg = <0x0 0x10100>;
139 enable-method = "psci";
140 next-level-cache = <&L2_1>;
141 power-domains = <&CPU_PD5>;
142 power-domain-names = "psci";
143 cpu-idle-states = <&CLUSTER_C4>;
144 };
145
146 CPU6: cpu@10200 {
147 device_type = "cpu";
148 compatible = "qcom,oryon";
149 reg = <0x0 0x10200>;
150 enable-method = "psci";
151 next-level-cache = <&L2_1>;
152 power-domains = <&CPU_PD6>;
153 power-domain-names = "psci";
154 cpu-idle-states = <&CLUSTER_C4>;
155 };
156
157 CPU7: cpu@10300 {
158 device_type = "cpu";
159 compatible = "qcom,oryon";
160 reg = <0x0 0x10300>;
161 enable-method = "psci";
162 next-level-cache = <&L2_1>;
163 power-domains = <&CPU_PD7>;
164 power-domain-names = "psci";
165 cpu-idle-states = <&CLUSTER_C4>;
166 };
167
168 CPU8: cpu@20000 {
169 device_type = "cpu";
170 compatible = "qcom,oryon";
171 reg = <0x0 0x20000>;
172 enable-method = "psci";
173 next-level-cache = <&L2_2>;
174 power-domains = <&CPU_PD8>;
175 power-domain-names = "psci";
176 cpu-idle-states = <&CLUSTER_C4>;
177
178 L2_2: l2-cache {
179 compatible = "cache";
180 cache-level = <2>;
181 cache-unified;
182 };
183 };
184
185 CPU9: cpu@20100 {
186 device_type = "cpu";
187 compatible = "qcom,oryon";
188 reg = <0x0 0x20100>;
189 enable-method = "psci";
190 next-level-cache = <&L2_2>;
191 power-domains = <&CPU_PD9>;
192 power-domain-names = "psci";
193 cpu-idle-states = <&CLUSTER_C4>;
194 };
195
196 CPU10: cpu@20200 {
197 device_type = "cpu";
198 compatible = "qcom,oryon";
199 reg = <0x0 0x20200>;
200 enable-method = "psci";
201 next-level-cache = <&L2_2>;
202 power-domains = <&CPU_PD10>;
203 power-domain-names = "psci";
204 cpu-idle-states = <&CLUSTER_C4>;
205 };
206
207 CPU11: cpu@20300 {
208 device_type = "cpu";
209 compatible = "qcom,oryon";
210 reg = <0x0 0x20300>;
211 enable-method = "psci";
212 next-level-cache = <&L2_2>;
213 power-domains = <&CPU_PD11>;
214 power-domain-names = "psci";
215 cpu-idle-states = <&CLUSTER_C4>;
216 };
217
218 cpu-map {
219 cluster0 {
220 core0 {
221 cpu = <&CPU0>;
222 };
223
224 core1 {
225 cpu = <&CPU1>;
226 };
227
228 core2 {
229 cpu = <&CPU2>;
230 };
231
232 core3 {
233 cpu = <&CPU3>;
234 };
235 };
236
237 cluster1 {
238 core0 {
239 cpu = <&CPU4>;
240 };
241
242 core1 {
243 cpu = <&CPU5>;
244 };
245
246 core2 {
247 cpu = <&CPU6>;
248 };
249
250 core3 {
251 cpu = <&CPU7>;
252 };
253 };
254
255 cluster2 {
256 core0 {
257 cpu = <&CPU8>;
258 };
259
260 core1 {
261 cpu = <&CPU9>;
262 };
263
264 core2 {
265 cpu = <&CPU10>;
266 };
267
268 core3 {
269 cpu = <&CPU11>;
270 };
271 };
272 };
273
274 idle-states {
275 entry-method = "psci";
276
277 CLUSTER_C4: cpu-sleep-0 {
278 compatible = "arm,idle-state";
279 idle-state-name = "ret";
280 arm,psci-suspend-param = <0x00000004>;
281 entry-latency-us = <180>;
282 exit-latency-us = <320>;
283 min-residency-us = <1000>;
284 };
285 };
286
287 domain-idle-states {
288 CLUSTER_CL4: cluster-sleep-0 {
289 compatible = "domain-idle-state";
290 idle-state-name = "l2-ret";
291 arm,psci-suspend-param = <0x01000044>;
292 entry-latency-us = <350>;
293 exit-latency-us = <500>;
294 min-residency-us = <2500>;
295 };
296
297 CLUSTER_CL5: cluster-sleep-1 {
298 compatible = "domain-idle-state";
299 idle-state-name = "ret-pll-off";
300 arm,psci-suspend-param = <0x01000054>;
301 entry-latency-us = <2200>;
302 exit-latency-us = <2500>;
303 min-residency-us = <7000>;
304 };
305 };
306 };
307
308 firmware {
309 scm: scm {
310 compatible = "qcom,scm-x1e80100", "qcom,scm";
311 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
313 };
314 };
315
316 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-clk-virt";
318 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_voter>;
320 };
321
322 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc-virt";
324 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_voter>;
326 };
327
328 memory@80000000 {
329 device_type = "memory";
330 /* We expect the bootloader to fill in the size */
331 reg = <0 0x80000000 0 0>;
332 };
333
334 pmu {
335 compatible = "arm,armv8-pmuv3";
336 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
337 };
338
339 psci {
340 compatible = "arm,psci-1.0";
341 method = "smc";
342
343 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells = <0>;
345 power-domains = <&CLUSTER_PD0>;
346 };
347
348 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells = <0>;
350 power-domains = <&CLUSTER_PD0>;
351 };
352
353 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD0>;
356 };
357
358 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells = <0>;
360 power-domains = <&CLUSTER_PD0>;
361 };
362
363 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells = <0>;
365 power-domains = <&CLUSTER_PD1>;
366 };
367
368 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD1>;
371 };
372
373 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells = <0>;
375 power-domains = <&CLUSTER_PD1>;
376 };
377
378 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells = <0>;
380 power-domains = <&CLUSTER_PD1>;
381 };
382
383 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells = <0>;
385 power-domains = <&CLUSTER_PD2>;
386 };
387
388 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells = <0>;
390 power-domains = <&CLUSTER_PD2>;
391 };
392
393 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells = <0>;
395 power-domains = <&CLUSTER_PD2>;
396 };
397
398 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells = <0>;
400 power-domains = <&CLUSTER_PD2>;
401 };
402
403 CLUSTER_PD0: power-domain-cpu-cluster0 {
404 #power-domain-cells = <0>;
405 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
406 power-domains = <&SYSTEM_PD>;
407 };
408
409 CLUSTER_PD1: power-domain-cpu-cluster1 {
410 #power-domain-cells = <0>;
411 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
412 power-domains = <&SYSTEM_PD>;
413 };
414
415 CLUSTER_PD2: power-domain-cpu-cluster2 {
416 #power-domain-cells = <0>;
417 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
418 power-domains = <&SYSTEM_PD>;
419 };
420
421 SYSTEM_PD: power-domain-system {
422 #power-domain-cells = <0>;
423 /* TODO: system-wide idle states */
424 };
425 };
426
427 reserved-memory {
428 #address-cells = <2>;
429 #size-cells = <2>;
430 ranges;
431
432 gunyah_hyp_mem: gunyah-hyp@80000000 {
433 reg = <0x0 0x80000000 0x0 0x800000>;
434 no-map;
435 };
436
437 hyp_elf_package_mem: hyp-elf-package@80800000 {
438 reg = <0x0 0x80800000 0x0 0x200000>;
439 no-map;
440 };
441
442 ncc_mem: ncc@80a00000 {
443 reg = <0x0 0x80a00000 0x0 0x400000>;
444 no-map;
445 };
446
447 cpucp_log_mem: cpucp-log@80e00000 {
448 reg = <0x0 0x80e00000 0x0 0x40000>;
449 no-map;
450 };
451
452 cpucp_mem: cpucp@80e40000 {
453 reg = <0x0 0x80e40000 0x0 0x540000>;
454 no-map;
455 };
456
457 reserved-region@81380000 {
458 reg = <0x0 0x81380000 0x0 0x80000>;
459 no-map;
460 };
461
462 tags_mem: tags-region@81400000 {
463 reg = <0x0 0x81400000 0x0 0x1a0000>;
464 no-map;
465 };
466
467 xbl_dtlog_mem: xbl-dtlog@81a00000 {
468 reg = <0x0 0x81a00000 0x0 0x40000>;
469 no-map;
470 };
471
472 xbl_ramdump_mem: xbl-ramdump@81a40000 {
473 reg = <0x0 0x81a40000 0x0 0x1c0000>;
474 no-map;
475 };
476
477 aop_image_mem: aop-image@81c00000 {
478 reg = <0x0 0x81c00000 0x0 0x60000>;
479 no-map;
480 };
481
482 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd-db";
484 reg = <0x0 0x81c60000 0x0 0x20000>;
485 no-map;
486 };
487
488 aop_config_mem: aop-config@81c80000 {
489 reg = <0x0 0x81c80000 0x0 0x20000>;
490 no-map;
491 };
492
493 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
494 reg = <0x0 0x81ca0000 0x0 0x40000>;
495 no-map;
496 };
497
498 tme_log_mem: tme-log@81ce0000 {
499 reg = <0x0 0x81ce0000 0x0 0x4000>;
500 no-map;
501 };
502
503 uefi_log_mem: uefi-log@81ce4000 {
504 reg = <0x0 0x81ce4000 0x0 0x10000>;
505 no-map;
506 };
507
508 secdata_apss_mem: secdata-apss@81cff000 {
509 reg = <0x0 0x81cff000 0x0 0x1000>;
510 no-map;
511 };
512
513 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
514 reg = <0x0 0x81e00000 0x0 0x100000>;
515 no-map;
516 };
517
518 gpu_prr_mem: gpu-prr@81f00000 {
519 reg = <0x0 0x81f00000 0x0 0x10000>;
520 no-map;
521 };
522
523 tpm_control_mem: tpm-control@81f10000 {
524 reg = <0x0 0x81f10000 0x0 0x10000>;
525 no-map;
526 };
527
528 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
529 reg = <0x0 0x81f20000 0x0 0x10000>;
530 no-map;
531 };
532
533 pld_pep_mem: pld-pep@81f30000 {
534 reg = <0x0 0x81f30000 0x0 0x6000>;
535 no-map;
536 };
537
538 pld_gmu_mem: pld-gmu@81f36000 {
539 reg = <0x0 0x81f36000 0x0 0x1000>;
540 no-map;
541 };
542
543 pld_pdp_mem: pld-pdp@81f37000 {
544 reg = <0x0 0x81f37000 0x0 0x1000>;
545 no-map;
546 };
547
548 tz_stat_mem: tz-stat@82700000 {
549 reg = <0x0 0x82700000 0x0 0x100000>;
550 no-map;
551 };
552
553 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
554 reg = <0x0 0x82800000 0x0 0xc00000>;
555 no-map;
556 };
557
558 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
559 reg = <0x0 0x84b00000 0x0 0x800000>;
560 no-map;
561 };
562
563 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
564 reg = <0x0 0x85300000 0x0 0x80000>;
565 no-map;
566 };
567
568 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
569 reg = <0x0 0x866c0000 0x0 0x40000>;
570 no-map;
571 };
572
573 spss_region_mem: spss-region@86700000 {
574 reg = <0x0 0x86700000 0x0 0x400000>;
575 no-map;
576 };
577
578 adsp_boot_mem: adsp-boot@86b00000 {
579 reg = <0x0 0x86b00000 0x0 0xc00000>;
580 no-map;
581 };
582
583 video_mem: video@87700000 {
584 reg = <0x0 0x87700000 0x0 0x700000>;
585 no-map;
586 };
587
588 adspslpi_mem: adspslpi@87e00000 {
589 reg = <0x0 0x87e00000 0x0 0x3a00000>;
590 no-map;
591 };
592
593 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
594 reg = <0x0 0x8b800000 0x0 0x80000>;
595 no-map;
596 };
597
598 cdsp_mem: cdsp@8b900000 {
599 reg = <0x0 0x8b900000 0x0 0x2000000>;
600 no-map;
601 };
602
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
604 reg = <0x0 0x8d900000 0x0 0x80000>;
605 no-map;
606 };
607
608 gpu_microcode_mem: gpu-microcode@8d9fe000 {
609 reg = <0x0 0x8d9fe000 0x0 0x2000>;
610 no-map;
611 };
612
613 cvp_mem: cvp@8da00000 {
614 reg = <0x0 0x8da00000 0x0 0x700000>;
615 no-map;
616 };
617
618 camera_mem: camera@8e100000 {
619 reg = <0x0 0x8e100000 0x0 0x800000>;
620 no-map;
621 };
622
623 av1_encoder_mem: av1-encoder@8e900000 {
624 reg = <0x0 0x8e900000 0x0 0x700000>;
625 no-map;
626 };
627
628 reserved-region@8f000000 {
629 reg = <0x0 0x8f000000 0x0 0xa00000>;
630 no-map;
631 };
632
633 wpss_mem: wpss@8fa00000 {
634 reg = <0x0 0x8fa00000 0x0 0x1900000>;
635 no-map;
636 };
637
638 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
639 reg = <0x0 0x91300000 0x0 0x80000>;
640 no-map;
641 };
642
643 xbl_sc_mem: xbl-sc@d8000000 {
644 reg = <0x0 0xd8000000 0x0 0x40000>;
645 no-map;
646 };
647
648 reserved-region@d8040000 {
649 reg = <0x0 0xd8040000 0x0 0xa0000>;
650 no-map;
651 };
652
653 qtee_mem: qtee@d80e0000 {
654 reg = <0x0 0xd80e0000 0x0 0x520000>;
655 no-map;
656 };
657
658 ta_mem: ta@d8600000 {
659 reg = <0x0 0xd8600000 0x0 0x8a00000>;
660 no-map;
661 };
662
663 tags_mem1: tags@e1000000 {
664 reg = <0x0 0xe1000000 0x0 0x26a0000>;
665 no-map;
666 };
667
668 llcc_lpi_mem: llcc-lpi@ff800000 {
669 reg = <0x0 0xff800000 0x0 0x600000>;
670 no-map;
671 };
672
673 smem_mem: smem@ffe00000 {
674 compatible = "qcom,smem";
675 reg = <0x0 0xffe00000 0x0 0x200000>;
676 hwlocks = <&tcsr_mutex 3>;
677 no-map;
678 };
679 };
680
681 smp2p-adsp {
682 compatible = "qcom,smp2p";
683
684 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
685 IPCC_MPROC_SIGNAL_SMP2P
686 IRQ_TYPE_EDGE_RISING>;
687
688 mboxes = <&ipcc IPCC_CLIENT_LPASS
689 IPCC_MPROC_SIGNAL_SMP2P>;
690
691 qcom,smem = <443>, <429>;
692 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>;
694
695 smp2p_adsp_out: master-kernel {
696 qcom,entry-name = "master-kernel";
697 #qcom,smem-state-cells = <1>;
698 };
699
700 smp2p_adsp_in: slave-kernel {
701 qcom,entry-name = "slave-kernel";
702 interrupt-controller;
703 #interrupt-cells = <2>;
704 };
705 };
706
707 smp2p-cdsp {
708 compatible = "qcom,smp2p";
709
710 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
711 IPCC_MPROC_SIGNAL_SMP2P
712 IRQ_TYPE_EDGE_RISING>;
713
714 mboxes = <&ipcc IPCC_CLIENT_CDSP
715 IPCC_MPROC_SIGNAL_SMP2P>;
716
717 qcom,smem = <94>, <432>;
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <5>;
720
721 smp2p_cdsp_out: master-kernel {
722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells = <1>;
724 };
725
726 smp2p_cdsp_in: slave-kernel {
727 qcom,entry-name = "slave-kernel";
728 interrupt-controller;
729 #interrupt-cells = <2>;
730 };
731 };
732
733 soc: soc@0 {
734 compatible = "simple-bus";
735
736 #address-cells = <2>;
737 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>;
739 ranges = <0 0 0 0 0x10 0>;
740
741 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e80100-gcc";
743 reg = <0 0x00100000 0 0x200000>;
744
745 clocks = <&bi_tcxo_div2>,
746 <&sleep_clk>,
747 <0>,
748 <&pcie4_phy>,
749 <&pcie5_phy>,
750 <&pcie6a_phy>,
751 <0>,
752 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
753 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
754 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
755
756 power-domains = <&rpmhpd RPMHPD_CX>;
757 #clock-cells = <1>;
758 #reset-cells = <1>;
759 #power-domain-cells = <1>;
760 };
761
762 ipcc: mailbox@408000 {
763 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
764 reg = <0 0x00408000 0 0x1000>;
765
766 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
767 interrupt-controller;
768 #interrupt-cells = <3>;
769
770 #mbox-cells = <2>;
771 };
772
773 gpi_dma2: dma-controller@800000 {
774 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
775 reg = <0 0x00800000 0 0x60000>;
776
777 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
789
790 dma-channels = <12>;
791 dma-channel-mask = <0x3e>;
792 #dma-cells = <3>;
793
794 iommus = <&apps_smmu 0x436 0x0>;
795
796 status = "disabled";
797 };
798
799 qupv3_2: geniqup@8c0000 {
800 compatible = "qcom,geni-se-qup";
801 reg = <0 0x008c0000 0 0x2000>;
802
803 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
804 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
805 clock-names = "m-ahb",
806 "s-ahb";
807
808 iommus = <&apps_smmu 0x423 0x0>;
809
810 #address-cells = <2>;
811 #size-cells = <2>;
812 ranges;
813
814 status = "disabled";
815
816 i2c16: i2c@880000 {
817 compatible = "qcom,geni-i2c";
818 reg = <0 0x00880000 0 0x4000>;
819
820 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
821
822 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
823 clock-names = "se";
824
825 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
826 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
827 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
828 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
829 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
830 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
831 interconnect-names = "qup-core",
832 "qup-config",
833 "qup-memory";
834
835 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
836 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
837 dma-names = "tx",
838 "rx";
839
840 pinctrl-0 = <&qup_i2c16_data_clk>;
841 pinctrl-names = "default";
842
843 #address-cells = <1>;
844 #size-cells = <0>;
845
846 status = "disabled";
847 };
848
849 spi16: spi@880000 {
850 compatible = "qcom,geni-spi";
851 reg = <0 0x00880000 0 0x4000>;
852
853 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
854
855 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
856 clock-names = "se";
857
858 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
859 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
860 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
861 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
862 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
863 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
864 interconnect-names = "qup-core",
865 "qup-config",
866 "qup-memory";
867
868 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
869 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
870 dma-names = "tx",
871 "rx";
872
873 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 pinctrl-names = "default";
875
876 #address-cells = <1>;
877 #size-cells = <0>;
878
879 status = "disabled";
880 };
881
882 i2c17: i2c@884000 {
883 compatible = "qcom,geni-i2c";
884 reg = <0 0x00884000 0 0x4000>;
885
886 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
887
888 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
889 clock-names = "se";
890
891 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
892 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
893 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
894 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
895 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
896 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
897 interconnect-names = "qup-core",
898 "qup-config",
899 "qup-memory";
900
901 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
902 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
903 dma-names = "tx",
904 "rx";
905
906 pinctrl-0 = <&qup_i2c17_data_clk>;
907 pinctrl-names = "default";
908
909 #address-cells = <1>;
910 #size-cells = <0>;
911
912 status = "disabled";
913 };
914
915 spi17: spi@884000 {
916 compatible = "qcom,geni-spi";
917 reg = <0 0x00884000 0 0x4000>;
918
919 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
920
921 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
922 clock-names = "se";
923
924 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
925 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
926 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
927 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
928 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
930 interconnect-names = "qup-core",
931 "qup-config",
932 "qup-memory";
933
934 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
935 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
936 dma-names = "tx",
937 "rx";
938
939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
940 pinctrl-names = "default";
941
942 #address-cells = <1>;
943 #size-cells = <0>;
944
945 status = "disabled";
946 };
947
948 i2c18: i2c@888000 {
949 compatible = "qcom,geni-i2c";
950 reg = <0 0x00888000 0 0x4000>;
951
952 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
953
954 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
955 clock-names = "se";
956
957 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
958 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
959 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
960 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
961 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
963 interconnect-names = "qup-core",
964 "qup-config",
965 "qup-memory";
966
967 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
968 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
969 dma-names = "tx",
970 "rx";
971
972 pinctrl-0 = <&qup_i2c18_data_clk>;
973 pinctrl-names = "default";
974
975 #address-cells = <1>;
976 #size-cells = <0>;
977
978 status = "disabled";
979 };
980
981 spi18: spi@888000 {
982 compatible = "qcom,geni-spi";
983 reg = <0 0x00888000 0 0x4000>;
984
985 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
986
987 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
988 clock-names = "se";
989
990 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
991 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
993 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
994 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
996 interconnect-names = "qup-core",
997 "qup-config",
998 "qup-memory";
999
1000 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1001 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1002 dma-names = "tx",
1003 "rx";
1004
1005 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1006 pinctrl-names = "default";
1007
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1010
1011 status = "disabled";
1012 };
1013
1014 i2c19: i2c@88c000 {
1015 compatible = "qcom,geni-i2c";
1016 reg = <0 0x0088c000 0 0x4000>;
1017
1018 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1019
1020 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1021 clock-names = "se";
1022
1023 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1024 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1025 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1026 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1027 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1029 interconnect-names = "qup-core",
1030 "qup-config",
1031 "qup-memory";
1032
1033 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1034 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1035 dma-names = "tx",
1036 "rx";
1037
1038 pinctrl-0 = <&qup_i2c19_data_clk>;
1039 pinctrl-names = "default";
1040
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043
1044 status = "disabled";
1045 };
1046
1047 spi19: spi@88c000 {
1048 compatible = "qcom,geni-spi";
1049 reg = <0 0x0088c000 0 0x4000>;
1050
1051 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1052
1053 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1054 clock-names = "se";
1055
1056 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1057 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1058 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1059 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1060 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1062 interconnect-names = "qup-core",
1063 "qup-config",
1064 "qup-memory";
1065
1066 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1067 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1068 dma-names = "tx",
1069 "rx";
1070
1071 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1072 pinctrl-names = "default";
1073
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1076
1077 status = "disabled";
1078 };
1079
1080 i2c20: i2c@890000 {
1081 compatible = "qcom,geni-i2c";
1082 reg = <0 0x00890000 0 0x4000>;
1083
1084 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1085
1086 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1087 clock-names = "se";
1088
1089 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1090 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1091 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1092 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1093 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1095 interconnect-names = "qup-core",
1096 "qup-config",
1097 "qup-memory";
1098
1099 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1100 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1101 dma-names = "tx",
1102 "rx";
1103
1104 pinctrl-0 = <&qup_i2c20_data_clk>;
1105 pinctrl-names = "default";
1106
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1109
1110 status = "disabled";
1111 };
1112
1113 spi20: spi@890000 {
1114 compatible = "qcom,geni-spi";
1115 reg = <0 0x00890000 0 0x4000>;
1116
1117 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1118
1119 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1120 clock-names = "se";
1121
1122 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1123 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1124 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1125 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1126 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1128 interconnect-names = "qup-core",
1129 "qup-config",
1130 "qup-memory";
1131
1132 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1133 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1134 dma-names = "tx",
1135 "rx";
1136
1137 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1138 pinctrl-names = "default";
1139
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1142
1143 status = "disabled";
1144 };
1145
1146 i2c21: i2c@894000 {
1147 compatible = "qcom,geni-i2c";
1148 reg = <0 0x00894000 0 0x4000>;
1149
1150 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1151
1152 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1153 clock-names = "se";
1154
1155 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1156 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1158 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1159 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1161 interconnect-names = "qup-core",
1162 "qup-config",
1163 "qup-memory";
1164
1165 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1166 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1167 dma-names = "tx",
1168 "rx";
1169
1170 pinctrl-0 = <&qup_i2c21_data_clk>;
1171 pinctrl-names = "default";
1172
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1175
1176 status = "disabled";
1177 };
1178
1179 spi21: spi@894000 {
1180 compatible = "qcom,geni-spi";
1181 reg = <0 0x00894000 0 0x4000>;
1182
1183 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1184
1185 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1186 clock-names = "se";
1187
1188 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1189 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1190 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1191 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1192 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1193 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1194 interconnect-names = "qup-core",
1195 "qup-config",
1196 "qup-memory";
1197
1198 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1199 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1200 dma-names = "tx",
1201 "rx";
1202
1203 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1204 pinctrl-names = "default";
1205
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1208
1209 status = "disabled";
1210 };
1211
1212 uart21: serial@894000 {
1213 compatible = "qcom,geni-uart";
1214 reg = <0 0x00894000 0 0x4000>;
1215
1216 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1217
1218 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1219 clock-names = "se";
1220
1221 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1222 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1223 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1224 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1225 interconnect-names = "qup-core",
1226 "qup-config";
1227
1228 pinctrl-0 = <&qup_uart21_default>;
1229 pinctrl-names = "default";
1230
1231 status = "disabled";
1232 };
1233
1234 i2c22: i2c@898000 {
1235 compatible = "qcom,geni-i2c";
1236 reg = <0 0x00898000 0 0x4000>;
1237
1238 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1239
1240 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1241 clock-names = "se";
1242
1243 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1244 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1246 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1247 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1249 interconnect-names = "qup-core",
1250 "qup-config",
1251 "qup-memory";
1252
1253 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1254 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1255 dma-names = "tx",
1256 "rx";
1257
1258 pinctrl-0 = <&qup_i2c22_data_clk>;
1259 pinctrl-names = "default";
1260
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1263
1264 status = "disabled";
1265 };
1266
1267 spi22: spi@898000 {
1268 compatible = "qcom,geni-spi";
1269 reg = <0 0x00898000 0 0x4000>;
1270
1271 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1272
1273 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1274 clock-names = "se";
1275
1276 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1277 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1279 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1280 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1282 interconnect-names = "qup-core",
1283 "qup-config",
1284 "qup-memory";
1285
1286 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1287 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1288 dma-names = "tx",
1289 "rx";
1290
1291 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1292 pinctrl-names = "default";
1293
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1296
1297 status = "disabled";
1298 };
1299
1300 i2c23: i2c@89c000 {
1301 compatible = "qcom,geni-i2c";
1302 reg = <0 0x0089c000 0 0x4000>;
1303
1304 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1305
1306 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1307 clock-names = "se";
1308
1309 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1310 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1311 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1312 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1313 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1315 interconnect-names = "qup-core",
1316 "qup-config",
1317 "qup-memory";
1318
1319 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1320 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1321 dma-names = "tx",
1322 "rx";
1323
1324 pinctrl-0 = <&qup_i2c23_data_clk>;
1325 pinctrl-names = "default";
1326
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1329
1330 status = "disabled";
1331 };
1332
1333 spi23: spi@89c000 {
1334 compatible = "qcom,geni-spi";
1335 reg = <0 0x0089c000 0 0x4000>;
1336
1337 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1338
1339 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1340 clock-names = "se";
1341
1342 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1343 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1345 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1346 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1348 interconnect-names = "qup-core",
1349 "qup-config",
1350 "qup-memory";
1351
1352 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1353 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1354 dma-names = "tx",
1355 "rx";
1356
1357 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1358 pinctrl-names = "default";
1359
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362
1363 status = "disabled";
1364 };
1365 };
1366
1367 gpi_dma1: dma-controller@a00000 {
1368 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1369 reg = <0 0x00a00000 0 0x60000>;
1370
1371 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
1383
1384 dma-channels = <12>;
1385 dma-channel-mask = <0x3e>;
1386 #dma-cells = <3>;
1387
1388 iommus = <&apps_smmu 0x136 0x0>;
1389
1390 status = "disabled";
1391 };
1392
1393 qupv3_1: geniqup@ac0000 {
1394 compatible = "qcom,geni-se-qup";
1395 reg = <0 0x00ac0000 0 0x2000>;
1396
1397 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1398 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1399 clock-names = "m-ahb",
1400 "s-ahb";
1401
1402 iommus = <&apps_smmu 0x123 0x0>;
1403
1404 #address-cells = <2>;
1405 #size-cells = <2>;
1406 ranges;
1407
1408 status = "disabled";
1409
1410 i2c8: i2c@a80000 {
1411 compatible = "qcom,geni-i2c";
1412 reg = <0 0x00a80000 0 0x4000>;
1413
1414 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1415
1416 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1417 clock-names = "se";
1418
1419 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1420 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1422 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1423 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1424 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1425 interconnect-names = "qup-core",
1426 "qup-config",
1427 "qup-memory";
1428
1429 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1430 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1431 dma-names = "tx",
1432 "rx";
1433
1434 pinctrl-0 = <&qup_i2c8_data_clk>;
1435 pinctrl-names = "default";
1436
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1439
1440 status = "disabled";
1441 };
1442
1443 spi8: spi@a80000 {
1444 compatible = "qcom,geni-spi";
1445 reg = <0 0x00a80000 0 0x4000>;
1446
1447 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1448
1449 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1450 clock-names = "se";
1451
1452 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1453 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1454 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1455 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1456 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1457 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1458 interconnect-names = "qup-core",
1459 "qup-config",
1460 "qup-memory";
1461
1462 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1463 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1464 dma-names = "tx",
1465 "rx";
1466
1467 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1468 pinctrl-names = "default";
1469
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472
1473 status = "disabled";
1474 };
1475
1476 i2c9: i2c@a84000 {
1477 compatible = "qcom,geni-i2c";
1478 reg = <0 0x00a84000 0 0x4000>;
1479
1480 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1481
1482 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1483 clock-names = "se";
1484
1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1486 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1487 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1488 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1489 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1490 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1491 interconnect-names = "qup-core",
1492 "qup-config",
1493 "qup-memory";
1494
1495 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1496 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1497 dma-names = "tx",
1498 "rx";
1499
1500 pinctrl-0 = <&qup_i2c9_data_clk>;
1501 pinctrl-names = "default";
1502
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1505
1506 status = "disabled";
1507 };
1508
1509 spi9: spi@a84000 {
1510 compatible = "qcom,geni-spi";
1511 reg = <0 0x00a84000 0 0x4000>;
1512
1513 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1514
1515 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1516 clock-names = "se";
1517
1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect-names = "qup-core",
1525 "qup-config",
1526 "qup-memory";
1527
1528 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1529 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1530 dma-names = "tx",
1531 "rx";
1532
1533 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 pinctrl-names = "default";
1535
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1538
1539 status = "disabled";
1540 };
1541
1542 i2c10: i2c@a88000 {
1543 compatible = "qcom,geni-i2c";
1544 reg = <0 0x00a88000 0 0x4000>;
1545
1546 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1547
1548 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1549 clock-names = "se";
1550
1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1552 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1553 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1554 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1555 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1556 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1557 interconnect-names = "qup-core",
1558 "qup-config",
1559 "qup-memory";
1560
1561 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1562 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1563 dma-names = "tx",
1564 "rx";
1565
1566 pinctrl-0 = <&qup_i2c10_data_clk>;
1567 pinctrl-names = "default";
1568
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571
1572 status = "disabled";
1573 };
1574
1575 spi10: spi@a88000 {
1576 compatible = "qcom,geni-spi";
1577 reg = <0 0x00a88000 0 0x4000>;
1578
1579 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1580
1581 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1582 clock-names = "se";
1583
1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1585 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1587 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1588 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1590 interconnect-names = "qup-core",
1591 "qup-config",
1592 "qup-memory";
1593
1594 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1595 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1596 dma-names = "tx",
1597 "rx";
1598
1599 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 pinctrl-names = "default";
1601
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604
1605 status = "disabled";
1606 };
1607
1608 i2c11: i2c@a8c000 {
1609 compatible = "qcom,geni-i2c";
1610 reg = <0 0x00a8c000 0 0x4000>;
1611
1612 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1613
1614 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1615 clock-names = "se";
1616
1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect-names = "qup-core",
1624 "qup-config",
1625 "qup-memory";
1626
1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1628 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1629 dma-names = "tx",
1630 "rx";
1631
1632 pinctrl-0 = <&qup_i2c11_data_clk>;
1633 pinctrl-names = "default";
1634
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1637
1638 status = "disabled";
1639 };
1640
1641 spi11: spi@a8c000 {
1642 compatible = "qcom,geni-spi";
1643 reg = <0 0x00a8c000 0 0x4000>;
1644
1645 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1646
1647 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1648 clock-names = "se";
1649
1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1651 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1653 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1654 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1656 interconnect-names = "qup-core",
1657 "qup-config",
1658 "qup-memory";
1659
1660 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1661 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1662 dma-names = "tx",
1663 "rx";
1664
1665 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1666 pinctrl-names = "default";
1667
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670
1671 status = "disabled";
1672 };
1673
1674 i2c12: i2c@a90000 {
1675 compatible = "qcom,geni-i2c";
1676 reg = <0 0x00a90000 0 0x4000>;
1677
1678 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1679
1680 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1681 clock-names = "se";
1682
1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1684 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1685 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1686 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1687 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1688 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1689 interconnect-names = "qup-core",
1690 "qup-config",
1691 "qup-memory";
1692
1693 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1694 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1695 dma-names = "tx",
1696 "rx";
1697
1698 pinctrl-0 = <&qup_i2c12_data_clk>;
1699 pinctrl-names = "default";
1700
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1703
1704 status = "disabled";
1705 };
1706
1707 spi12: spi@a90000 {
1708 compatible = "qcom,geni-spi";
1709 reg = <0 0x00a90000 0 0x4000>;
1710
1711 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1712
1713 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1714 clock-names = "se";
1715
1716 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1717 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1718 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1719 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1720 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1721 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1722 interconnect-names = "qup-core",
1723 "qup-config",
1724 "qup-memory";
1725
1726 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1727 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1728 dma-names = "tx",
1729 "rx";
1730
1731 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1732 pinctrl-names = "default";
1733
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1736
1737 status = "disabled";
1738 };
1739
1740 i2c13: i2c@a94000 {
1741 compatible = "qcom,geni-i2c";
1742 reg = <0 0x00a94000 0 0x4000>;
1743
1744 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1745
1746 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1747 clock-names = "se";
1748
1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1750 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1752 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1753 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1755 interconnect-names = "qup-core",
1756 "qup-config",
1757 "qup-memory";
1758
1759 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1760 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1761 dma-names = "tx",
1762 "rx";
1763
1764 pinctrl-0 = <&qup_i2c13_data_clk>;
1765 pinctrl-names = "default";
1766
1767 #address-cells = <1>;
1768 #size-cells = <0>;
1769
1770 status = "disabled";
1771 };
1772
1773 spi13: spi@a94000 {
1774 compatible = "qcom,geni-spi";
1775 reg = <0 0x00a94000 0 0x4000>;
1776
1777 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1778
1779 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1780 clock-names = "se";
1781
1782 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1783 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1784 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1785 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1786 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1787 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1788 interconnect-names = "qup-core",
1789 "qup-config",
1790 "qup-memory";
1791
1792 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1793 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1794 dma-names = "tx",
1795 "rx";
1796
1797 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1798 pinctrl-names = "default";
1799
1800 #address-cells = <1>;
1801 #size-cells = <0>;
1802
1803 status = "disabled";
1804 };
1805
1806 i2c14: i2c@a98000 {
1807 compatible = "qcom,geni-i2c";
1808 reg = <0 0x00a98000 0 0x4000>;
1809
1810 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1811
1812 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1813 clock-names = "se";
1814
1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1816 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1818 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1819 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1821 interconnect-names = "qup-core",
1822 "qup-config",
1823 "qup-memory";
1824
1825 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1826 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1827 dma-names = "tx",
1828 "rx";
1829
1830 pinctrl-0 = <&qup_i2c14_data_clk>;
1831 pinctrl-names = "default";
1832
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1835
1836 status = "disabled";
1837 };
1838
1839 spi14: spi@a98000 {
1840 compatible = "qcom,geni-spi";
1841 reg = <0 0x00a98000 0 0x4000>;
1842
1843 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1844
1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1846 clock-names = "se";
1847
1848 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1849 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1850 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1851 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1852 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1853 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1854 interconnect-names = "qup-core",
1855 "qup-config",
1856 "qup-memory";
1857
1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1859 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1860 dma-names = "tx",
1861 "rx";
1862
1863 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1864 pinctrl-names = "default";
1865
1866 #address-cells = <1>;
1867 #size-cells = <0>;
1868
1869 status = "disabled";
1870 };
1871
1872 i2c15: i2c@a9c000 {
1873 compatible = "qcom,geni-i2c";
1874 reg = <0 0x00a9c000 0 0x4000>;
1875
1876 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1877
1878 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1879 clock-names = "se";
1880
1881 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1882 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1884 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1885 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1887 interconnect-names = "qup-core",
1888 "qup-config",
1889 "qup-memory";
1890
1891 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1892 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1893 dma-names = "tx",
1894 "rx";
1895
1896 pinctrl-0 = <&qup_i2c15_data_clk>;
1897 pinctrl-names = "default";
1898
1899 #address-cells = <1>;
1900 #size-cells = <0>;
1901
1902 status = "disabled";
1903 };
1904
1905 spi15: spi@a9c000 {
1906 compatible = "qcom,geni-spi";
1907 reg = <0 0x00a9c000 0 0x4000>;
1908
1909 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1910
1911 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1912 clock-names = "se";
1913
1914 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1915 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1917 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1918 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1920 interconnect-names = "qup-core",
1921 "qup-config",
1922 "qup-memory";
1923
1924 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1925 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1926 dma-names = "tx",
1927 "rx";
1928
1929 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1930 pinctrl-names = "default";
1931
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934
1935 status = "disabled";
1936 };
1937 };
1938
1939 gpi_dma0: dma-controller@b00000 {
1940 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1941 reg = <0 0x00b00000 0 0x60000>;
1942
1943 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
1955
1956 dma-channels = <12>;
1957 dma-channel-mask = <0x3e>;
1958 #dma-cells = <3>;
1959
1960 iommus = <&apps_smmu 0x456 0x0>;
1961
1962 status = "disabled";
1963 };
1964
1965 qupv3_0: geniqup@bc0000 {
1966 compatible = "qcom,geni-se-qup";
1967 reg = <0 0x00bc0000 0 0x2000>;
1968
1969 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1970 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1971 clock-names = "m-ahb",
1972 "s-ahb";
1973
1974 iommus = <&apps_smmu 0x443 0x0>;
1975 #address-cells = <2>;
1976 #size-cells = <2>;
1977 ranges;
1978
1979 status = "disabled";
1980
1981 i2c0: i2c@b80000 {
1982 compatible = "qcom,geni-i2c";
1983 reg = <0 0x00b80000 0 0x4000>;
1984
1985 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1986
1987 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1988 clock-names = "se";
1989
1990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1996 interconnect-names = "qup-core",
1997 "qup-config",
1998 "qup-memory";
1999
2000 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2001 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2002 dma-names = "tx",
2003 "rx";
2004
2005 pinctrl-0 = <&qup_i2c0_data_clk>;
2006 pinctrl-names = "default";
2007
2008 #address-cells = <1>;
2009 #size-cells = <0>;
2010
2011 status = "disabled";
2012 };
2013
2014 spi0: spi@b80000 {
2015 compatible = "qcom,geni-spi";
2016 reg = <0 0x00b80000 0 0x4000>;
2017
2018 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2019
2020 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2021 clock-names = "se";
2022
2023 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2024 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2025 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2026 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2027 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2029 interconnect-names = "qup-core",
2030 "qup-config",
2031 "qup-memory";
2032
2033 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2034 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2035 dma-names = "tx",
2036 "rx";
2037
2038 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2039 pinctrl-names = "default";
2040
2041 #address-cells = <1>;
2042 #size-cells = <0>;
2043
2044 status = "disabled";
2045 };
2046
2047 i2c1: i2c@b84000 {
2048 compatible = "qcom,geni-i2c";
2049 reg = <0 0x00b84000 0 0x4000>;
2050
2051 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2052
2053 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2054 clock-names = "se";
2055
2056 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2057 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2058 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2059 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2060 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2062 interconnect-names = "qup-core",
2063 "qup-config",
2064 "qup-memory";
2065
2066 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2067 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
2068 dma-names = "tx",
2069 "rx";
2070
2071 pinctrl-0 = <&qup_i2c1_data_clk>;
2072 pinctrl-names = "default";
2073
2074 #address-cells = <1>;
2075 #size-cells = <0>;
2076
2077 status = "disabled";
2078 };
2079
2080 spi1: spi@b84000 {
2081 compatible = "qcom,geni-spi";
2082 reg = <0 0x00b84000 0 0x4000>;
2083
2084 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2085
2086 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2087 clock-names = "se";
2088
2089 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2090 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2091 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2092 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2093 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2095 interconnect-names = "qup-core",
2096 "qup-config",
2097 "qup-memory";
2098
2099 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2100 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
2101 dma-names = "tx",
2102 "rx";
2103
2104 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2105 pinctrl-names = "default";
2106
2107 #address-cells = <1>;
2108 #size-cells = <0>;
2109
2110 status = "disabled";
2111 };
2112
2113 i2c2: i2c@b88000 {
2114 compatible = "qcom,geni-i2c";
2115 reg = <0 0x00b88000 0 0x4000>;
2116
2117 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2118
2119 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2120 clock-names = "se";
2121
2122 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2123 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2124 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2125 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2126 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2128 interconnect-names = "qup-core",
2129 "qup-config",
2130 "qup-memory";
2131
2132 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2133 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
2134 dma-names = "tx",
2135 "rx";
2136
2137 pinctrl-0 = <&qup_i2c2_data_clk>;
2138 pinctrl-names = "default";
2139
2140 #address-cells = <1>;
2141 #size-cells = <0>;
2142
2143 status = "disabled";
2144 };
2145
2146 uart2: serial@b88000 {
2147 compatible = "qcom,geni-uart";
2148 reg = <0 0x00b88000 0 0x4000>;
2149
2150 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2151
2152 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2153 clock-names = "se";
2154
2155 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2156 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2158 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
2159 interconnect-names = "qup-core",
2160 "qup-config";
2161
2162 pinctrl-0 = <&qup_uart2_default>;
2163 pinctrl-names = "default";
2164
2165 status = "disabled";
2166 };
2167
2168 spi2: spi@b88000 {
2169 compatible = "qcom,geni-spi";
2170 reg = <0 0x00b88000 0 0x4000>;
2171
2172 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2173
2174 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2175 clock-names = "se";
2176
2177 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2178 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2179 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2180 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2181 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2182 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2183 interconnect-names = "qup-core",
2184 "qup-config",
2185 "qup-memory";
2186
2187 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2188 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
2189 dma-names = "tx",
2190 "rx";
2191
2192 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2193 pinctrl-names = "default";
2194
2195 #address-cells = <1>;
2196 #size-cells = <0>;
2197
2198 status = "disabled";
2199 };
2200
2201 i2c3: i2c@b8c000 {
2202 compatible = "qcom,geni-i2c";
2203 reg = <0 0x00b8c000 0 0x4000>;
2204
2205 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2206
2207 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2208 clock-names = "se";
2209
2210 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2211 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2212 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2213 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2214 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2215 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2216 interconnect-names = "qup-core",
2217 "qup-config",
2218 "qup-memory";
2219
2220 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2221 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
2222 dma-names = "tx",
2223 "rx";
2224
2225 pinctrl-0 = <&qup_i2c3_data_clk>;
2226 pinctrl-names = "default";
2227
2228 #address-cells = <1>;
2229 #size-cells = <0>;
2230
2231 status = "disabled";
2232 };
2233
2234 spi3: spi@b8c000 {
2235 compatible = "qcom,geni-spi";
2236 reg = <0 0x00b8c000 0 0x4000>;
2237
2238 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2239
2240 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2241 clock-names = "se";
2242
2243 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2244 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2246 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2247 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2249 interconnect-names = "qup-core",
2250 "qup-config",
2251 "qup-memory";
2252
2253 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2254 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
2255 dma-names = "tx",
2256 "rx";
2257
2258 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2259 pinctrl-names = "default";
2260
2261 #address-cells = <1>;
2262 #size-cells = <0>;
2263
2264 status = "disabled";
2265 };
2266
2267 i2c4: i2c@b90000 {
2268 compatible = "qcom,geni-i2c";
2269 reg = <0 0x00b90000 0 0x4000>;
2270
2271 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2272
2273 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2274 clock-names = "se";
2275
2276 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2277 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2279 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2280 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2282 interconnect-names = "qup-core",
2283 "qup-config",
2284 "qup-memory";
2285
2286 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2287 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
2288 dma-names = "tx",
2289 "rx";
2290
2291 pinctrl-0 = <&qup_i2c4_data_clk>;
2292 pinctrl-names = "default";
2293
2294 #address-cells = <1>;
2295 #size-cells = <0>;
2296
2297 status = "disabled";
2298 };
2299
2300 spi4: spi@b90000 {
2301 compatible = "qcom,geni-spi";
2302 reg = <0 0x00b90000 0 0x4000>;
2303
2304 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2305
2306 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2307 clock-names = "se";
2308
2309 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2310 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2311 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2312 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2313 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2315 interconnect-names = "qup-core",
2316 "qup-config",
2317 "qup-memory";
2318
2319 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2320 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2321 dma-names = "tx",
2322 "rx";
2323
2324 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2325 pinctrl-names = "default";
2326
2327 #address-cells = <1>;
2328 #size-cells = <0>;
2329
2330 status = "disabled";
2331 };
2332
2333 i2c5: i2c@b94000 {
2334 compatible = "qcom,geni-i2c";
2335 reg = <0 0x00b94000 0 0x4000>;
2336
2337 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2338
2339 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2340 clock-names = "se";
2341
2342 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2343 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2345 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2346 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2348 interconnect-names = "qup-core",
2349 "qup-config",
2350 "qup-memory";
2351
2352 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2353 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2354 dma-names = "tx",
2355 "rx";
2356
2357 pinctrl-0 = <&qup_i2c5_data_clk>;
2358 pinctrl-names = "default";
2359
2360 #address-cells = <1>;
2361 #size-cells = <0>;
2362
2363 status = "disabled";
2364 };
2365
2366 spi5: spi@b94000 {
2367 compatible = "qcom,geni-spi";
2368 reg = <0 0x00b94000 0 0x4000>;
2369
2370 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2371
2372 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2373 clock-names = "se";
2374
2375 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2376 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2377 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2378 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2379 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2381 interconnect-names = "qup-core",
2382 "qup-config",
2383 "qup-memory";
2384
2385 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2386 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2387 dma-names = "tx",
2388 "rx";
2389
2390 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2391 pinctrl-names = "default";
2392
2393 #address-cells = <1>;
2394 #size-cells = <0>;
2395
2396 status = "disabled";
2397 };
2398
2399 i2c6: i2c@b98000 {
2400 compatible = "qcom,geni-i2c";
2401 reg = <0 0x00b98000 0 0x4000>;
2402
2403 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2404
2405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2406 clock-names = "se";
2407
2408 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2409 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2410 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2411 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2412 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2413 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2414 interconnect-names = "qup-core",
2415 "qup-config",
2416 "qup-memory";
2417
2418 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2419 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
2420 dma-names = "tx",
2421 "rx";
2422
2423 pinctrl-0 = <&qup_i2c6_data_clk>;
2424 pinctrl-names = "default";
2425
2426 #address-cells = <1>;
2427 #size-cells = <0>;
2428
2429 status = "disabled";
2430 };
2431
2432 spi6: spi@b98000 {
2433 compatible = "qcom,geni-spi";
2434 reg = <0 0x00b98000 0 0x4000>;
2435
2436 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2437
2438 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2439 clock-names = "se";
2440
2441 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2442 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2443 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2444 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2445 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2446 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2447 interconnect-names = "qup-core",
2448 "qup-config",
2449 "qup-memory";
2450
2451 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2452 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
2453 dma-names = "tx",
2454 "rx";
2455
2456 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2457 pinctrl-names = "default";
2458
2459 #address-cells = <1>;
2460 #size-cells = <0>;
2461
2462 status = "disabled";
2463 };
2464
2465 i2c7: i2c@b9c000 {
2466 compatible = "qcom,geni-i2c";
2467 reg = <0 0x00b9c000 0 0x4000>;
2468
2469 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2470
2471 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2472 clock-names = "se";
2473
2474 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2475 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2476 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2477 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2478 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2479 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2480 interconnect-names = "qup-core",
2481 "qup-config",
2482 "qup-memory";
2483
2484 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2485 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
2486 dma-names = "tx",
2487 "rx";
2488
2489 pinctrl-0 = <&qup_i2c7_data_clk>;
2490 pinctrl-names = "default";
2491
2492 #address-cells = <1>;
2493 #size-cells = <0>;
2494
2495 status = "disabled";
2496 };
2497
2498 spi7: spi@b9c000 {
2499 compatible = "qcom,geni-spi";
2500 reg = <0 0x00b9c000 0 0x4000>;
2501
2502 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2503
2504 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2505 clock-names = "se";
2506
2507 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2508 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2509 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2510 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2511 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2512 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2513 interconnect-names = "qup-core",
2514 "qup-config",
2515 "qup-memory";
2516
2517 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2518 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
2519 dma-names = "tx",
2520 "rx";
2521
2522 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2523 pinctrl-names = "default";
2524
2525 #address-cells = <1>;
2526 #size-cells = <0>;
2527
2528 status = "disabled";
2529 };
2530 };
2531
2532 tsens0: thermal-sensor@c271000 {
2533 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2534 reg = <0 0x0c271000 0 0x1000>,
2535 <0 0x0c222000 0 0x1000>;
2536
2537 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2538 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
2539 interrupt-names = "uplow",
2540 "critical";
2541
2542 #qcom,sensors = <16>;
2543
2544 #thermal-sensor-cells = <1>;
2545 };
2546
2547 tsens1: thermal-sensor@c272000 {
2548 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2549 reg = <0 0x0c272000 0 0x1000>,
2550 <0 0x0c223000 0 0x1000>;
2551
2552 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2553 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
2554 interrupt-names = "uplow",
2555 "critical";
2556
2557 #qcom,sensors = <16>;
2558
2559 #thermal-sensor-cells = <1>;
2560 };
2561
2562 tsens2: thermal-sensor@c273000 {
2563 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2564 reg = <0 0x0c273000 0 0x1000>,
2565 <0 0x0c224000 0 0x1000>;
2566
2567 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2568 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
2569 interrupt-names = "uplow",
2570 "critical";
2571
2572 #qcom,sensors = <16>;
2573
2574 #thermal-sensor-cells = <1>;
2575 };
2576
2577 tsens3: thermal-sensor@c274000 {
2578 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2579 reg = <0 0x0c274000 0 0x1000>,
2580 <0 0x0c225000 0 0x1000>;
2581
2582 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2583 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
2584 interrupt-names = "uplow",
2585 "critical";
2586
2587 #qcom,sensors = <16>;
2588
2589 #thermal-sensor-cells = <1>;
2590 };
2591
2592 usb_1_ss0_hsphy: phy@fd3000 {
2593 compatible = "qcom,x1e80100-snps-eusb2-phy",
2594 "qcom,sm8550-snps-eusb2-phy";
2595 reg = <0 0x00fd3000 0 0x154>;
2596 #phy-cells = <0>;
2597
2598 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2599 clock-names = "ref";
2600
2601 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2602
2603 status = "disabled";
2604 };
2605
2606 usb_1_ss0_qmpphy: phy@fd5000 {
2607 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2608 reg = <0 0x00fd5000 0 0x4000>;
2609
2610 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2611 <&rpmhcc RPMH_CXO_CLK>,
2612 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2613 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2614 clock-names = "aux",
2615 "ref",
2616 "com_aux",
2617 "usb3_pipe";
2618
2619 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2620
2621 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2622 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
2623 reset-names = "phy",
2624 "common";
2625
2626 #clock-cells = <1>;
2627 #phy-cells = <1>;
2628
2629 orientation-switch;
2630
2631 status = "disabled";
2632
2633 ports {
2634 #address-cells = <1>;
2635 #size-cells = <0>;
2636
2637 port@0 {
2638 reg = <0>;
2639
2640 usb_1_ss0_qmpphy_out: endpoint {
2641 };
2642 };
2643
2644 port@1 {
2645 reg = <1>;
2646
2647 usb_1_ss0_qmpphy_usb_ss_in: endpoint {
2648 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2649 };
2650 };
2651
2652 port@2 {
2653 reg = <2>;
2654
2655 usb_1_ss0_qmpphy_dp_in: endpoint {
2656 remote-endpoint = <&mdss_dp0_out>;
2657 };
2658 };
2659 };
2660 };
2661
2662 usb_1_ss1_hsphy: phy@fd9000 {
2663 compatible = "qcom,x1e80100-snps-eusb2-phy",
2664 "qcom,sm8550-snps-eusb2-phy";
2665 reg = <0 0x00fd9000 0 0x154>;
2666 #phy-cells = <0>;
2667
2668 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2669 clock-names = "ref";
2670
2671 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2672
2673 status = "disabled";
2674 };
2675
2676 usb_1_ss1_qmpphy: phy@fda000 {
2677 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2678 reg = <0 0x00fda000 0 0x4000>;
2679
2680 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2681 <&rpmhcc RPMH_CXO_CLK>,
2682 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2683 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2684 clock-names = "aux",
2685 "ref",
2686 "com_aux",
2687 "usb3_pipe";
2688
2689 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2690
2691 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2692 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
2693 reset-names = "phy",
2694 "common";
2695
2696 #clock-cells = <1>;
2697 #phy-cells = <1>;
2698
2699 orientation-switch;
2700
2701 status = "disabled";
2702
2703 ports {
2704 #address-cells = <1>;
2705 #size-cells = <0>;
2706
2707 port@0 {
2708 reg = <0>;
2709
2710 usb_1_ss1_qmpphy_out: endpoint {
2711 };
2712 };
2713
2714 port@1 {
2715 reg = <1>;
2716
2717 usb_1_ss1_qmpphy_usb_ss_in: endpoint {
2718 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2719 };
2720 };
2721
2722 port@2 {
2723 reg = <2>;
2724
2725 usb_1_ss1_qmpphy_dp_in: endpoint {
2726 remote-endpoint = <&mdss_dp1_out>;
2727 };
2728 };
2729 };
2730 };
2731
2732 usb_1_ss2_hsphy: phy@fde000 {
2733 compatible = "qcom,x1e80100-snps-eusb2-phy",
2734 "qcom,sm8550-snps-eusb2-phy";
2735 reg = <0 0x00fde000 0 0x154>;
2736 #phy-cells = <0>;
2737
2738 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2739 clock-names = "ref";
2740
2741 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
2742
2743 status = "disabled";
2744 };
2745
2746 usb_1_ss2_qmpphy: phy@fdf000 {
2747 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2748 reg = <0 0x00fdf000 0 0x4000>;
2749
2750 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
2751 <&rpmhcc RPMH_CXO_CLK>,
2752 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
2753 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
2754 clock-names = "aux",
2755 "ref",
2756 "com_aux",
2757 "usb3_pipe";
2758
2759 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2760
2761 resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
2762 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
2763 reset-names = "phy",
2764 "common";
2765
2766 #clock-cells = <1>;
2767 #phy-cells = <1>;
2768
2769 orientation-switch;
2770
2771 status = "disabled";
2772
2773 ports {
2774 #address-cells = <1>;
2775 #size-cells = <0>;
2776
2777 port@0 {
2778 reg = <0>;
2779
2780 usb_1_ss2_qmpphy_out: endpoint {
2781 };
2782 };
2783
2784 port@1 {
2785 reg = <1>;
2786
2787 usb_1_ss2_qmpphy_usb_ss_in: endpoint {
2788 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
2789 };
2790 };
2791
2792 port@2 {
2793 reg = <2>;
2794
2795 usb_1_ss2_qmpphy_dp_in: endpoint {
2796 remote-endpoint = <&mdss_dp2_out>;
2797 };
2798 };
2799 };
2800 };
2801
2802 cnoc_main: interconnect@1500000 {
2803 compatible = "qcom,x1e80100-cnoc-main";
2804 reg = <0 0x01500000 0 0x14400>;
2805
2806 qcom,bcm-voters = <&apps_bcm_voter>;
2807
2808 #interconnect-cells = <2>;
2809 };
2810
2811 config_noc: interconnect@1600000 {
2812 compatible = "qcom,x1e80100-cnoc-cfg";
2813 reg = <0 0x01600000 0 0x6600>;
2814
2815 qcom,bcm-voters = <&apps_bcm_voter>;
2816
2817 #interconnect-cells = <2>;
2818 };
2819
2820 system_noc: interconnect@1680000 {
2821 compatible = "qcom,x1e80100-system-noc";
2822 reg = <0 0x01680000 0 0x1c080>;
2823
2824 qcom,bcm-voters = <&apps_bcm_voter>;
2825
2826 #interconnect-cells = <2>;
2827 };
2828
2829 pcie_south_anoc: interconnect@16c0000 {
2830 compatible = "qcom,x1e80100-pcie-south-anoc";
2831 reg = <0 0x016c0000 0 0xd080>;
2832
2833 qcom,bcm-voters = <&apps_bcm_voter>;
2834
2835 #interconnect-cells = <2>;
2836 };
2837
2838 pcie_center_anoc: interconnect@16d0000 {
2839 compatible = "qcom,x1e80100-pcie-center-anoc";
2840 reg = <0 0x016d0000 0 0x7000>;
2841
2842 qcom,bcm-voters = <&apps_bcm_voter>;
2843
2844 #interconnect-cells = <2>;
2845 };
2846
2847 aggre1_noc: interconnect@16e0000 {
2848 compatible = "qcom,x1e80100-aggre1-noc";
2849 reg = <0 0x016e0000 0 0x14400>;
2850
2851 qcom,bcm-voters = <&apps_bcm_voter>;
2852
2853 #interconnect-cells = <2>;
2854 };
2855
2856 aggre2_noc: interconnect@1700000 {
2857 compatible = "qcom,x1e80100-aggre2-noc";
2858 reg = <0 0x01700000 0 0x1c400>;
2859
2860 qcom,bcm-voters = <&apps_bcm_voter>;
2861
2862 #interconnect-cells = <2>;
2863 };
2864
2865 pcie_north_anoc: interconnect@1740000 {
2866 compatible = "qcom,x1e80100-pcie-north-anoc";
2867 reg = <0 0x01740000 0 0x9080>;
2868
2869 qcom,bcm-voters = <&apps_bcm_voter>;
2870
2871 #interconnect-cells = <2>;
2872 };
2873
2874 usb_center_anoc: interconnect@1750000 {
2875 compatible = "qcom,x1e80100-usb-center-anoc";
2876 reg = <0 0x01750000 0 0x8800>;
2877
2878 qcom,bcm-voters = <&apps_bcm_voter>;
2879
2880 #interconnect-cells = <2>;
2881 };
2882
2883 usb_north_anoc: interconnect@1760000 {
2884 compatible = "qcom,x1e80100-usb-north-anoc";
2885 reg = <0 0x01760000 0 0x7080>;
2886
2887 qcom,bcm-voters = <&apps_bcm_voter>;
2888
2889 #interconnect-cells = <2>;
2890 };
2891
2892 usb_south_anoc: interconnect@1770000 {
2893 compatible = "qcom,x1e80100-usb-south-anoc";
2894 reg = <0 0x01770000 0 0xf080>;
2895
2896 qcom,bcm-voters = <&apps_bcm_voter>;
2897
2898 #interconnect-cells = <2>;
2899 };
2900
2901 mmss_noc: interconnect@1780000 {
2902 compatible = "qcom,x1e80100-mmss-noc";
2903 reg = <0 0x01780000 0 0x5B800>;
2904
2905 qcom,bcm-voters = <&apps_bcm_voter>;
2906
2907 #interconnect-cells = <2>;
2908 };
2909
2910 pcie6a: pci@1bf8000 {
2911 device_type = "pci";
2912 compatible = "qcom,pcie-x1e80100";
2913 reg = <0 0x01bf8000 0 0x3000>,
2914 <0 0x70000000 0 0xf20>,
2915 <0 0x70000f40 0 0xa8>,
2916 <0 0x70001000 0 0x1000>,
2917 <0 0x70100000 0 0x100000>,
2918 <0 0x01bfb000 0 0x1000>;
2919 reg-names = "parf",
2920 "dbi",
2921 "elbi",
2922 "atu",
2923 "config",
2924 "mhi";
2925 #address-cells = <3>;
2926 #size-cells = <2>;
2927 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
2928 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>;
2929 bus-range = <0x00 0xff>;
2930
2931 dma-coherent;
2932
2933 linux,pci-domain = <6>;
2934 num-lanes = <4>;
2935
2936 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
2939 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
2940 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
2941 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
2942 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
2943 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
2944 interrupt-names = "msi0",
2945 "msi1",
2946 "msi2",
2947 "msi3",
2948 "msi4",
2949 "msi5",
2950 "msi6",
2951 "msi7";
2952
2953 #interrupt-cells = <1>;
2954 interrupt-map-mask = <0 0 0 0x7>;
2955 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2956 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
2957 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
2958 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
2959
2960 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
2961 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
2962 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
2963 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
2964 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
2965 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
2966 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
2967 clock-names = "aux",
2968 "cfg",
2969 "bus_master",
2970 "bus_slave",
2971 "slave_q2a",
2972 "noc_aggr",
2973 "cnoc_sf_axi";
2974
2975 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
2976 assigned-clock-rates = <19200000>;
2977
2978 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
2979 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2980 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2981 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
2982 interconnect-names = "pcie-mem",
2983 "cpu-pcie";
2984
2985 resets = <&gcc GCC_PCIE_6A_BCR>,
2986 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
2987 reset-names = "pci",
2988 "link_down";
2989
2990 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
2991 required-opps = <&rpmhpd_opp_nom>;
2992
2993 phys = <&pcie6a_phy>;
2994 phy-names = "pciephy";
2995
2996 status = "disabled";
2997 };
2998
2999 pcie6a_phy: phy@1bfc000 {
3000 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3001 reg = <0 0x01bfc000 0 0x2000>,
3002 <0 0x01bfe000 0 0x2000>;
3003
3004 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
3005 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3006 <&tcsr TCSR_PCIE_4L_CLKREF_EN>,
3007 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
3008 <&gcc GCC_PCIE_6A_PIPE_CLK>,
3009 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
3010 clock-names = "aux",
3011 "cfg_ahb",
3012 "ref",
3013 "rchng",
3014 "pipe",
3015 "pipediv2";
3016
3017 resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
3018 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
3019 reset-names = "phy",
3020 "phy_nocsr";
3021
3022 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3023 assigned-clock-rates = <100000000>;
3024
3025 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3026
3027 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3028
3029 #clock-cells = <0>;
3030 clock-output-names = "pcie6a_pipe_clk";
3031
3032 #phy-cells = <0>;
3033
3034 status = "disabled";
3035 };
3036
3037 pcie5: pci@1c00000 {
3038 device_type = "pci";
3039 compatible = "qcom,pcie-x1e80100";
3040 reg = <0 0x01c00000 0 0x3000>,
3041 <0 0x7e000000 0 0xf1d>,
3042 <0 0x7e000f40 0 0xa8>,
3043 <0 0x7e001000 0 0x1000>,
3044 <0 0x7e100000 0 0x100000>,
3045 <0 0x01c03000 0 0x1000>;
3046 reg-names = "parf",
3047 "dbi",
3048 "elbi",
3049 "atu",
3050 "config",
3051 "mhi";
3052 #address-cells = <3>;
3053 #size-cells = <2>;
3054 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
3055 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
3056 bus-range = <0x00 0xff>;
3057
3058 dma-coherent;
3059
3060 linux,pci-domain = <5>;
3061 num-lanes = <2>;
3062
3063 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3064 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3065 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3066 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3067 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3068 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
3070 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
3071 interrupt-names = "msi0",
3072 "msi1",
3073 "msi2",
3074 "msi3",
3075 "msi4",
3076 "msi5",
3077 "msi6",
3078 "msi7";
3079
3080 #interrupt-cells = <1>;
3081 interrupt-map-mask = <0 0 0 0x7>;
3082 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3083 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
3084 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
3085 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
3086
3087 clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3088 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3089 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
3090 <&gcc GCC_PCIE_5_SLV_AXI_CLK>,
3091 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
3092 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3093 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3094 clock-names = "aux",
3095 "cfg",
3096 "bus_master",
3097 "bus_slave",
3098 "slave_q2a",
3099 "noc_aggr",
3100 "cnoc_sf_axi";
3101
3102 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3103 assigned-clock-rates = <19200000>;
3104
3105 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
3106 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3107 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3108 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>;
3109 interconnect-names = "pcie-mem",
3110 "cpu-pcie";
3111
3112 resets = <&gcc GCC_PCIE_5_BCR>,
3113 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
3114 reset-names = "pci",
3115 "link_down";
3116
3117 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3118 required-opps = <&rpmhpd_opp_nom>;
3119
3120 phys = <&pcie5_phy>;
3121 phy-names = "pciephy";
3122
3123 status = "disabled";
3124 };
3125
3126 pcie5_phy: phy@1c06000 {
3127 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3128 reg = <0 0x01c06000 0 0x2000>;
3129
3130 clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3131 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3132 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>,
3133 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
3134 <&gcc GCC_PCIE_5_PIPE_CLK>,
3135 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>;
3136 clock-names = "aux",
3137 "cfg_ahb",
3138 "ref",
3139 "rchng",
3140 "pipe",
3141 "pipediv2";
3142
3143 resets = <&gcc GCC_PCIE_5_PHY_BCR>;
3144 reset-names = "phy";
3145
3146 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3147 assigned-clock-rates = <100000000>;
3148
3149 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3150
3151 #clock-cells = <0>;
3152 clock-output-names = "pcie5_pipe_clk";
3153
3154 #phy-cells = <0>;
3155
3156 status = "disabled";
3157 };
3158
3159 pcie4: pci@1c08000 {
3160 device_type = "pci";
3161 compatible = "qcom,pcie-x1e80100";
3162 reg = <0 0x01c08000 0 0x3000>,
3163 <0 0x7c000000 0 0xf1d>,
3164 <0 0x7c000f40 0 0xa8>,
3165 <0 0x7c001000 0 0x1000>,
3166 <0 0x7c100000 0 0x100000>,
3167 <0 0x01c0b000 0 0x1000>;
3168 reg-names = "parf",
3169 "dbi",
3170 "elbi",
3171 "atu",
3172 "config",
3173 "mhi";
3174 #address-cells = <3>;
3175 #size-cells = <2>;
3176 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3177 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3178 bus-range = <0x00 0xff>;
3179
3180 dma-coherent;
3181
3182 linux,pci-domain = <4>;
3183 num-lanes = <2>;
3184
3185 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3186 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
3187 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
3188 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
3189 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
3190 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
3192 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
3193 interrupt-names = "msi0",
3194 "msi1",
3195 "msi2",
3196 "msi3",
3197 "msi4",
3198 "msi5",
3199 "msi6",
3200 "msi7";
3201
3202 #interrupt-cells = <1>;
3203 interrupt-map-mask = <0 0 0 0x7>;
3204 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3205 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3206 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3207 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3208
3209 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3210 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3211 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
3212 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
3213 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
3214 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3215 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3216 clock-names = "aux",
3217 "cfg",
3218 "bus_master",
3219 "bus_slave",
3220 "slave_q2a",
3221 "noc_aggr",
3222 "cnoc_sf_axi";
3223
3224 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3225 assigned-clock-rates = <19200000>;
3226
3227 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
3228 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3229 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3230 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
3231 interconnect-names = "pcie-mem",
3232 "cpu-pcie";
3233
3234 resets = <&gcc GCC_PCIE_4_BCR>,
3235 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
3236 reset-names = "pci",
3237 "link_down";
3238
3239 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3240 required-opps = <&rpmhpd_opp_nom>;
3241
3242 phys = <&pcie4_phy>;
3243 phy-names = "pciephy";
3244
3245 status = "disabled";
3246
3247 pcie4_port0: pcie@0 {
3248 device_type = "pci";
3249 reg = <0x0 0x0 0x0 0x0 0x0>;
3250 bus-range = <0x01 0xff>;
3251
3252 #address-cells = <3>;
3253 #size-cells = <2>;
3254 ranges;
3255 };
3256 };
3257
3258 pcie4_phy: phy@1c0e000 {
3259 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3260 reg = <0 0x01c0e000 0 0x2000>;
3261
3262 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3263 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3264 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>,
3265 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
3266 <&gcc GCC_PCIE_4_PIPE_CLK>,
3267 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
3268 clock-names = "aux",
3269 "cfg_ahb",
3270 "ref",
3271 "rchng",
3272 "pipe",
3273 "pipediv2";
3274
3275 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
3276 reset-names = "phy";
3277
3278 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3279 assigned-clock-rates = <100000000>;
3280
3281 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3282
3283 #clock-cells = <0>;
3284 clock-output-names = "pcie4_pipe_clk";
3285
3286 #phy-cells = <0>;
3287
3288 status = "disabled";
3289 };
3290
3291 tcsr_mutex: hwlock@1f40000 {
3292 compatible = "qcom,tcsr-mutex";
3293 reg = <0 0x01f40000 0 0x20000>;
3294 #hwlock-cells = <1>;
3295 };
3296
3297 tcsr: clock-controller@1fc0000 {
3298 compatible = "qcom,x1e80100-tcsr", "syscon";
3299 reg = <0 0x01fc0000 0 0x30000>;
3300 clocks = <&rpmhcc RPMH_CXO_CLK>;
3301 #clock-cells = <1>;
3302 #reset-cells = <1>;
3303 };
3304
3305 gpu: gpu@3d00000 {
3306 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3307 reg = <0x0 0x03d00000 0x0 0x40000>,
3308 <0x0 0x03d9e000 0x0 0x1000>,
3309 <0x0 0x03d61000 0x0 0x800>;
3310
3311 reg-names = "kgsl_3d0_reg_memory",
3312 "cx_mem",
3313 "cx_dbgc";
3314
3315 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3316
3317 iommus = <&adreno_smmu 0 0x0>,
3318 <&adreno_smmu 1 0x0>;
3319
3320 operating-points-v2 = <&gpu_opp_table>;
3321
3322 qcom,gmu = <&gmu>;
3323 #cooling-cells = <2>;
3324
3325 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3326 interconnect-names = "gfx-mem";
3327
3328 status = "disabled";
3329
3330 zap-shader {
3331 memory-region = <&gpu_microcode_mem>;
3332 };
3333
3334 gpu_opp_table: opp-table {
3335 compatible = "operating-points-v2";
3336
3337 opp-1100000000 {
3338 opp-hz = /bits/ 64 <1100000000>;
3339 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3340 opp-peak-kBps = <16500000>;
3341 };
3342
3343 opp-1000000000 {
3344 opp-hz = /bits/ 64 <1000000000>;
3345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3346 opp-peak-kBps = <14398438>;
3347 };
3348
3349 opp-925000000 {
3350 opp-hz = /bits/ 64 <925000000>;
3351 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3352 opp-peak-kBps = <14398438>;
3353 };
3354
3355 opp-800000000 {
3356 opp-hz = /bits/ 64 <800000000>;
3357 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3358 opp-peak-kBps = <12449219>;
3359 };
3360
3361 opp-744000000 {
3362 opp-hz = /bits/ 64 <744000000>;
3363 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3364 opp-peak-kBps = <10687500>;
3365 };
3366
3367 opp-687000000 {
3368 opp-hz = /bits/ 64 <687000000>;
3369 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3370 opp-peak-kBps = <8171875>;
3371 };
3372
3373 opp-550000000 {
3374 opp-hz = /bits/ 64 <550000000>;
3375 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3376 opp-peak-kBps = <6074219>;
3377 };
3378
3379 opp-390000000 {
3380 opp-hz = /bits/ 64 <390000000>;
3381 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3382 opp-peak-kBps = <3000000>;
3383 };
3384
3385 opp-300000000 {
3386 opp-hz = /bits/ 64 <300000000>;
3387 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3388 opp-peak-kBps = <2136719>;
3389 };
3390 };
3391 };
3392
3393 gmu: gmu@3d6a000 {
3394 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3395 reg = <0x0 0x03d6a000 0x0 0x35000>,
3396 <0x0 0x03d50000 0x0 0x10000>,
3397 <0x0 0x0b280000 0x0 0x10000>;
3398 reg-names = "gmu", "rscc", "gmu_pdc";
3399
3400 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3401 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3402 interrupt-names = "hfi", "gmu";
3403
3404 clocks = <&gpucc GPU_CC_AHB_CLK>,
3405 <&gpucc GPU_CC_CX_GMU_CLK>,
3406 <&gpucc GPU_CC_CXO_CLK>,
3407 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3408 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3409 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
3410 <&gpucc GPU_CC_DEMET_CLK>;
3411 clock-names = "ahb",
3412 "gmu",
3413 "cxo",
3414 "axi",
3415 "memnoc",
3416 "hub",
3417 "demet";
3418
3419 power-domains = <&gpucc GPU_CX_GDSC>,
3420 <&gpucc GPU_GX_GDSC>;
3421 power-domain-names = "cx",
3422 "gx";
3423
3424 iommus = <&adreno_smmu 5 0x0>;
3425
3426 qcom,qmp = <&aoss_qmp>;
3427
3428 operating-points-v2 = <&gmu_opp_table>;
3429
3430 gmu_opp_table: opp-table {
3431 compatible = "operating-points-v2";
3432
3433 opp-550000000 {
3434 opp-hz = /bits/ 64 <550000000>;
3435 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3436 };
3437
3438 opp-220000000 {
3439 opp-hz = /bits/ 64 <220000000>;
3440 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3441 };
3442 };
3443 };
3444
3445 gpucc: clock-controller@3d90000 {
3446 compatible = "qcom,x1e80100-gpucc";
3447 reg = <0 0x03d90000 0 0xa000>;
3448 clocks = <&bi_tcxo_div2>,
3449 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
3450 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
3451 #clock-cells = <1>;
3452 #reset-cells = <1>;
3453 #power-domain-cells = <1>;
3454 };
3455
3456 adreno_smmu: iommu@3da0000 {
3457 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3458 "qcom,smmu-500", "arm,mmu-500";
3459 reg = <0x0 0x03da0000 0x0 0x40000>;
3460 #iommu-cells = <2>;
3461 #global-interrupts = <1>;
3462 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
3463 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3464 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3465 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3466 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3467 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3469 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3470 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
3471 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
3472 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
3474 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3475 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
3476 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
3477 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
3488 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
3489 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3490 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3491 <&gpucc GPU_CC_AHB_CLK>;
3492 clock-names = "hlos",
3493 "bus",
3494 "iface",
3495 "ahb";
3496 power-domains = <&gpucc GPU_CX_GDSC>;
3497 dma-coherent;
3498 };
3499
3500 gem_noc: interconnect@26400000 {
3501 compatible = "qcom,x1e80100-gem-noc";
3502 reg = <0 0x26400000 0 0x311200>;
3503
3504 qcom,bcm-voters = <&apps_bcm_voter>;
3505
3506 #interconnect-cells = <2>;
3507 };
3508
3509 nsp_noc: interconnect@320c0000 {
3510 compatible = "qcom,x1e80100-nsp-noc";
3511 reg = <0 0x320C0000 0 0xe080>;
3512
3513 qcom,bcm-voters = <&apps_bcm_voter>;
3514
3515 #interconnect-cells = <2>;
3516 };
3517
3518 lpass_wsa2macro: codec@6aa0000 {
3519 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3520 reg = <0 0x06aa0000 0 0x1000>;
3521 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3522 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3523 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3524 <&lpass_vamacro>;
3525 clock-names = "mclk",
3526 "macro",
3527 "dcodec",
3528 "fsgen";
3529
3530 #clock-cells = <0>;
3531 clock-output-names = "wsa2-mclk";
3532 #sound-dai-cells = <1>;
3533 sound-name-prefix = "WSA2";
3534 };
3535
3536 swr3: soundwire@6ab0000 {
3537 compatible = "qcom,soundwire-v2.0.0";
3538 reg = <0 0x06ab0000 0 0x10000>;
3539 clocks = <&lpass_wsa2macro>;
3540 clock-names = "iface";
3541 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
3542 label = "WSA2";
3543
3544 pinctrl-0 = <&wsa2_swr_active>;
3545 pinctrl-names = "default";
3546 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>;
3547 reset-names = "swr_audio_cgcr";
3548
3549 qcom,din-ports = <4>;
3550 qcom,dout-ports = <9>;
3551
3552 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3553 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3554 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3555 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3556 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3557 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3558 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3559 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3560 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3561
3562 #address-cells = <2>;
3563 #size-cells = <0>;
3564 #sound-dai-cells = <1>;
3565 status = "disabled";
3566 };
3567
3568 lpass_rxmacro: codec@6ac0000 {
3569 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3570 reg = <0 0x06ac0000 0 0x1000>;
3571 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3572 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3573 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3574 <&lpass_vamacro>;
3575 clock-names = "mclk",
3576 "macro",
3577 "dcodec",
3578 "fsgen";
3579
3580 #clock-cells = <0>;
3581 clock-output-names = "mclk";
3582 #sound-dai-cells = <1>;
3583 };
3584
3585 swr1: soundwire@6ad0000 {
3586 compatible = "qcom,soundwire-v2.0.0";
3587 reg = <0 0x06ad0000 0 0x10000>;
3588 clocks = <&lpass_rxmacro>;
3589 clock-names = "iface";
3590 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
3591 label = "RX";
3592
3593 pinctrl-0 = <&rx_swr_active>;
3594 pinctrl-names = "default";
3595
3596 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
3597 reset-names = "swr_audio_cgcr";
3598 qcom,din-ports = <1>;
3599 qcom,dout-ports = <11>;
3600
3601 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3602 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3603 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3604 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3608 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3609 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3610
3611 #address-cells = <2>;
3612 #size-cells = <0>;
3613 #sound-dai-cells = <1>;
3614 status = "disabled";
3615 };
3616
3617 lpass_txmacro: codec@6ae0000 {
3618 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3619 reg = <0 0x06ae0000 0 0x1000>;
3620 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3621 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3622 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3623 <&lpass_vamacro>;
3624 clock-names = "mclk",
3625 "macro",
3626 "dcodec",
3627 "fsgen";
3628
3629 #clock-cells = <0>;
3630 clock-output-names = "mclk";
3631 #sound-dai-cells = <1>;
3632 };
3633
3634 lpass_wsamacro: codec@6b00000 {
3635 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3636 reg = <0 0x06b00000 0 0x1000>;
3637 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3638 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3639 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3640 <&lpass_vamacro>;
3641 clock-names = "mclk",
3642 "macro",
3643 "dcodec",
3644 "fsgen";
3645
3646 #clock-cells = <0>;
3647 clock-output-names = "mclk";
3648 #sound-dai-cells = <1>;
3649 sound-name-prefix = "WSA";
3650 };
3651
3652 swr0: soundwire@6b10000 {
3653 compatible = "qcom,soundwire-v2.0.0";
3654 reg = <0 0x06b10000 0 0x10000>;
3655 clocks = <&lpass_wsamacro>;
3656 clock-names = "iface";
3657 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
3658 label = "WSA";
3659
3660 pinctrl-0 = <&wsa_swr_active>;
3661 pinctrl-names = "default";
3662 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
3663 reset-names = "swr_audio_cgcr";
3664
3665 qcom,din-ports = <4>;
3666 qcom,dout-ports = <9>;
3667
3668 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3669 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3670 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3671 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3672 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3673 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3674 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3675 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3676 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3677
3678 #address-cells = <2>;
3679 #size-cells = <0>;
3680 #sound-dai-cells = <1>;
3681 status = "disabled";
3682 };
3683
3684 lpass_audiocc: clock-controller@6b6c000 {
3685 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
3686 reg = <0 0x06b6c000 0 0x1000>;
3687 #clock-cells = <1>;
3688 #reset-cells = <1>;
3689 };
3690
3691 swr2: soundwire@6d30000 {
3692 compatible = "qcom,soundwire-v2.0.0";
3693 reg = <0 0x06d30000 0 0x10000>;
3694 clocks = <&lpass_txmacro>;
3695 clock-names = "iface";
3696 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
3697 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
3698 interrupt-names = "core", "wakeup";
3699 label = "TX";
3700 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
3701 reset-names = "swr_audio_cgcr";
3702
3703 pinctrl-0 = <&tx_swr_active>;
3704 pinctrl-names = "default";
3705
3706 qcom,din-ports = <4>;
3707 qcom,dout-ports = <1>;
3708
3709 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3710 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3711 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3712 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3713 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3714 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3715 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3718
3719 #address-cells = <2>;
3720 #size-cells = <0>;
3721 #sound-dai-cells = <1>;
3722 status = "disabled";
3723 };
3724
3725 lpass_vamacro: codec@6d44000 {
3726 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3727 reg = <0 0x06d44000 0 0x1000>;
3728 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3729 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3730 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3731 clock-names = "mclk",
3732 "macro",
3733 "dcodec";
3734
3735 #clock-cells = <0>;
3736 clock-output-names = "fsgen";
3737 #sound-dai-cells = <1>;
3738 };
3739
3740 lpass_tlmm: pinctrl@6e80000 {
3741 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
3742 reg = <0 0x06e80000 0 0x20000>,
3743 <0 0x07250000 0 0x10000>;
3744
3745 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3746 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3747 clock-names = "core", "audio";
3748
3749 gpio-controller;
3750 #gpio-cells = <2>;
3751 gpio-ranges = <&lpass_tlmm 0 0 23>;
3752
3753 tx_swr_active: tx-swr-active-state {
3754 clk-pins {
3755 pins = "gpio0";
3756 function = "swr_tx_clk";
3757 drive-strength = <2>;
3758 slew-rate = <1>;
3759 bias-disable;
3760 };
3761
3762 data-pins {
3763 pins = "gpio1", "gpio2";
3764 function = "swr_tx_data";
3765 drive-strength = <2>;
3766 slew-rate = <1>;
3767 bias-bus-hold;
3768 };
3769 };
3770
3771 rx_swr_active: rx-swr-active-state {
3772 clk-pins {
3773 pins = "gpio3";
3774 function = "swr_rx_clk";
3775 drive-strength = <2>;
3776 slew-rate = <1>;
3777 bias-disable;
3778 };
3779
3780 data-pins {
3781 pins = "gpio4", "gpio5";
3782 function = "swr_rx_data";
3783 drive-strength = <2>;
3784 slew-rate = <1>;
3785 bias-bus-hold;
3786 };
3787 };
3788
3789 dmic01_default: dmic01-default-state {
3790 clk-pins {
3791 pins = "gpio6";
3792 function = "dmic1_clk";
3793 drive-strength = <8>;
3794 output-high;
3795 };
3796
3797 data-pins {
3798 pins = "gpio7";
3799 function = "dmic1_data";
3800 drive-strength = <8>;
3801 input-enable;
3802 };
3803 };
3804
3805 dmic23_default: dmic23-default-state {
3806 clk-pins {
3807 pins = "gpio8";
3808 function = "dmic2_clk";
3809 drive-strength = <8>;
3810 output-high;
3811 };
3812
3813 data-pins {
3814 pins = "gpio9";
3815 function = "dmic2_data";
3816 drive-strength = <8>;
3817 input-enable;
3818 };
3819 };
3820
3821 wsa_swr_active: wsa-swr-active-state {
3822 clk-pins {
3823 pins = "gpio10";
3824 function = "wsa_swr_clk";
3825 drive-strength = <2>;
3826 slew-rate = <1>;
3827 bias-disable;
3828 };
3829
3830 data-pins {
3831 pins = "gpio11";
3832 function = "wsa_swr_data";
3833 drive-strength = <2>;
3834 slew-rate = <1>;
3835 bias-bus-hold;
3836 };
3837 };
3838
3839 wsa2_swr_active: wsa2-swr-active-state {
3840 clk-pins {
3841 pins = "gpio15";
3842 function = "wsa2_swr_clk";
3843 drive-strength = <2>;
3844 slew-rate = <1>;
3845 bias-disable;
3846 };
3847
3848 data-pins {
3849 pins = "gpio16";
3850 function = "wsa2_swr_data";
3851 drive-strength = <2>;
3852 slew-rate = <1>;
3853 bias-bus-hold;
3854 };
3855 };
3856 };
3857
3858 lpasscc: clock-controller@6ea0000 {
3859 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
3860 reg = <0 0x06ea0000 0 0x12000>;
3861 #clock-cells = <1>;
3862 #reset-cells = <1>;
3863 };
3864
3865 lpass_ag_noc: interconnect@7e40000 {
3866 compatible = "qcom,x1e80100-lpass-ag-noc";
3867 reg = <0 0x07e40000 0 0xe080>;
3868
3869 qcom,bcm-voters = <&apps_bcm_voter>;
3870
3871 #interconnect-cells = <2>;
3872 };
3873
3874 lpass_lpiaon_noc: interconnect@7400000 {
3875 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3876 reg = <0 0x07400000 0 0x19080>;
3877
3878 qcom,bcm-voters = <&apps_bcm_voter>;
3879
3880 #interconnect-cells = <2>;
3881 };
3882
3883 lpass_lpicx_noc: interconnect@7430000 {
3884 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3885 reg = <0 0x07430000 0 0x3A200>;
3886
3887 qcom,bcm-voters = <&apps_bcm_voter>;
3888
3889 #interconnect-cells = <2>;
3890 };
3891
3892 usb_2_hsphy: phy@88e0000 {
3893 compatible = "qcom,x1e80100-snps-eusb2-phy",
3894 "qcom,sm8550-snps-eusb2-phy";
3895 reg = <0 0x088e0000 0 0x154>;
3896 #phy-cells = <0>;
3897
3898 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
3899 clock-names = "ref";
3900
3901 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
3902
3903 status = "disabled";
3904 };
3905
3906 usb_mp_hsphy0: phy@88e1000 {
3907 compatible = "qcom,x1e80100-snps-eusb2-phy",
3908 "qcom,sm8550-snps-eusb2-phy";
3909 reg = <0 0x088e1000 0 0x154>;
3910 #phy-cells = <0>;
3911
3912 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>;
3913 clock-names = "ref";
3914
3915 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
3916
3917 status = "disabled";
3918 };
3919
3920 usb_mp_hsphy1: phy@88e2000 {
3921 compatible = "qcom,x1e80100-snps-eusb2-phy",
3922 "qcom,sm8550-snps-eusb2-phy";
3923 reg = <0 0x088e2000 0 0x154>;
3924 #phy-cells = <0>;
3925
3926 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>;
3927 clock-names = "ref";
3928
3929 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
3930
3931 status = "disabled";
3932 };
3933
3934 usb_mp_qmpphy0: phy@88e3000 {
3935 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3936 reg = <0 0x088e3000 0 0x2000>;
3937
3938 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3939 <&rpmhcc RPMH_CXO_CLK>,
3940 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3941 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
3942 clock-names = "aux",
3943 "ref",
3944 "com_aux",
3945 "pipe";
3946
3947 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
3948 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
3949 reset-names = "phy",
3950 "phy_phy";
3951
3952 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
3953
3954 #clock-cells = <0>;
3955 clock-output-names = "usb_mp_phy0_pipe_clk";
3956
3957 #phy-cells = <0>;
3958
3959 status = "disabled";
3960 };
3961
3962 usb_mp_qmpphy1: phy@88e5000 {
3963 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3964 reg = <0 0x088e5000 0 0x2000>;
3965
3966 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3967 <&rpmhcc RPMH_CXO_CLK>,
3968 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3969 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
3970 clock-names = "aux",
3971 "ref",
3972 "com_aux",
3973 "pipe";
3974
3975 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
3976 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
3977 reset-names = "phy",
3978 "phy_phy";
3979
3980 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
3981
3982 #clock-cells = <0>;
3983 clock-output-names = "usb_mp_phy1_pipe_clk";
3984
3985 #phy-cells = <0>;
3986
3987 status = "disabled";
3988 };
3989
3990 usb_1_ss2: usb@a0f8800 {
3991 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
3992 reg = <0 0x0a0f8800 0 0x400>;
3993
3994 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
3995 <&gcc GCC_USB30_TERT_MASTER_CLK>,
3996 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
3997 <&gcc GCC_USB30_TERT_SLEEP_CLK>,
3998 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
3999 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4000 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4001 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4002 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4003 clock-names = "cfg_noc",
4004 "core",
4005 "iface",
4006 "sleep",
4007 "mock_utmi",
4008 "noc_aggr",
4009 "noc_aggr_north",
4010 "noc_aggr_south",
4011 "noc_sys";
4012
4013 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4014 <&gcc GCC_USB30_TERT_MASTER_CLK>;
4015 assigned-clock-rates = <19200000>,
4016 <200000000>;
4017
4018 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4019 <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
4020 <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
4021 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
4022 interrupt-names = "pwr_event",
4023 "dp_hs_phy_irq",
4024 "dm_hs_phy_irq",
4025 "ss_phy_irq";
4026
4027 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4028 required-opps = <&rpmhpd_opp_nom>;
4029
4030 resets = <&gcc GCC_USB30_TERT_BCR>;
4031
4032 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
4033 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4035 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
4036 interconnect-names = "usb-ddr",
4037 "apps-usb";
4038
4039 wakeup-source;
4040
4041 #address-cells = <2>;
4042 #size-cells = <2>;
4043 ranges;
4044
4045 status = "disabled";
4046
4047 usb_1_ss2_dwc3: usb@a000000 {
4048 compatible = "snps,dwc3";
4049 reg = <0 0x0a000000 0 0xcd00>;
4050
4051 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
4052
4053 iommus = <&apps_smmu 0x14a0 0x0>;
4054
4055 phys = <&usb_1_ss2_hsphy>,
4056 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
4057 phy-names = "usb2-phy",
4058 "usb3-phy";
4059
4060 snps,dis_u2_susphy_quirk;
4061 snps,dis_enblslpm_quirk;
4062 snps,usb3_lpm_capable;
4063
4064 dma-coherent;
4065
4066 ports {
4067 #address-cells = <1>;
4068 #size-cells = <0>;
4069
4070 port@0 {
4071 reg = <0>;
4072
4073 usb_1_ss2_dwc3_hs: endpoint {
4074 };
4075 };
4076
4077 port@1 {
4078 reg = <1>;
4079
4080 usb_1_ss2_dwc3_ss: endpoint {
4081 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4082 };
4083 };
4084 };
4085 };
4086 };
4087
4088 usb_2: usb@a2f8800 {
4089 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4090 reg = <0 0x0a2f8800 0 0x400>;
4091 #address-cells = <2>;
4092 #size-cells = <2>;
4093 ranges;
4094
4095 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
4096 <&gcc GCC_USB20_MASTER_CLK>,
4097 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
4098 <&gcc GCC_USB20_SLEEP_CLK>,
4099 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4100 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4101 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4102 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4103 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4104 clock-names = "cfg_noc",
4105 "core",
4106 "iface",
4107 "sleep",
4108 "mock_utmi",
4109 "noc_aggr",
4110 "noc_aggr_north",
4111 "noc_aggr_south",
4112 "noc_sys";
4113
4114 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4115 <&gcc GCC_USB20_MASTER_CLK>;
4116 assigned-clock-rates = <19200000>, <200000000>;
4117
4118 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4119 <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
4120 <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
4121 interrupt-names = "pwr_event",
4122 "dp_hs_phy_irq",
4123 "dm_hs_phy_irq";
4124
4125 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4126 required-opps = <&rpmhpd_opp_nom>;
4127
4128 resets = <&gcc GCC_USB20_PRIM_BCR>;
4129
4130 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
4131 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4132 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4133 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
4134 interconnect-names = "usb-ddr",
4135 "apps-usb";
4136
4137 wakeup-source;
4138
4139 status = "disabled";
4140
4141 usb_2_dwc3: usb@a200000 {
4142 compatible = "snps,dwc3";
4143 reg = <0 0x0a200000 0 0xcd00>;
4144 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
4145 iommus = <&apps_smmu 0x14e0 0x0>;
4146 phys = <&usb_2_hsphy>;
4147 phy-names = "usb2-phy";
4148 maximum-speed = "high-speed";
4149
4150 ports {
4151 #address-cells = <1>;
4152 #size-cells = <0>;
4153
4154 port@0 {
4155 reg = <0>;
4156
4157 usb_2_dwc3_hs: endpoint {
4158 };
4159 };
4160 };
4161 };
4162 };
4163
4164 usb_mp: usb@a4f8800 {
4165 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
4166 reg = <0 0x0a4f8800 0 0x400>;
4167
4168 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
4169 <&gcc GCC_USB30_MP_MASTER_CLK>,
4170 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
4171 <&gcc GCC_USB30_MP_SLEEP_CLK>,
4172 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4173 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4174 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4175 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4176 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4177 clock-names = "cfg_noc",
4178 "core",
4179 "iface",
4180 "sleep",
4181 "mock_utmi",
4182 "noc_aggr",
4183 "noc_aggr_north",
4184 "noc_aggr_south",
4185 "noc_sys";
4186
4187 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4188 <&gcc GCC_USB30_MP_MASTER_CLK>;
4189 assigned-clock-rates = <19200000>,
4190 <200000000>;
4191
4192 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
4193 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
4194 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
4195 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
4196 <&pdc 52 IRQ_TYPE_EDGE_BOTH>,
4197 <&pdc 51 IRQ_TYPE_EDGE_BOTH>,
4198 <&pdc 54 IRQ_TYPE_EDGE_BOTH>,
4199 <&pdc 53 IRQ_TYPE_EDGE_BOTH>,
4200 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
4201 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
4202 interrupt-names = "pwr_event_1", "pwr_event_2",
4203 "hs_phy_1", "hs_phy_2",
4204 "dp_hs_phy_1", "dm_hs_phy_1",
4205 "dp_hs_phy_2", "dm_hs_phy_2",
4206 "ss_phy_1", "ss_phy_2";
4207
4208 power-domains = <&gcc GCC_USB30_MP_GDSC>;
4209 required-opps = <&rpmhpd_opp_nom>;
4210
4211 resets = <&gcc GCC_USB30_MP_BCR>;
4212
4213 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS
4214 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4215 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4216 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>;
4217 interconnect-names = "usb-ddr",
4218 "apps-usb";
4219
4220 wakeup-source;
4221
4222 #address-cells = <2>;
4223 #size-cells = <2>;
4224 ranges;
4225
4226 status = "disabled";
4227
4228 usb_mp_dwc3: usb@a400000 {
4229 compatible = "snps,dwc3";
4230 reg = <0 0x0a400000 0 0xcd00>;
4231
4232 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
4233
4234 iommus = <&apps_smmu 0x1400 0x0>;
4235
4236 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
4237 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
4238 phy-names = "usb2-0", "usb3-0",
4239 "usb2-1", "usb3-1";
4240 dr_mode = "host";
4241
4242 snps,dis_u2_susphy_quirk;
4243 snps,dis_enblslpm_quirk;
4244 snps,usb3_lpm_capable;
4245
4246 dma-coherent;
4247 };
4248 };
4249
4250 usb_1_ss0: usb@a6f8800 {
4251 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4252 reg = <0 0x0a6f8800 0 0x400>;
4253
4254 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4255 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4256 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4257 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4258 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4259 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4260 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
4261 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
4262 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4263 clock-names = "cfg_noc",
4264 "core",
4265 "iface",
4266 "sleep",
4267 "mock_utmi",
4268 "noc_aggr",
4269 "noc_aggr_north",
4270 "noc_aggr_south",
4271 "noc_sys";
4272
4273 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4274 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4275 assigned-clock-rates = <19200000>,
4276 <200000000>;
4277
4278 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4279 <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
4280 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4281 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4282 interrupt-names = "pwr_event",
4283 "dp_hs_phy_irq",
4284 "dm_hs_phy_irq",
4285 "ss_phy_irq";
4286
4287 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4288 required-opps = <&rpmhpd_opp_nom>;
4289
4290 resets = <&gcc GCC_USB30_PRIM_BCR>;
4291
4292 wakeup-source;
4293
4294 #address-cells = <2>;
4295 #size-cells = <2>;
4296 ranges;
4297
4298 status = "disabled";
4299
4300 usb_1_ss0_dwc3: usb@a600000 {
4301 compatible = "snps,dwc3";
4302 reg = <0 0x0a600000 0 0xcd00>;
4303
4304 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
4305
4306 iommus = <&apps_smmu 0x1420 0x0>;
4307
4308 phys = <&usb_1_ss0_hsphy>,
4309 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
4310 phy-names = "usb2-phy",
4311 "usb3-phy";
4312
4313 snps,dis_u2_susphy_quirk;
4314 snps,dis_enblslpm_quirk;
4315 snps,usb3_lpm_capable;
4316
4317 dma-coherent;
4318
4319 ports {
4320 #address-cells = <1>;
4321 #size-cells = <0>;
4322
4323 port@0 {
4324 reg = <0>;
4325
4326 usb_1_ss0_dwc3_hs: endpoint {
4327 };
4328 };
4329
4330 port@1 {
4331 reg = <1>;
4332
4333 usb_1_ss0_dwc3_ss: endpoint {
4334 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
4335 };
4336 };
4337 };
4338 };
4339 };
4340
4341 usb_1_ss1: usb@a8f8800 {
4342 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4343 reg = <0 0x0a8f8800 0 0x400>;
4344
4345 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4346 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4347 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4348 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4349 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4350 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4351 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4352 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4353 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4354 clock-names = "cfg_noc",
4355 "core",
4356 "iface",
4357 "sleep",
4358 "mock_utmi",
4359 "noc_aggr",
4360 "noc_aggr_north",
4361 "noc_aggr_south",
4362 "noc_sys";
4363
4364 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4365 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4366 assigned-clock-rates = <19200000>,
4367 <200000000>;
4368
4369 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4370 <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
4371 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
4372 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
4373 interrupt-names = "pwr_event",
4374 "dp_hs_phy_irq",
4375 "dm_hs_phy_irq",
4376 "ss_phy_irq";
4377
4378 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4379 required-opps = <&rpmhpd_opp_nom>;
4380
4381 resets = <&gcc GCC_USB30_SEC_BCR>;
4382
4383 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
4384 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4385 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4386 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
4387 interconnect-names = "usb-ddr",
4388 "apps-usb";
4389
4390 wakeup-source;
4391
4392 #address-cells = <2>;
4393 #size-cells = <2>;
4394 ranges;
4395
4396 status = "disabled";
4397
4398 usb_1_ss1_dwc3: usb@a800000 {
4399 compatible = "snps,dwc3";
4400 reg = <0 0x0a800000 0 0xcd00>;
4401
4402 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
4403
4404 iommus = <&apps_smmu 0x1460 0x0>;
4405
4406 phys = <&usb_1_ss1_hsphy>,
4407 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
4408 phy-names = "usb2-phy",
4409 "usb3-phy";
4410
4411 snps,dis_u2_susphy_quirk;
4412 snps,dis_enblslpm_quirk;
4413 snps,usb3_lpm_capable;
4414
4415 dma-coherent;
4416
4417 ports {
4418 #address-cells = <1>;
4419 #size-cells = <0>;
4420
4421 port@0 {
4422 reg = <0>;
4423
4424 usb_1_ss1_dwc3_hs: endpoint {
4425 };
4426 };
4427
4428 port@1 {
4429 reg = <1>;
4430
4431 usb_1_ss1_dwc3_ss: endpoint {
4432 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
4433 };
4434 };
4435 };
4436 };
4437 };
4438
4439 mdss: display-subsystem@ae00000 {
4440 compatible = "qcom,x1e80100-mdss";
4441 reg = <0 0x0ae00000 0 0x1000>;
4442 reg-names = "mdss";
4443
4444 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4445
4446 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4447 <&gcc GCC_DISP_HF_AXI_CLK>,
4448 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4449
4450 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
4451
4452 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
4453 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
4454 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
4455 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4456 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4457 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
4458 interconnect-names = "mdp0-mem",
4459 "mdp1-mem",
4460 "cpu-cfg";
4461
4462 power-domains = <&dispcc MDSS_GDSC>;
4463
4464 iommus = <&apps_smmu 0x1c00 0x2>;
4465
4466 interrupt-controller;
4467 #interrupt-cells = <1>;
4468
4469 #address-cells = <2>;
4470 #size-cells = <2>;
4471 ranges;
4472
4473 status = "disabled";
4474
4475 mdss_mdp: display-controller@ae01000 {
4476 compatible = "qcom,x1e80100-dpu";
4477 reg = <0 0x0ae01000 0 0x8f000>,
4478 <0 0x0aeb0000 0 0x2008>;
4479 reg-names = "mdp",
4480 "vbif";
4481
4482 interrupts-extended = <&mdss 0>;
4483
4484 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4485 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4486 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
4487 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4488 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4489 clock-names = "nrt_bus",
4490 "iface",
4491 "lut",
4492 "core",
4493 "vsync";
4494
4495 operating-points-v2 = <&mdp_opp_table>;
4496
4497 power-domains = <&rpmhpd RPMHPD_MMCX>;
4498
4499 ports {
4500 #address-cells = <1>;
4501 #size-cells = <0>;
4502
4503 port@0 {
4504 reg = <0>;
4505
4506 mdss_intf0_out: endpoint {
4507 remote-endpoint = <&mdss_dp0_in>;
4508 };
4509 };
4510
4511 port@4 {
4512 reg = <4>;
4513
4514 mdss_intf4_out: endpoint {
4515 remote-endpoint = <&mdss_dp1_in>;
4516 };
4517 };
4518
4519 port@5 {
4520 reg = <5>;
4521
4522 mdss_intf5_out: endpoint {
4523 remote-endpoint = <&mdss_dp3_in>;
4524 };
4525 };
4526
4527 port@6 {
4528 reg = <6>;
4529
4530 mdss_intf6_out: endpoint {
4531 remote-endpoint = <&mdss_dp2_in>;
4532 };
4533 };
4534 };
4535
4536 mdp_opp_table: opp-table {
4537 compatible = "operating-points-v2";
4538
4539 opp-200000000 {
4540 opp-hz = /bits/ 64 <200000000>;
4541 required-opps = <&rpmhpd_opp_low_svs>;
4542 };
4543
4544 opp-325000000 {
4545 opp-hz = /bits/ 64 <325000000>;
4546 required-opps = <&rpmhpd_opp_svs>;
4547 };
4548
4549 opp-375000000 {
4550 opp-hz = /bits/ 64 <375000000>;
4551 required-opps = <&rpmhpd_opp_svs_l1>;
4552 };
4553
4554 opp-514000000 {
4555 opp-hz = /bits/ 64 <514000000>;
4556 required-opps = <&rpmhpd_opp_nom>;
4557 };
4558
4559 opp-575000000 {
4560 opp-hz = /bits/ 64 <575000000>;
4561 required-opps = <&rpmhpd_opp_nom_l1>;
4562 };
4563 };
4564 };
4565
4566 mdss_dp0: displayport-controller@ae90000 {
4567 compatible = "qcom,x1e80100-dp";
4568 reg = <0 0x0ae90000 0 0x200>,
4569 <0 0x0ae90200 0 0x200>,
4570 <0 0x0ae90400 0 0x600>,
4571 <0 0x0ae91000 0 0x400>,
4572 <0 0x0ae91400 0 0x400>;
4573
4574 interrupts-extended = <&mdss 12>;
4575
4576 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4577 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
4578 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
4579 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4580 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4581 clock-names = "core_iface",
4582 "core_aux",
4583 "ctrl_link",
4584 "ctrl_link_iface",
4585 "stream_pixel";
4586
4587 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4588 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4589 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4590 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4591
4592 operating-points-v2 = <&mdss_dp0_opp_table>;
4593
4594 power-domains = <&rpmhpd RPMHPD_MMCX>;
4595
4596 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
4597 phy-names = "dp";
4598
4599 #sound-dai-cells = <0>;
4600
4601 status = "disabled";
4602
4603 ports {
4604 #address-cells = <1>;
4605 #size-cells = <0>;
4606
4607 port@0 {
4608 reg = <0>;
4609
4610 mdss_dp0_in: endpoint {
4611 remote-endpoint = <&mdss_intf0_out>;
4612 };
4613 };
4614
4615 port@1 {
4616 reg = <1>;
4617
4618 mdss_dp0_out: endpoint {
4619 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
4620 };
4621 };
4622 };
4623
4624 mdss_dp0_opp_table: opp-table {
4625 compatible = "operating-points-v2";
4626
4627 opp-160000000 {
4628 opp-hz = /bits/ 64 <160000000>;
4629 required-opps = <&rpmhpd_opp_low_svs>;
4630 };
4631
4632 opp-270000000 {
4633 opp-hz = /bits/ 64 <270000000>;
4634 required-opps = <&rpmhpd_opp_svs>;
4635 };
4636
4637 opp-540000000 {
4638 opp-hz = /bits/ 64 <540000000>;
4639 required-opps = <&rpmhpd_opp_svs_l1>;
4640 };
4641
4642 opp-810000000 {
4643 opp-hz = /bits/ 64 <810000000>;
4644 required-opps = <&rpmhpd_opp_nom>;
4645 };
4646 };
4647 };
4648
4649 mdss_dp1: displayport-controller@ae98000 {
4650 compatible = "qcom,x1e80100-dp";
4651 reg = <0 0x0ae98000 0 0x200>,
4652 <0 0x0ae98200 0 0x200>,
4653 <0 0x0ae98400 0 0x600>,
4654 <0 0x0ae99000 0 0x400>,
4655 <0 0x0ae99400 0 0x400>;
4656
4657 interrupts-extended = <&mdss 13>;
4658
4659 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4660 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
4661 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
4662 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4663 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4664 clock-names = "core_iface",
4665 "core_aux",
4666 "ctrl_link",
4667 "ctrl_link_iface",
4668 "stream_pixel";
4669
4670 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4671 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4672 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4673 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4674
4675 operating-points-v2 = <&mdss_dp1_opp_table>;
4676
4677 power-domains = <&rpmhpd RPMHPD_MMCX>;
4678
4679 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
4680 phy-names = "dp";
4681
4682 #sound-dai-cells = <0>;
4683
4684 status = "disabled";
4685
4686 ports {
4687 #address-cells = <1>;
4688 #size-cells = <0>;
4689
4690 port@0 {
4691 reg = <0>;
4692
4693 mdss_dp1_in: endpoint {
4694 remote-endpoint = <&mdss_intf4_out>;
4695 };
4696 };
4697
4698 port@1 {
4699 reg = <1>;
4700
4701 mdss_dp1_out: endpoint {
4702 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
4703 };
4704 };
4705 };
4706
4707 mdss_dp1_opp_table: opp-table {
4708 compatible = "operating-points-v2";
4709
4710 opp-160000000 {
4711 opp-hz = /bits/ 64 <160000000>;
4712 required-opps = <&rpmhpd_opp_low_svs>;
4713 };
4714
4715 opp-270000000 {
4716 opp-hz = /bits/ 64 <270000000>;
4717 required-opps = <&rpmhpd_opp_svs>;
4718 };
4719
4720 opp-540000000 {
4721 opp-hz = /bits/ 64 <540000000>;
4722 required-opps = <&rpmhpd_opp_svs_l1>;
4723 };
4724
4725 opp-810000000 {
4726 opp-hz = /bits/ 64 <810000000>;
4727 required-opps = <&rpmhpd_opp_nom>;
4728 };
4729 };
4730 };
4731
4732 mdss_dp2: displayport-controller@ae9a000 {
4733 compatible = "qcom,x1e80100-dp";
4734 reg = <0 0x0ae9a000 0 0x200>,
4735 <0 0x0ae9a200 0 0x200>,
4736 <0 0x0ae9a400 0 0x600>,
4737 <0 0x0ae9b000 0 0x400>,
4738 <0 0x0ae9b400 0 0x400>;
4739
4740 interrupts-extended = <&mdss 14>;
4741
4742 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4743 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4744 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
4745 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4746 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4747 clock-names = "core_iface",
4748 "core_aux",
4749 "ctrl_link",
4750 "ctrl_link_iface",
4751 "stream_pixel";
4752
4753 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4754 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4755 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4756 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4757
4758 operating-points-v2 = <&mdss_dp2_opp_table>;
4759
4760 power-domains = <&rpmhpd RPMHPD_MMCX>;
4761
4762 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
4763 phy-names = "dp";
4764
4765 #sound-dai-cells = <0>;
4766
4767 status = "disabled";
4768
4769 ports {
4770 #address-cells = <1>;
4771 #size-cells = <0>;
4772
4773 port@0 {
4774 reg = <0>;
4775 mdss_dp2_in: endpoint {
4776 remote-endpoint = <&mdss_intf6_out>;
4777 };
4778 };
4779
4780 port@1 {
4781 reg = <1>;
4782
4783 mdss_dp2_out: endpoint {
4784 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
4785 };
4786 };
4787 };
4788
4789 mdss_dp2_opp_table: opp-table {
4790 compatible = "operating-points-v2";
4791
4792 opp-160000000 {
4793 opp-hz = /bits/ 64 <160000000>;
4794 required-opps = <&rpmhpd_opp_low_svs>;
4795 };
4796
4797 opp-270000000 {
4798 opp-hz = /bits/ 64 <270000000>;
4799 required-opps = <&rpmhpd_opp_svs>;
4800 };
4801
4802 opp-540000000 {
4803 opp-hz = /bits/ 64 <540000000>;
4804 required-opps = <&rpmhpd_opp_svs_l1>;
4805 };
4806
4807 opp-810000000 {
4808 opp-hz = /bits/ 64 <810000000>;
4809 required-opps = <&rpmhpd_opp_nom>;
4810 };
4811 };
4812 };
4813
4814 mdss_dp3: displayport-controller@aea0000 {
4815 compatible = "qcom,x1e80100-dp";
4816 reg = <0 0x0aea0000 0 0x200>,
4817 <0 0x0aea0200 0 0x200>,
4818 <0 0x0aea0400 0 0x600>,
4819 <0 0x0aea1000 0 0x400>,
4820 <0 0x0aea1400 0 0x400>;
4821
4822 interrupts-extended = <&mdss 15>;
4823
4824 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4825 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4826 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
4827 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4828 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4829 clock-names = "core_iface",
4830 "core_aux",
4831 "ctrl_link",
4832 "ctrl_link_iface",
4833 "stream_pixel";
4834
4835 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4836 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4837 assigned-clock-parents = <&mdss_dp3_phy 0>,
4838 <&mdss_dp3_phy 1>;
4839
4840 operating-points-v2 = <&mdss_dp3_opp_table>;
4841
4842 power-domains = <&rpmhpd RPMHPD_MMCX>;
4843
4844 phys = <&mdss_dp3_phy>;
4845 phy-names = "dp";
4846
4847 #sound-dai-cells = <0>;
4848
4849 status = "disabled";
4850
4851 ports {
4852 #address-cells = <1>;
4853 #size-cells = <0>;
4854
4855 port@0 {
4856 reg = <0>;
4857
4858 mdss_dp3_in: endpoint {
4859 remote-endpoint = <&mdss_intf5_out>;
4860 };
4861 };
4862
4863 port@1 {
4864 reg = <1>;
4865 };
4866 };
4867
4868 mdss_dp3_opp_table: opp-table {
4869 compatible = "operating-points-v2";
4870
4871 opp-160000000 {
4872 opp-hz = /bits/ 64 <160000000>;
4873 required-opps = <&rpmhpd_opp_low_svs>;
4874 };
4875
4876 opp-270000000 {
4877 opp-hz = /bits/ 64 <270000000>;
4878 required-opps = <&rpmhpd_opp_svs>;
4879 };
4880
4881 opp-540000000 {
4882 opp-hz = /bits/ 64 <540000000>;
4883 required-opps = <&rpmhpd_opp_svs_l1>;
4884 };
4885
4886 opp-810000000 {
4887 opp-hz = /bits/ 64 <810000000>;
4888 required-opps = <&rpmhpd_opp_nom>;
4889 };
4890 };
4891 };
4892
4893 };
4894
4895 mdss_dp2_phy: phy@aec2a00 {
4896 compatible = "qcom,x1e80100-dp-phy";
4897 reg = <0 0x0aec2a00 0 0x19c>,
4898 <0 0x0aec2200 0 0xec>,
4899 <0 0x0aec2600 0 0xec>,
4900 <0 0x0aec2000 0 0x1c8>;
4901
4902 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4903 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4904 clock-names = "aux",
4905 "cfg_ahb";
4906
4907 power-domains = <&rpmhpd RPMHPD_MX>;
4908
4909 #clock-cells = <1>;
4910 #phy-cells = <0>;
4911
4912 status = "disabled";
4913 };
4914
4915 mdss_dp3_phy: phy@aec5a00 {
4916 compatible = "qcom,x1e80100-dp-phy";
4917 reg = <0 0x0aec5a00 0 0x19c>,
4918 <0 0x0aec5200 0 0xec>,
4919 <0 0x0aec5600 0 0xec>,
4920 <0 0x0aec5000 0 0x1c8>;
4921
4922 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4923 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4924 clock-names = "aux",
4925 "cfg_ahb";
4926
4927 power-domains = <&rpmhpd RPMHPD_MX>;
4928
4929 #clock-cells = <1>;
4930 #phy-cells = <0>;
4931
4932 status = "disabled";
4933 };
4934
4935 dispcc: clock-controller@af00000 {
4936 compatible = "qcom,x1e80100-dispcc";
4937 reg = <0 0x0af00000 0 0x20000>;
4938 clocks = <&bi_tcxo_div2>,
4939 <&bi_tcxo_ao_div2>,
4940 <&gcc GCC_DISP_AHB_CLK>,
4941 <&sleep_clk>,
4942 <0>, /* dsi0 */
4943 <0>,
4944 <0>, /* dsi1 */
4945 <0>,
4946 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
4947 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4948 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
4949 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4950 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
4951 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4952 <&mdss_dp3_phy 0>, /* dp3 */
4953 <&mdss_dp3_phy 1>;
4954 power-domains = <&rpmhpd RPMHPD_MMCX>;
4955 required-opps = <&rpmhpd_opp_low_svs>;
4956 #clock-cells = <1>;
4957 #reset-cells = <1>;
4958 #power-domain-cells = <1>;
4959 };
4960
4961 pdc: interrupt-controller@b220000 {
4962 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4963 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4964
4965 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4966 <47 522 52>, <99 609 32>,
4967 <131 717 12>, <143 816 19>;
4968 #interrupt-cells = <2>;
4969 interrupt-parent = <&intc>;
4970 interrupt-controller;
4971 };
4972
4973 aoss_qmp: power-management@c300000 {
4974 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
4975 reg = <0 0x0c300000 0 0x400>;
4976 interrupt-parent = <&ipcc>;
4977 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4978 IRQ_TYPE_EDGE_RISING>;
4979 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4980
4981 #clock-cells = <0>;
4982 };
4983
4984 sram@c3f0000 {
4985 compatible = "qcom,rpmh-stats";
4986 reg = <0 0x0c3f0000 0 0x400>;
4987 };
4988
4989 spmi: arbiter@c400000 {
4990 compatible = "qcom,x1e80100-spmi-pmic-arb";
4991 reg = <0 0x0c400000 0 0x3000>,
4992 <0 0x0c500000 0 0x400000>,
4993 <0 0x0c440000 0 0x80000>;
4994 reg-names = "core", "chnls", "obsrvr";
4995
4996 qcom,ee = <0>;
4997 qcom,channel = <0>;
4998
4999 #address-cells = <2>;
5000 #size-cells = <2>;
5001 ranges;
5002
5003 spmi_bus0: spmi@c42d000 {
5004 reg = <0 0x0c42d000 0 0x4000>,
5005 <0 0x0c4c0000 0 0x10000>;
5006 reg-names = "cnfg", "intr";
5007
5008 interrupt-names = "periph_irq";
5009 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5010 interrupt-controller;
5011 #interrupt-cells = <4>;
5012
5013 #address-cells = <2>;
5014 #size-cells = <0>;
5015 };
5016
5017 spmi_bus1: spmi@c432000 {
5018 reg = <0 0x0c432000 0 0x4000>,
5019 <0 0x0c4d0000 0 0x10000>;
5020 reg-names = "cnfg", "intr";
5021
5022 interrupt-names = "periph_irq";
5023 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5024 interrupt-controller;
5025 #interrupt-cells = <4>;
5026
5027 #address-cells = <2>;
5028 #size-cells = <0>;
5029 };
5030 };
5031
5032 tlmm: pinctrl@f100000 {
5033 compatible = "qcom,x1e80100-tlmm";
5034 reg = <0 0x0f100000 0 0xf00000>;
5035
5036 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5037
5038 gpio-controller;
5039 #gpio-cells = <2>;
5040
5041 interrupt-controller;
5042 #interrupt-cells = <2>;
5043
5044 gpio-ranges = <&tlmm 0 0 239>;
5045 wakeup-parent = <&pdc>;
5046
5047 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5048 /* SDA, SCL */
5049 pins = "gpio0", "gpio1";
5050 function = "qup0_se0";
5051 drive-strength = <2>;
5052 bias-pull-up = <2200>;
5053 };
5054
5055 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5056 /* SDA, SCL */
5057 pins = "gpio4", "gpio5";
5058 function = "qup0_se1";
5059 drive-strength = <2>;
5060 bias-pull-up = <2200>;
5061 };
5062
5063 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5064 /* SDA, SCL */
5065 pins = "gpio8", "gpio9";
5066 function = "qup0_se2";
5067 drive-strength = <2>;
5068 bias-pull-up = <2200>;
5069 };
5070
5071 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5072 /* SDA, SCL */
5073 pins = "gpio12", "gpio13";
5074 function = "qup0_se3";
5075 drive-strength = <2>;
5076 bias-pull-up = <2200>;
5077 };
5078
5079 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5080 /* SDA, SCL */
5081 pins = "gpio16", "gpio17";
5082 function = "qup0_se4";
5083 drive-strength = <2>;
5084 bias-pull-up = <2200>;
5085 };
5086
5087 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5088 /* SDA, SCL */
5089 pins = "gpio20", "gpio21";
5090 function = "qup0_se5";
5091 drive-strength = <2>;
5092 bias-pull-up = <2200>;
5093 };
5094
5095 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5096 /* SDA, SCL */
5097 pins = "gpio24", "gpio25";
5098 function = "qup0_se6";
5099 drive-strength = <2>;
5100 bias-pull-up = <2200>;
5101 };
5102
5103 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5104 /* SDA, SCL */
5105 pins = "gpio14", "gpio15";
5106 function = "qup0_se7";
5107 drive-strength = <2>;
5108 bias-pull-up = <2200>;
5109 };
5110
5111 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5112 /* SDA, SCL */
5113 pins = "gpio32", "gpio33";
5114 function = "qup1_se0";
5115 drive-strength = <2>;
5116 bias-pull-up = <2200>;
5117 };
5118
5119 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5120 /* SDA, SCL */
5121 pins = "gpio36", "gpio37";
5122 function = "qup1_se1";
5123 drive-strength = <2>;
5124 bias-pull-up = <2200>;
5125 };
5126
5127 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5128 /* SDA, SCL */
5129 pins = "gpio40", "gpio41";
5130 function = "qup1_se2";
5131 drive-strength = <2>;
5132 bias-pull-up = <2200>;
5133 };
5134
5135 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5136 /* SDA, SCL */
5137 pins = "gpio44", "gpio45";
5138 function = "qup1_se3";
5139 drive-strength = <2>;
5140 bias-pull-up = <2200>;
5141 };
5142
5143 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5144 /* SDA, SCL */
5145 pins = "gpio48", "gpio49";
5146 function = "qup1_se4";
5147 drive-strength = <2>;
5148 bias-pull-up = <2200>;
5149 };
5150
5151 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5152 /* SDA, SCL */
5153 pins = "gpio52", "gpio53";
5154 function = "qup1_se5";
5155 drive-strength = <2>;
5156 bias-pull-up = <2200>;
5157 };
5158
5159 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5160 /* SDA, SCL */
5161 pins = "gpio56", "gpio57";
5162 function = "qup1_se6";
5163 drive-strength = <2>;
5164 bias-pull-up = <2200>;
5165 };
5166
5167 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5168 /* SDA, SCL */
5169 pins = "gpio54", "gpio55";
5170 function = "qup1_se7";
5171 drive-strength = <2>;
5172 bias-pull-up = <2200>;
5173 };
5174
5175 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5176 /* SDA, SCL */
5177 pins = "gpio64", "gpio65";
5178 function = "qup2_se0";
5179 drive-strength = <2>;
5180 bias-pull-up = <2200>;
5181 };
5182
5183 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5184 /* SDA, SCL */
5185 pins = "gpio68", "gpio69";
5186 function = "qup2_se1";
5187 drive-strength = <2>;
5188 bias-pull-up = <2200>;
5189 };
5190
5191 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5192 /* SDA, SCL */
5193 pins = "gpio72", "gpio73";
5194 function = "qup2_se2";
5195 drive-strength = <2>;
5196 bias-pull-up = <2200>;
5197 };
5198
5199 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5200 /* SDA, SCL */
5201 pins = "gpio76", "gpio77";
5202 function = "qup2_se3";
5203 drive-strength = <2>;
5204 bias-pull-up = <2200>;
5205 };
5206
5207 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5208 /* SDA, SCL */
5209 pins = "gpio80", "gpio81";
5210 function = "qup2_se4";
5211 drive-strength = <2>;
5212 bias-pull-up = <2200>;
5213 };
5214
5215 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5216 /* SDA, SCL */
5217 pins = "gpio84", "gpio85";
5218 function = "qup2_se5";
5219 drive-strength = <2>;
5220 bias-pull-up = <2200>;
5221 };
5222
5223 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5224 /* SDA, SCL */
5225 pins = "gpio88", "gpio89";
5226 function = "qup2_se6";
5227 drive-strength = <2>;
5228 bias-pull-up = <2200>;
5229 };
5230
5231 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5232 /* SDA, SCL */
5233 pins = "gpio86", "gpio87";
5234 function = "qup2_se7";
5235 drive-strength = <2>;
5236 bias-pull-up = <2200>;
5237 };
5238
5239 qup_spi0_cs: qup-spi0-cs-state {
5240 pins = "gpio3";
5241 function = "qup0_se0";
5242 drive-strength = <6>;
5243 bias-disable;
5244 };
5245
5246 qup_spi0_data_clk: qup-spi0-data-clk-state {
5247 /* MISO, MOSI, CLK */
5248 pins = "gpio0", "gpio1", "gpio2";
5249 function = "qup0_se0";
5250 drive-strength = <6>;
5251 bias-disable;
5252 };
5253
5254 qup_spi1_cs: qup-spi1-cs-state {
5255 pins = "gpio7";
5256 function = "qup0_se1";
5257 drive-strength = <6>;
5258 bias-disable;
5259 };
5260
5261 qup_spi1_data_clk: qup-spi1-data-clk-state {
5262 /* MISO, MOSI, CLK */
5263 pins = "gpio4", "gpio5", "gpio6";
5264 function = "qup0_se1";
5265 drive-strength = <6>;
5266 bias-disable;
5267 };
5268
5269 qup_spi2_cs: qup-spi2-cs-state {
5270 pins = "gpio11";
5271 function = "qup0_se2";
5272 drive-strength = <6>;
5273 bias-disable;
5274 };
5275
5276 qup_spi2_data_clk: qup-spi2-data-clk-state {
5277 /* MISO, MOSI, CLK */
5278 pins = "gpio8", "gpio9", "gpio10";
5279 function = "qup0_se2";
5280 drive-strength = <6>;
5281 bias-disable;
5282 };
5283
5284 qup_spi3_cs: qup-spi3-cs-state {
5285 pins = "gpio15";
5286 function = "qup0_se3";
5287 drive-strength = <6>;
5288 bias-disable;
5289 };
5290
5291 qup_spi3_data_clk: qup-spi3-data-clk-state {
5292 /* MISO, MOSI, CLK */
5293 pins = "gpio12", "gpio13", "gpio14";
5294 function = "qup0_se3";
5295 drive-strength = <6>;
5296 bias-disable;
5297 };
5298
5299 qup_spi4_cs: qup-spi4-cs-state {
5300 pins = "gpio19";
5301 function = "qup0_se4";
5302 drive-strength = <6>;
5303 bias-disable;
5304 };
5305
5306 qup_spi4_data_clk: qup-spi4-data-clk-state {
5307 /* MISO, MOSI, CLK */
5308 pins = "gpio16", "gpio17", "gpio18";
5309 function = "qup0_se4";
5310 drive-strength = <6>;
5311 bias-disable;
5312 };
5313
5314 qup_spi5_cs: qup-spi5-cs-state {
5315 pins = "gpio23";
5316 function = "qup0_se5";
5317 drive-strength = <6>;
5318 bias-disable;
5319 };
5320
5321 qup_spi5_data_clk: qup-spi5-data-clk-state {
5322 /* MISO, MOSI, CLK */
5323 pins = "gpio20", "gpio21", "gpio22";
5324 function = "qup0_se5";
5325 drive-strength = <6>;
5326 bias-disable;
5327 };
5328
5329 qup_spi6_cs: qup-spi6-cs-state {
5330 pins = "gpio27";
5331 function = "qup0_se6";
5332 drive-strength = <6>;
5333 bias-disable;
5334 };
5335
5336 qup_spi6_data_clk: qup-spi6-data-clk-state {
5337 /* MISO, MOSI, CLK */
5338 pins = "gpio24", "gpio25", "gpio26";
5339 function = "qup0_se6";
5340 drive-strength = <6>;
5341 bias-disable;
5342 };
5343
5344 qup_spi7_cs: qup-spi7-cs-state {
5345 pins = "gpio13";
5346 function = "qup0_se7";
5347 drive-strength = <6>;
5348 bias-disable;
5349 };
5350
5351 qup_spi7_data_clk: qup-spi7-data-clk-state {
5352 /* MISO, MOSI, CLK */
5353 pins = "gpio14", "gpio15", "gpio12";
5354 function = "qup0_se7";
5355 drive-strength = <6>;
5356 bias-disable;
5357 };
5358
5359 qup_spi8_cs: qup-spi8-cs-state {
5360 pins = "gpio35";
5361 function = "qup1_se0";
5362 drive-strength = <6>;
5363 bias-disable;
5364 };
5365
5366 qup_spi8_data_clk: qup-spi8-data-clk-state {
5367 /* MISO, MOSI, CLK */
5368 pins = "gpio32", "gpio33", "gpio34";
5369 function = "qup1_se0";
5370 drive-strength = <6>;
5371 bias-disable;
5372 };
5373
5374 qup_spi9_cs: qup-spi9-cs-state {
5375 pins = "gpio39";
5376 function = "qup1_se1";
5377 drive-strength = <6>;
5378 bias-disable;
5379 };
5380
5381 qup_spi9_data_clk: qup-spi9-data-clk-state {
5382 /* MISO, MOSI, CLK */
5383 pins = "gpio36", "gpio37", "gpio38";
5384 function = "qup1_se1";
5385 drive-strength = <6>;
5386 bias-disable;
5387 };
5388
5389 qup_spi10_cs: qup-spi10-cs-state {
5390 pins = "gpio43";
5391 function = "qup1_se2";
5392 drive-strength = <6>;
5393 bias-disable;
5394 };
5395
5396 qup_spi10_data_clk: qup-spi10-data-clk-state {
5397 /* MISO, MOSI, CLK */
5398 pins = "gpio40", "gpio41", "gpio42";
5399 function = "qup1_se2";
5400 drive-strength = <6>;
5401 bias-disable;
5402 };
5403
5404 qup_spi11_cs: qup-spi11-cs-state {
5405 pins = "gpio47";
5406 function = "qup1_se3";
5407 drive-strength = <6>;
5408 bias-disable;
5409 };
5410
5411 qup_spi11_data_clk: qup-spi11-data-clk-state {
5412 /* MISO, MOSI, CLK */
5413 pins = "gpio44", "gpio45", "gpio46";
5414 function = "qup1_se3";
5415 drive-strength = <6>;
5416 bias-disable;
5417 };
5418
5419 qup_spi12_cs: qup-spi12-cs-state {
5420 pins = "gpio51";
5421 function = "qup1_se4";
5422 drive-strength = <6>;
5423 bias-disable;
5424 };
5425
5426 qup_spi12_data_clk: qup-spi12-data-clk-state {
5427 /* MISO, MOSI, CLK */
5428 pins = "gpio48", "gpio49", "gpio50";
5429 function = "qup1_se4";
5430 drive-strength = <6>;
5431 bias-disable;
5432 };
5433
5434 qup_spi13_cs: qup-spi13-cs-state {
5435 pins = "gpio55";
5436 function = "qup1_se5";
5437 drive-strength = <6>;
5438 bias-disable;
5439 };
5440
5441 qup_spi13_data_clk: qup-spi13-data-clk-state {
5442 /* MISO, MOSI, CLK */
5443 pins = "gpio52", "gpio53", "gpio54";
5444 function = "qup1_se5";
5445 drive-strength = <6>;
5446 bias-disable;
5447 };
5448
5449 qup_spi14_cs: qup-spi14-cs-state {
5450 pins = "gpio59";
5451 function = "qup1_se6";
5452 drive-strength = <6>;
5453 bias-disable;
5454 };
5455
5456 qup_spi14_data_clk: qup-spi14-data-clk-state {
5457 /* MISO, MOSI, CLK */
5458 pins = "gpio56", "gpio57", "gpio58";
5459 function = "qup1_se6";
5460 drive-strength = <6>;
5461 bias-disable;
5462 };
5463
5464 qup_spi15_cs: qup-spi15-cs-state {
5465 pins = "gpio53";
5466 function = "qup1_se7";
5467 drive-strength = <6>;
5468 bias-disable;
5469 };
5470
5471 qup_spi15_data_clk: qup-spi15-data-clk-state {
5472 /* MISO, MOSI, CLK */
5473 pins = "gpio54", "gpio55", "gpio52";
5474 function = "qup1_se7";
5475 drive-strength = <6>;
5476 bias-disable;
5477 };
5478
5479 qup_spi16_cs: qup-spi16-cs-state {
5480 pins = "gpio67";
5481 function = "qup2_se0";
5482 drive-strength = <6>;
5483 bias-disable;
5484 };
5485
5486 qup_spi16_data_clk: qup-spi16-data-clk-state {
5487 /* MISO, MOSI, CLK */
5488 pins = "gpio64", "gpio65", "gpio66";
5489 function = "qup2_se0";
5490 drive-strength = <6>;
5491 bias-disable;
5492 };
5493
5494 qup_spi17_cs: qup-spi17-cs-state {
5495 pins = "gpio71";
5496 function = "qup2_se1";
5497 drive-strength = <6>;
5498 bias-disable;
5499 };
5500
5501 qup_spi17_data_clk: qup-spi17-data-clk-state {
5502 /* MISO, MOSI, CLK */
5503 pins = "gpio68", "gpio69", "gpio70";
5504 function = "qup2_se1";
5505 drive-strength = <6>;
5506 bias-disable;
5507 };
5508
5509 qup_spi18_cs: qup-spi18-cs-state {
5510 pins = "gpio75";
5511 function = "qup2_se2";
5512 drive-strength = <6>;
5513 bias-disable;
5514 };
5515
5516 qup_spi18_data_clk: qup-spi18-data-clk-state {
5517 /* MISO, MOSI, CLK */
5518 pins = "gpio72", "gpio73", "gpio74";
5519 function = "qup2_se2";
5520 drive-strength = <6>;
5521 bias-disable;
5522 };
5523
5524 qup_spi19_cs: qup-spi19-cs-state {
5525 pins = "gpio79";
5526 function = "qup2_se3";
5527 drive-strength = <6>;
5528 bias-disable;
5529 };
5530
5531 qup_spi19_data_clk: qup-spi19-data-clk-state {
5532 /* MISO, MOSI, CLK */
5533 pins = "gpio76", "gpio77", "gpio78";
5534 function = "qup2_se3";
5535 drive-strength = <6>;
5536 bias-disable;
5537 };
5538
5539 qup_spi20_cs: qup-spi20-cs-state {
5540 pins = "gpio83";
5541 function = "qup2_se4";
5542 drive-strength = <6>;
5543 bias-disable;
5544 };
5545
5546 qup_spi20_data_clk: qup-spi20-data-clk-state {
5547 /* MISO, MOSI, CLK */
5548 pins = "gpio80", "gpio81", "gpio82";
5549 function = "qup2_se4";
5550 drive-strength = <6>;
5551 bias-disable;
5552 };
5553
5554 qup_spi21_cs: qup-spi21-cs-state {
5555 pins = "gpio87";
5556 function = "qup2_se5";
5557 drive-strength = <6>;
5558 bias-disable;
5559 };
5560
5561 qup_spi21_data_clk: qup-spi21-data-clk-state {
5562 /* MISO, MOSI, CLK */
5563 pins = "gpio84", "gpio85", "gpio86";
5564 function = "qup2_se5";
5565 drive-strength = <6>;
5566 bias-disable;
5567 };
5568
5569 qup_spi22_cs: qup-spi22-cs-state {
5570 pins = "gpio91";
5571 function = "qup2_se6";
5572 drive-strength = <6>;
5573 bias-disable;
5574 };
5575
5576 qup_spi22_data_clk: qup-spi22-data-clk-state {
5577 /* MISO, MOSI, CLK */
5578 pins = "gpio88", "gpio89", "gpio90";
5579 function = "qup2_se6";
5580 drive-strength = <6>;
5581 bias-disable;
5582 };
5583
5584 qup_spi23_cs: qup-spi23-cs-state {
5585 pins = "gpio85";
5586 function = "qup2_se7";
5587 drive-strength = <6>;
5588 bias-disable;
5589 };
5590
5591 qup_spi23_data_clk: qup-spi23-data-clk-state {
5592 /* MISO, MOSI, CLK */
5593 pins = "gpio86", "gpio87", "gpio84";
5594 function = "qup2_se7";
5595 drive-strength = <6>;
5596 bias-disable;
5597 };
5598
5599 qup_uart2_default: qup-uart2-default-state {
5600 cts-pins {
5601 pins = "gpio8";
5602 function = "qup0_se2";
5603 drive-strength = <2>;
5604 bias-disable;
5605 };
5606
5607 rts-pins {
5608 pins = "gpio9";
5609 function = "qup0_se2";
5610 drive-strength = <2>;
5611 bias-disable;
5612 };
5613
5614 tx-pins {
5615 pins = "gpio10";
5616 function = "qup0_se2";
5617 drive-strength = <2>;
5618 bias-disable;
5619 };
5620
5621 rx-pins {
5622 pins = "gpio11";
5623 function = "qup0_se2";
5624 drive-strength = <2>;
5625 bias-disable;
5626 };
5627 };
5628
5629 qup_uart21_default: qup-uart21-default-state {
5630 tx-pins {
5631 pins = "gpio86";
5632 function = "qup2_se5";
5633 drive-strength = <2>;
5634 bias-disable;
5635 };
5636
5637 rx-pins {
5638 pins = "gpio87";
5639 function = "qup2_se5";
5640 drive-strength = <2>;
5641 bias-disable;
5642 };
5643 };
5644 };
5645
5646 apps_smmu: iommu@15000000 {
5647 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5648 reg = <0 0x15000000 0 0x100000>;
5649
5650 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5651 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5652 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5653 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5654 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5655 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5656 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5657 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5658 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5659 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5660 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5661 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5662 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5663 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5664 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5665 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5666 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5667 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5668 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5669 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5670 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5671 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5672 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5673 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5674 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5675 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5676 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5677 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5678 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5679 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5680 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5681 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5682 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5690 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5691 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5692 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5693 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5694 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5695 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5696 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5697 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5698 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5699 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5700 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5701 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5702 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5703 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5704 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5705 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5706 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5707 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5708 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5709 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5710 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5711 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5712 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5713 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5714 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5715 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5716 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5717 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5718 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5719 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5720 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5721 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5722 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5723 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5724 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5725 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5726 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5727 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5728 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5729 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5730 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5731 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5732 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5733 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5734 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5735 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
5736 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5737 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5738 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5739 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5740 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5741 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5742 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5743 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5744 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5745 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5746 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
5747
5748 #iommu-cells = <2>;
5749 #global-interrupts = <1>;
5750 };
5751
5752 intc: interrupt-controller@17000000 {
5753 compatible = "arm,gic-v3";
5754 reg = <0 0x17000000 0 0x10000>, /* GICD */
5755 <0 0x17080000 0 0x480000>; /* GICR * 12 */
5756
5757 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5758
5759 #interrupt-cells = <3>;
5760 interrupt-controller;
5761
5762 #redistributor-regions = <1>;
5763 redistributor-stride = <0x0 0x40000>;
5764
5765 #address-cells = <2>;
5766 #size-cells = <2>;
5767 ranges;
5768
5769 gic_its: msi-controller@17040000 {
5770 compatible = "arm,gic-v3-its";
5771 reg = <0 0x17040000 0 0x40000>;
5772
5773 msi-controller;
5774 #msi-cells = <1>;
5775
5776 status = "disabled";
5777 };
5778 };
5779
5780 apps_rsc: rsc@17500000 {
5781 compatible = "qcom,rpmh-rsc";
5782 reg = <0 0x17500000 0 0x10000>,
5783 <0 0x17510000 0 0x10000>,
5784 <0 0x17520000 0 0x10000>;
5785 reg-names = "drv-0", "drv-1", "drv-2";
5786
5787 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5788 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5790 qcom,tcs-offset = <0xd00>;
5791 qcom,drv-id = <2>;
5792 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5793 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5794
5795 label = "apps_rsc";
5796 power-domains = <&SYSTEM_PD>;
5797
5798 apps_bcm_voter: bcm-voter {
5799 compatible = "qcom,bcm-voter";
5800 };
5801
5802 rpmhcc: clock-controller {
5803 compatible = "qcom,x1e80100-rpmh-clk";
5804
5805 clocks = <&xo_board>;
5806 clock-names = "xo";
5807
5808 #clock-cells = <1>;
5809 };
5810
5811 rpmhpd: power-controller {
5812 compatible = "qcom,x1e80100-rpmhpd";
5813
5814 operating-points-v2 = <&rpmhpd_opp_table>;
5815
5816 #power-domain-cells = <1>;
5817
5818 rpmhpd_opp_table: opp-table {
5819 compatible = "operating-points-v2";
5820
5821 rpmhpd_opp_ret: opp-16 {
5822 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5823 };
5824
5825 rpmhpd_opp_min_svs: opp-48 {
5826 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5827 };
5828
5829 rpmhpd_opp_low_svs_d2: opp-52 {
5830 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5831 };
5832
5833 rpmhpd_opp_low_svs_d1: opp-56 {
5834 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5835 };
5836
5837 rpmhpd_opp_low_svs_d0: opp-60 {
5838 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5839 };
5840
5841 rpmhpd_opp_low_svs: opp-64 {
5842 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5843 };
5844
5845 rpmhpd_opp_low_svs_l1: opp-80 {
5846 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5847 };
5848
5849 rpmhpd_opp_svs: opp-128 {
5850 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5851 };
5852
5853 rpmhpd_opp_svs_l0: opp-144 {
5854 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5855 };
5856
5857 rpmhpd_opp_svs_l1: opp-192 {
5858 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5859 };
5860
5861 rpmhpd_opp_nom: opp-256 {
5862 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5863 };
5864
5865 rpmhpd_opp_nom_l1: opp-320 {
5866 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5867 };
5868
5869 rpmhpd_opp_nom_l2: opp-336 {
5870 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5871 };
5872
5873 rpmhpd_opp_turbo: opp-384 {
5874 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5875 };
5876
5877 rpmhpd_opp_turbo_l1: opp-416 {
5878 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5879 };
5880 };
5881 };
5882 };
5883
5884 timer@17800000 {
5885 compatible = "arm,armv7-timer-mem";
5886 reg = <0 0x17800000 0 0x1000>;
5887
5888 #address-cells = <2>;
5889 #size-cells = <1>;
5890 ranges = <0 0 0 0 0x20000000>;
5891
5892 frame@17801000 {
5893 reg = <0 0x17801000 0x1000>,
5894 <0 0x17802000 0x1000>;
5895
5896 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5898
5899 frame-number = <0>;
5900 };
5901
5902 frame@17803000 {
5903 reg = <0 0x17803000 0x1000>;
5904
5905 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5906
5907 frame-number = <1>;
5908
5909 status = "disabled";
5910 };
5911
5912 frame@17805000 {
5913 reg = <0 0x17805000 0x1000>;
5914
5915 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5916
5917 frame-number = <2>;
5918
5919 status = "disabled";
5920 };
5921
5922 frame@17807000 {
5923 reg = <0 0x17807000 0x1000>;
5924
5925 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5926
5927 frame-number = <3>;
5928
5929 status = "disabled";
5930 };
5931
5932 frame@17809000 {
5933 reg = <0 0x17809000 0x1000>;
5934
5935 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5936
5937 frame-number = <4>;
5938
5939 status = "disabled";
5940 };
5941
5942 frame@1780b000 {
5943 reg = <0 0x1780b000 0x1000>;
5944
5945 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5946
5947 frame-number = <5>;
5948
5949 status = "disabled";
5950 };
5951
5952 frame@1780d000 {
5953 reg = <0 0x1780d000 0x1000>;
5954
5955 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5956
5957 frame-number = <6>;
5958
5959 status = "disabled";
5960 };
5961 };
5962
5963 pmu@24091000 {
5964 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5965 reg = <0 0x24091000 0 0x1000>;
5966
5967 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
5968
5969 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
5970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
5971
5972 operating-points-v2 = <&llcc_bwmon_opp_table>;
5973
5974 llcc_bwmon_opp_table: opp-table {
5975 compatible = "operating-points-v2";
5976
5977 opp-0 {
5978 opp-peak-kBps = <800000>;
5979 };
5980
5981 opp-1 {
5982 opp-peak-kBps = <2188000>;
5983 };
5984
5985 opp-2 {
5986 opp-peak-kBps = <3072000>;
5987 };
5988
5989 opp-3 {
5990 opp-peak-kBps = <6220800>;
5991 };
5992
5993 opp-4 {
5994 opp-peak-kBps = <6835200>;
5995 };
5996
5997 opp-5 {
5998 opp-peak-kBps = <8371200>;
5999 };
6000
6001 opp-6 {
6002 opp-peak-kBps = <10944000>;
6003 };
6004
6005 opp-7 {
6006 opp-peak-kBps = <12748800>;
6007 };
6008
6009 opp-8 {
6010 opp-peak-kBps = <14745600>;
6011 };
6012
6013 opp-9 {
6014 opp-peak-kBps = <16896000>;
6015 };
6016 };
6017 };
6018
6019 /* cluster0 */
6020 pmu@240b3400 {
6021 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6022 reg = <0 0x240b3400 0 0x600>;
6023
6024 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6025
6026 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6027 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6028
6029 operating-points-v2 = <&cpu_bwmon_opp_table>;
6030
6031 cpu_bwmon_opp_table: opp-table {
6032 compatible = "operating-points-v2";
6033
6034 opp-0 {
6035 opp-peak-kBps = <4800000>;
6036 };
6037
6038 opp-1 {
6039 opp-peak-kBps = <7464000>;
6040 };
6041
6042 opp-2 {
6043 opp-peak-kBps = <9600000>;
6044 };
6045
6046 opp-3 {
6047 opp-peak-kBps = <12896000>;
6048 };
6049
6050 opp-4 {
6051 opp-peak-kBps = <14928000>;
6052 };
6053
6054 opp-5 {
6055 opp-peak-kBps = <17064000>;
6056 };
6057 };
6058 };
6059
6060 /* cluster2 */
6061 pmu@240b5400 {
6062 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6063 reg = <0 0x240b5400 0 0x600>;
6064
6065 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6066
6067 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6068 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6069
6070 operating-points-v2 = <&cpu_bwmon_opp_table>;
6071 };
6072
6073 /* cluster1 */
6074 pmu@240b6400 {
6075 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6076 reg = <0 0x240b6400 0 0x600>;
6077
6078 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6079
6080 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6081 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6082
6083 operating-points-v2 = <&cpu_bwmon_opp_table>;
6084 };
6085
6086 system-cache-controller@25000000 {
6087 compatible = "qcom,x1e80100-llcc";
6088 reg = <0 0x25000000 0 0x200000>,
6089 <0 0x25200000 0 0x200000>,
6090 <0 0x25400000 0 0x200000>,
6091 <0 0x25600000 0 0x200000>,
6092 <0 0x25800000 0 0x200000>,
6093 <0 0x25a00000 0 0x200000>,
6094 <0 0x25c00000 0 0x200000>,
6095 <0 0x25e00000 0 0x200000>,
6096 <0 0x26000000 0 0x200000>,
6097 <0 0x26200000 0 0x200000>;
6098 reg-names = "llcc0_base",
6099 "llcc1_base",
6100 "llcc2_base",
6101 "llcc3_base",
6102 "llcc4_base",
6103 "llcc5_base",
6104 "llcc6_base",
6105 "llcc7_base",
6106 "llcc_broadcast_base",
6107 "llcc_broadcast_and_base";
6108 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
6109 };
6110
6111 remoteproc_adsp: remoteproc@30000000 {
6112 compatible = "qcom,x1e80100-adsp-pas";
6113 reg = <0 0x30000000 0 0x100>;
6114
6115 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6116 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
6117 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
6118 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
6119 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
6120 interrupt-names = "wdog",
6121 "fatal",
6122 "ready",
6123 "handover",
6124 "stop-ack";
6125
6126 clocks = <&rpmhcc RPMH_CXO_CLK>;
6127 clock-names = "xo";
6128
6129 power-domains = <&rpmhpd RPMHPD_LCX>,
6130 <&rpmhpd RPMHPD_LMX>;
6131 power-domain-names = "lcx",
6132 "lmx";
6133
6134 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
6135 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6136
6137 memory-region = <&adspslpi_mem>,
6138 <&q6_adsp_dtb_mem>;
6139
6140 qcom,qmp = <&aoss_qmp>;
6141
6142 qcom,smem-states = <&smp2p_adsp_out 0>;
6143 qcom,smem-state-names = "stop";
6144
6145 status = "disabled";
6146
6147 glink-edge {
6148 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6149 IPCC_MPROC_SIGNAL_GLINK_QMP
6150 IRQ_TYPE_EDGE_RISING>;
6151 mboxes = <&ipcc IPCC_CLIENT_LPASS
6152 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6153
6154 label = "lpass";
6155 qcom,remote-pid = <2>;
6156
6157 fastrpc {
6158 compatible = "qcom,fastrpc";
6159 qcom,glink-channels = "fastrpcglink-apps-dsp";
6160 label = "adsp";
6161 qcom,non-secure-domain;
6162 #address-cells = <1>;
6163 #size-cells = <0>;
6164
6165 compute-cb@3 {
6166 compatible = "qcom,fastrpc-compute-cb";
6167 reg = <3>;
6168 iommus = <&apps_smmu 0x1003 0x80>,
6169 <&apps_smmu 0x1063 0x0>;
6170 dma-coherent;
6171 };
6172
6173 compute-cb@4 {
6174 compatible = "qcom,fastrpc-compute-cb";
6175 reg = <4>;
6176 iommus = <&apps_smmu 0x1004 0x80>,
6177 <&apps_smmu 0x1064 0x0>;
6178 dma-coherent;
6179 };
6180
6181 compute-cb@5 {
6182 compatible = "qcom,fastrpc-compute-cb";
6183 reg = <5>;
6184 iommus = <&apps_smmu 0x1005 0x80>,
6185 <&apps_smmu 0x1065 0x0>;
6186 dma-coherent;
6187 };
6188
6189 compute-cb@6 {
6190 compatible = "qcom,fastrpc-compute-cb";
6191 reg = <6>;
6192 iommus = <&apps_smmu 0x1006 0x80>,
6193 <&apps_smmu 0x1066 0x0>;
6194 dma-coherent;
6195 };
6196
6197 compute-cb@7 {
6198 compatible = "qcom,fastrpc-compute-cb";
6199 reg = <7>;
6200 iommus = <&apps_smmu 0x1007 0x80>,
6201 <&apps_smmu 0x1067 0x0>;
6202 dma-coherent;
6203 };
6204 };
6205
6206 gpr {
6207 compatible = "qcom,gpr";
6208 qcom,glink-channels = "adsp_apps";
6209 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
6210 qcom,intents = <512 20>;
6211 #address-cells = <1>;
6212 #size-cells = <0>;
6213
6214 q6apm: service@1 {
6215 compatible = "qcom,q6apm";
6216 reg = <GPR_APM_MODULE_IID>;
6217 #sound-dai-cells = <0>;
6218 qcom,protection-domain = "avs/audio",
6219 "msm/adsp/audio_pd";
6220
6221 q6apmbedai: bedais {
6222 compatible = "qcom,q6apm-lpass-dais";
6223 #sound-dai-cells = <1>;
6224 };
6225
6226 q6apmdai: dais {
6227 compatible = "qcom,q6apm-dais";
6228 iommus = <&apps_smmu 0x1001 0x80>,
6229 <&apps_smmu 0x1061 0x0>;
6230 };
6231 };
6232
6233 q6prm: service@2 {
6234 compatible = "qcom,q6prm";
6235 reg = <GPR_PRM_MODULE_IID>;
6236 qcom,protection-domain = "avs/audio",
6237 "msm/adsp/audio_pd";
6238
6239 q6prmcc: clock-controller {
6240 compatible = "qcom,q6prm-lpass-clocks";
6241 #clock-cells = <2>;
6242 };
6243 };
6244 };
6245 };
6246 };
6247
6248 remoteproc_cdsp: remoteproc@32300000 {
6249 compatible = "qcom,x1e80100-cdsp-pas";
6250 reg = <0 0x32300000 0 0x1400000>;
6251
6252 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6253 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
6254 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
6255 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
6256 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
6257 interrupt-names = "wdog",
6258 "fatal",
6259 "ready",
6260 "handover",
6261 "stop-ack";
6262
6263 clocks = <&rpmhcc RPMH_CXO_CLK>;
6264 clock-names = "xo";
6265
6266 power-domains = <&rpmhpd RPMHPD_CX>,
6267 <&rpmhpd RPMHPD_MXC>,
6268 <&rpmhpd RPMHPD_NSP>;
6269 power-domain-names = "cx",
6270 "mxc",
6271 "nsp";
6272
6273 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
6274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6275
6276 memory-region = <&cdsp_mem>,
6277 <&q6_cdsp_dtb_mem>;
6278
6279 qcom,qmp = <&aoss_qmp>;
6280
6281 qcom,smem-states = <&smp2p_cdsp_out 0>;
6282 qcom,smem-state-names = "stop";
6283
6284 status = "disabled";
6285
6286 glink-edge {
6287 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6288 IPCC_MPROC_SIGNAL_GLINK_QMP
6289 IRQ_TYPE_EDGE_RISING>;
6290 mboxes = <&ipcc IPCC_CLIENT_CDSP
6291 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6292
6293 label = "cdsp";
6294 qcom,remote-pid = <5>;
6295
6296 fastrpc {
6297 compatible = "qcom,fastrpc";
6298 qcom,glink-channels = "fastrpcglink-apps-dsp";
6299 label = "cdsp";
6300 qcom,non-secure-domain;
6301 #address-cells = <1>;
6302 #size-cells = <0>;
6303
6304 compute-cb@1 {
6305 compatible = "qcom,fastrpc-compute-cb";
6306 reg = <1>;
6307 iommus = <&apps_smmu 0x0c01 0x20>;
6308 dma-coherent;
6309 };
6310
6311 compute-cb@2 {
6312 compatible = "qcom,fastrpc-compute-cb";
6313 reg = <2>;
6314 iommus = <&apps_smmu 0x0c02 0x20>;
6315 dma-coherent;
6316 };
6317
6318 compute-cb@3 {
6319 compatible = "qcom,fastrpc-compute-cb";
6320 reg = <3>;
6321 iommus = <&apps_smmu 0x0c03 0x20>;
6322 dma-coherent;
6323 };
6324
6325 compute-cb@4 {
6326 compatible = "qcom,fastrpc-compute-cb";
6327 reg = <4>;
6328 iommus = <&apps_smmu 0x0c04 0x20>;
6329 dma-coherent;
6330 };
6331
6332 compute-cb@5 {
6333 compatible = "qcom,fastrpc-compute-cb";
6334 reg = <5>;
6335 iommus = <&apps_smmu 0x0c05 0x20>;
6336 dma-coherent;
6337 };
6338
6339 compute-cb@6 {
6340 compatible = "qcom,fastrpc-compute-cb";
6341 reg = <6>;
6342 iommus = <&apps_smmu 0x0c06 0x20>;
6343 dma-coherent;
6344 };
6345
6346 compute-cb@7 {
6347 compatible = "qcom,fastrpc-compute-cb";
6348 reg = <7>;
6349 iommus = <&apps_smmu 0x0c07 0x20>;
6350 dma-coherent;
6351 };
6352
6353 compute-cb@8 {
6354 compatible = "qcom,fastrpc-compute-cb";
6355 reg = <8>;
6356 iommus = <&apps_smmu 0x0c08 0x20>;
6357 dma-coherent;
6358 };
6359
6360 /* note: compute-cb@9 is secure */
6361
6362 compute-cb@10 {
6363 compatible = "qcom,fastrpc-compute-cb";
6364 reg = <10>;
6365 iommus = <&apps_smmu 0x0c0c 0x20>;
6366 dma-coherent;
6367 };
6368
6369 compute-cb@11 {
6370 compatible = "qcom,fastrpc-compute-cb";
6371 reg = <11>;
6372 iommus = <&apps_smmu 0x0c0d 0x20>;
6373 dma-coherent;
6374 };
6375
6376 compute-cb@12 {
6377 compatible = "qcom,fastrpc-compute-cb";
6378 reg = <12>;
6379 iommus = <&apps_smmu 0x0c0e 0x20>;
6380 dma-coherent;
6381 };
6382
6383 compute-cb@13 {
6384 compatible = "qcom,fastrpc-compute-cb";
6385 reg = <13>;
6386 iommus = <&apps_smmu 0x0c0f 0x20>;
6387 dma-coherent;
6388 };
6389 };
6390 };
6391 };
6392 };
6393
6394 timer {
6395 compatible = "arm,armv8-timer";
6396
6397 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6398 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6399 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6400 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6401 };
6402
6403 thermal-zones {
6404 aoss0-thermal {
6405 thermal-sensors = <&tsens0 0>;
6406
6407 trips {
6408 trip-point0 {
6409 temperature = <90000>;
6410 hysteresis = <2000>;
6411 type = "hot";
6412 };
6413
6414 aoss0-critical {
6415 temperature = <125000>;
6416 hysteresis = <0>;
6417 type = "critical";
6418 };
6419 };
6420 };
6421
6422 cpu0-0-top-thermal {
6423 polling-delay-passive = <250>;
6424
6425 thermal-sensors = <&tsens0 1>;
6426
6427 trips {
6428 trip-point0 {
6429 temperature = <90000>;
6430 hysteresis = <2000>;
6431 type = "passive";
6432 };
6433
6434 trip-point1 {
6435 temperature = <95000>;
6436 hysteresis = <2000>;
6437 type = "passive";
6438 };
6439
6440 cpu-critical {
6441 temperature = <110000>;
6442 hysteresis = <1000>;
6443 type = "critical";
6444 };
6445 };
6446 };
6447
6448 cpu0-0-btm-thermal {
6449 polling-delay-passive = <250>;
6450
6451 thermal-sensors = <&tsens0 2>;
6452
6453 trips {
6454 trip-point0 {
6455 temperature = <90000>;
6456 hysteresis = <2000>;
6457 type = "passive";
6458 };
6459
6460 trip-point1 {
6461 temperature = <95000>;
6462 hysteresis = <2000>;
6463 type = "passive";
6464 };
6465
6466 cpu-critical {
6467 temperature = <110000>;
6468 hysteresis = <1000>;
6469 type = "critical";
6470 };
6471 };
6472 };
6473
6474 cpu0-1-top-thermal {
6475 polling-delay-passive = <250>;
6476
6477 thermal-sensors = <&tsens0 3>;
6478
6479 trips {
6480 trip-point0 {
6481 temperature = <90000>;
6482 hysteresis = <2000>;
6483 type = "passive";
6484 };
6485
6486 trip-point1 {
6487 temperature = <95000>;
6488 hysteresis = <2000>;
6489 type = "passive";
6490 };
6491
6492 cpu-critical {
6493 temperature = <110000>;
6494 hysteresis = <1000>;
6495 type = "critical";
6496 };
6497 };
6498 };
6499
6500 cpu0-1-btm-thermal {
6501 polling-delay-passive = <250>;
6502
6503 thermal-sensors = <&tsens0 4>;
6504
6505 trips {
6506 trip-point0 {
6507 temperature = <90000>;
6508 hysteresis = <2000>;
6509 type = "passive";
6510 };
6511
6512 trip-point1 {
6513 temperature = <95000>;
6514 hysteresis = <2000>;
6515 type = "passive";
6516 };
6517
6518 cpu-critical {
6519 temperature = <110000>;
6520 hysteresis = <1000>;
6521 type = "critical";
6522 };
6523 };
6524 };
6525
6526 cpu0-2-top-thermal {
6527 polling-delay-passive = <250>;
6528
6529 thermal-sensors = <&tsens0 5>;
6530
6531 trips {
6532 trip-point0 {
6533 temperature = <90000>;
6534 hysteresis = <2000>;
6535 type = "passive";
6536 };
6537
6538 trip-point1 {
6539 temperature = <95000>;
6540 hysteresis = <2000>;
6541 type = "passive";
6542 };
6543
6544 cpu-critical {
6545 temperature = <110000>;
6546 hysteresis = <1000>;
6547 type = "critical";
6548 };
6549 };
6550 };
6551
6552 cpu0-2-btm-thermal {
6553 polling-delay-passive = <250>;
6554
6555 thermal-sensors = <&tsens0 6>;
6556
6557 trips {
6558 trip-point0 {
6559 temperature = <90000>;
6560 hysteresis = <2000>;
6561 type = "passive";
6562 };
6563
6564 trip-point1 {
6565 temperature = <95000>;
6566 hysteresis = <2000>;
6567 type = "passive";
6568 };
6569
6570 cpu-critical {
6571 temperature = <110000>;
6572 hysteresis = <1000>;
6573 type = "critical";
6574 };
6575 };
6576 };
6577
6578 cpu0-3-top-thermal {
6579 polling-delay-passive = <250>;
6580
6581 thermal-sensors = <&tsens0 7>;
6582
6583 trips {
6584 trip-point0 {
6585 temperature = <90000>;
6586 hysteresis = <2000>;
6587 type = "passive";
6588 };
6589
6590 trip-point1 {
6591 temperature = <95000>;
6592 hysteresis = <2000>;
6593 type = "passive";
6594 };
6595
6596 cpu-critical {
6597 temperature = <110000>;
6598 hysteresis = <1000>;
6599 type = "critical";
6600 };
6601 };
6602 };
6603
6604 cpu0-3-btm-thermal {
6605 polling-delay-passive = <250>;
6606
6607 thermal-sensors = <&tsens0 8>;
6608
6609 trips {
6610 trip-point0 {
6611 temperature = <90000>;
6612 hysteresis = <2000>;
6613 type = "passive";
6614 };
6615
6616 trip-point1 {
6617 temperature = <95000>;
6618 hysteresis = <2000>;
6619 type = "passive";
6620 };
6621
6622 cpu-critical {
6623 temperature = <110000>;
6624 hysteresis = <1000>;
6625 type = "critical";
6626 };
6627 };
6628 };
6629
6630 cpuss0-top-thermal {
6631 thermal-sensors = <&tsens0 9>;
6632
6633 trips {
6634 trip-point0 {
6635 temperature = <90000>;
6636 hysteresis = <2000>;
6637 type = "hot";
6638 };
6639
6640 cpuss2-critical {
6641 temperature = <125000>;
6642 hysteresis = <0>;
6643 type = "critical";
6644 };
6645 };
6646 };
6647
6648 cpuss0-btm-thermal {
6649 thermal-sensors = <&tsens0 10>;
6650
6651 trips {
6652 trip-point0 {
6653 temperature = <90000>;
6654 hysteresis = <2000>;
6655 type = "hot";
6656 };
6657
6658 cpuss2-critical {
6659 temperature = <125000>;
6660 hysteresis = <0>;
6661 type = "critical";
6662 };
6663 };
6664 };
6665
6666 mem-thermal {
6667 thermal-sensors = <&tsens0 11>;
6668
6669 trips {
6670 trip-point0 {
6671 temperature = <90000>;
6672 hysteresis = <2000>;
6673 type = "hot";
6674 };
6675
6676 mem-critical {
6677 temperature = <125000>;
6678 hysteresis = <0>;
6679 type = "critical";
6680 };
6681 };
6682 };
6683
6684 video-thermal {
6685 polling-delay-passive = <250>;
6686
6687 thermal-sensors = <&tsens0 12>;
6688
6689 trips {
6690 trip-point0 {
6691 temperature = <125000>;
6692 hysteresis = <1000>;
6693 type = "passive";
6694 };
6695 };
6696 };
6697
6698 aoss1-thermal {
6699 thermal-sensors = <&tsens1 0>;
6700
6701 trips {
6702 trip-point0 {
6703 temperature = <90000>;
6704 hysteresis = <2000>;
6705 type = "hot";
6706 };
6707
6708 aoss0-critical {
6709 temperature = <125000>;
6710 hysteresis = <0>;
6711 type = "critical";
6712 };
6713 };
6714 };
6715
6716 cpu1-0-top-thermal {
6717 polling-delay-passive = <250>;
6718
6719 thermal-sensors = <&tsens1 1>;
6720
6721 trips {
6722 trip-point0 {
6723 temperature = <90000>;
6724 hysteresis = <2000>;
6725 type = "passive";
6726 };
6727
6728 trip-point1 {
6729 temperature = <95000>;
6730 hysteresis = <2000>;
6731 type = "passive";
6732 };
6733
6734 cpu-critical {
6735 temperature = <110000>;
6736 hysteresis = <1000>;
6737 type = "critical";
6738 };
6739 };
6740 };
6741
6742 cpu1-0-btm-thermal {
6743 polling-delay-passive = <250>;
6744
6745 thermal-sensors = <&tsens1 2>;
6746
6747 trips {
6748 trip-point0 {
6749 temperature = <90000>;
6750 hysteresis = <2000>;
6751 type = "passive";
6752 };
6753
6754 trip-point1 {
6755 temperature = <95000>;
6756 hysteresis = <2000>;
6757 type = "passive";
6758 };
6759
6760 cpu-critical {
6761 temperature = <110000>;
6762 hysteresis = <1000>;
6763 type = "critical";
6764 };
6765 };
6766 };
6767
6768 cpu1-1-top-thermal {
6769 polling-delay-passive = <250>;
6770
6771 thermal-sensors = <&tsens1 3>;
6772
6773 trips {
6774 trip-point0 {
6775 temperature = <90000>;
6776 hysteresis = <2000>;
6777 type = "passive";
6778 };
6779
6780 trip-point1 {
6781 temperature = <95000>;
6782 hysteresis = <2000>;
6783 type = "passive";
6784 };
6785
6786 cpu-critical {
6787 temperature = <110000>;
6788 hysteresis = <1000>;
6789 type = "critical";
6790 };
6791 };
6792 };
6793
6794 cpu1-1-btm-thermal {
6795 polling-delay-passive = <250>;
6796
6797 thermal-sensors = <&tsens1 4>;
6798
6799 trips {
6800 trip-point0 {
6801 temperature = <90000>;
6802 hysteresis = <2000>;
6803 type = "passive";
6804 };
6805
6806 trip-point1 {
6807 temperature = <95000>;
6808 hysteresis = <2000>;
6809 type = "passive";
6810 };
6811
6812 cpu-critical {
6813 temperature = <110000>;
6814 hysteresis = <1000>;
6815 type = "critical";
6816 };
6817 };
6818 };
6819
6820 cpu1-2-top-thermal {
6821 polling-delay-passive = <250>;
6822
6823 thermal-sensors = <&tsens1 5>;
6824
6825 trips {
6826 trip-point0 {
6827 temperature = <90000>;
6828 hysteresis = <2000>;
6829 type = "passive";
6830 };
6831
6832 trip-point1 {
6833 temperature = <95000>;
6834 hysteresis = <2000>;
6835 type = "passive";
6836 };
6837
6838 cpu-critical {
6839 temperature = <110000>;
6840 hysteresis = <1000>;
6841 type = "critical";
6842 };
6843 };
6844 };
6845
6846 cpu1-2-btm-thermal {
6847 polling-delay-passive = <250>;
6848
6849 thermal-sensors = <&tsens1 6>;
6850
6851 trips {
6852 trip-point0 {
6853 temperature = <90000>;
6854 hysteresis = <2000>;
6855 type = "passive";
6856 };
6857
6858 trip-point1 {
6859 temperature = <95000>;
6860 hysteresis = <2000>;
6861 type = "passive";
6862 };
6863
6864 cpu-critical {
6865 temperature = <110000>;
6866 hysteresis = <1000>;
6867 type = "critical";
6868 };
6869 };
6870 };
6871
6872 cpu1-3-top-thermal {
6873 polling-delay-passive = <250>;
6874
6875 thermal-sensors = <&tsens1 7>;
6876
6877 trips {
6878 trip-point0 {
6879 temperature = <90000>;
6880 hysteresis = <2000>;
6881 type = "passive";
6882 };
6883
6884 trip-point1 {
6885 temperature = <95000>;
6886 hysteresis = <2000>;
6887 type = "passive";
6888 };
6889
6890 cpu-critical {
6891 temperature = <110000>;
6892 hysteresis = <1000>;
6893 type = "critical";
6894 };
6895 };
6896 };
6897
6898 cpu1-3-btm-thermal {
6899 polling-delay-passive = <250>;
6900
6901 thermal-sensors = <&tsens1 8>;
6902
6903 trips {
6904 trip-point0 {
6905 temperature = <90000>;
6906 hysteresis = <2000>;
6907 type = "passive";
6908 };
6909
6910 trip-point1 {
6911 temperature = <95000>;
6912 hysteresis = <2000>;
6913 type = "passive";
6914 };
6915
6916 cpu-critical {
6917 temperature = <110000>;
6918 hysteresis = <1000>;
6919 type = "critical";
6920 };
6921 };
6922 };
6923
6924 cpuss1-top-thermal {
6925 thermal-sensors = <&tsens1 9>;
6926
6927 trips {
6928 trip-point0 {
6929 temperature = <90000>;
6930 hysteresis = <2000>;
6931 type = "hot";
6932 };
6933
6934 cpuss2-critical {
6935 temperature = <125000>;
6936 hysteresis = <0>;
6937 type = "critical";
6938 };
6939 };
6940 };
6941
6942 cpuss1-btm-thermal {
6943 thermal-sensors = <&tsens1 10>;
6944
6945 trips {
6946 trip-point0 {
6947 temperature = <90000>;
6948 hysteresis = <2000>;
6949 type = "hot";
6950 };
6951
6952 cpuss2-critical {
6953 temperature = <125000>;
6954 hysteresis = <0>;
6955 type = "critical";
6956 };
6957 };
6958 };
6959
6960 aoss2-thermal {
6961 thermal-sensors = <&tsens2 0>;
6962
6963 trips {
6964 trip-point0 {
6965 temperature = <90000>;
6966 hysteresis = <2000>;
6967 type = "hot";
6968 };
6969
6970 aoss0-critical {
6971 temperature = <125000>;
6972 hysteresis = <0>;
6973 type = "critical";
6974 };
6975 };
6976 };
6977
6978 cpu2-0-top-thermal {
6979 polling-delay-passive = <250>;
6980
6981 thermal-sensors = <&tsens2 1>;
6982
6983 trips {
6984 trip-point0 {
6985 temperature = <90000>;
6986 hysteresis = <2000>;
6987 type = "passive";
6988 };
6989
6990 trip-point1 {
6991 temperature = <95000>;
6992 hysteresis = <2000>;
6993 type = "passive";
6994 };
6995
6996 cpu-critical {
6997 temperature = <110000>;
6998 hysteresis = <1000>;
6999 type = "critical";
7000 };
7001 };
7002 };
7003
7004 cpu2-0-btm-thermal {
7005 polling-delay-passive = <250>;
7006
7007 thermal-sensors = <&tsens2 2>;
7008
7009 trips {
7010 trip-point0 {
7011 temperature = <90000>;
7012 hysteresis = <2000>;
7013 type = "passive";
7014 };
7015
7016 trip-point1 {
7017 temperature = <95000>;
7018 hysteresis = <2000>;
7019 type = "passive";
7020 };
7021
7022 cpu-critical {
7023 temperature = <110000>;
7024 hysteresis = <1000>;
7025 type = "critical";
7026 };
7027 };
7028 };
7029
7030 cpu2-1-top-thermal {
7031 polling-delay-passive = <250>;
7032
7033 thermal-sensors = <&tsens2 3>;
7034
7035 trips {
7036 trip-point0 {
7037 temperature = <90000>;
7038 hysteresis = <2000>;
7039 type = "passive";
7040 };
7041
7042 trip-point1 {
7043 temperature = <95000>;
7044 hysteresis = <2000>;
7045 type = "passive";
7046 };
7047
7048 cpu-critical {
7049 temperature = <110000>;
7050 hysteresis = <1000>;
7051 type = "critical";
7052 };
7053 };
7054 };
7055
7056 cpu2-1-btm-thermal {
7057 polling-delay-passive = <250>;
7058
7059 thermal-sensors = <&tsens2 4>;
7060
7061 trips {
7062 trip-point0 {
7063 temperature = <90000>;
7064 hysteresis = <2000>;
7065 type = "passive";
7066 };
7067
7068 trip-point1 {
7069 temperature = <95000>;
7070 hysteresis = <2000>;
7071 type = "passive";
7072 };
7073
7074 cpu-critical {
7075 temperature = <110000>;
7076 hysteresis = <1000>;
7077 type = "critical";
7078 };
7079 };
7080 };
7081
7082 cpu2-2-top-thermal {
7083 polling-delay-passive = <250>;
7084
7085 thermal-sensors = <&tsens2 5>;
7086
7087 trips {
7088 trip-point0 {
7089 temperature = <90000>;
7090 hysteresis = <2000>;
7091 type = "passive";
7092 };
7093
7094 trip-point1 {
7095 temperature = <95000>;
7096 hysteresis = <2000>;
7097 type = "passive";
7098 };
7099
7100 cpu-critical {
7101 temperature = <110000>;
7102 hysteresis = <1000>;
7103 type = "critical";
7104 };
7105 };
7106 };
7107
7108 cpu2-2-btm-thermal {
7109 polling-delay-passive = <250>;
7110
7111 thermal-sensors = <&tsens2 6>;
7112
7113 trips {
7114 trip-point0 {
7115 temperature = <90000>;
7116 hysteresis = <2000>;
7117 type = "passive";
7118 };
7119
7120 trip-point1 {
7121 temperature = <95000>;
7122 hysteresis = <2000>;
7123 type = "passive";
7124 };
7125
7126 cpu-critical {
7127 temperature = <110000>;
7128 hysteresis = <1000>;
7129 type = "critical";
7130 };
7131 };
7132 };
7133
7134 cpu2-3-top-thermal {
7135 polling-delay-passive = <250>;
7136
7137 thermal-sensors = <&tsens2 7>;
7138
7139 trips {
7140 trip-point0 {
7141 temperature = <90000>;
7142 hysteresis = <2000>;
7143 type = "passive";
7144 };
7145
7146 trip-point1 {
7147 temperature = <95000>;
7148 hysteresis = <2000>;
7149 type = "passive";
7150 };
7151
7152 cpu-critical {
7153 temperature = <110000>;
7154 hysteresis = <1000>;
7155 type = "critical";
7156 };
7157 };
7158 };
7159
7160 cpu2-3-btm-thermal {
7161 polling-delay-passive = <250>;
7162
7163 thermal-sensors = <&tsens2 8>;
7164
7165 trips {
7166 trip-point0 {
7167 temperature = <90000>;
7168 hysteresis = <2000>;
7169 type = "passive";
7170 };
7171
7172 trip-point1 {
7173 temperature = <95000>;
7174 hysteresis = <2000>;
7175 type = "passive";
7176 };
7177
7178 cpu-critical {
7179 temperature = <110000>;
7180 hysteresis = <1000>;
7181 type = "critical";
7182 };
7183 };
7184 };
7185
7186 cpuss2-top-thermal {
7187 thermal-sensors = <&tsens2 9>;
7188
7189 trips {
7190 trip-point0 {
7191 temperature = <90000>;
7192 hysteresis = <2000>;
7193 type = "hot";
7194 };
7195
7196 cpuss2-critical {
7197 temperature = <125000>;
7198 hysteresis = <0>;
7199 type = "critical";
7200 };
7201 };
7202 };
7203
7204 cpuss2-btm-thermal {
7205 thermal-sensors = <&tsens2 10>;
7206
7207 trips {
7208 trip-point0 {
7209 temperature = <90000>;
7210 hysteresis = <2000>;
7211 type = "hot";
7212 };
7213
7214 cpuss2-critical {
7215 temperature = <125000>;
7216 hysteresis = <0>;
7217 type = "critical";
7218 };
7219 };
7220 };
7221
7222 aoss3-thermal {
7223 thermal-sensors = <&tsens3 0>;
7224
7225 trips {
7226 trip-point0 {
7227 temperature = <90000>;
7228 hysteresis = <2000>;
7229 type = "hot";
7230 };
7231
7232 aoss0-critical {
7233 temperature = <125000>;
7234 hysteresis = <0>;
7235 type = "critical";
7236 };
7237 };
7238 };
7239
7240 nsp0-thermal {
7241 thermal-sensors = <&tsens3 1>;
7242
7243 trips {
7244 trip-point0 {
7245 temperature = <90000>;
7246 hysteresis = <2000>;
7247 type = "hot";
7248 };
7249
7250 nsp0-critical {
7251 temperature = <125000>;
7252 hysteresis = <0>;
7253 type = "critical";
7254 };
7255 };
7256 };
7257
7258 nsp1-thermal {
7259 thermal-sensors = <&tsens3 2>;
7260
7261 trips {
7262 trip-point0 {
7263 temperature = <90000>;
7264 hysteresis = <2000>;
7265 type = "hot";
7266 };
7267
7268 nsp1-critical {
7269 temperature = <125000>;
7270 hysteresis = <0>;
7271 type = "critical";
7272 };
7273 };
7274 };
7275
7276 nsp2-thermal {
7277 thermal-sensors = <&tsens3 3>;
7278
7279 trips {
7280 trip-point0 {
7281 temperature = <90000>;
7282 hysteresis = <2000>;
7283 type = "hot";
7284 };
7285
7286 nsp2-critical {
7287 temperature = <125000>;
7288 hysteresis = <0>;
7289 type = "critical";
7290 };
7291 };
7292 };
7293
7294 nsp3-thermal {
7295 thermal-sensors = <&tsens3 4>;
7296
7297 trips {
7298 trip-point0 {
7299 temperature = <90000>;
7300 hysteresis = <2000>;
7301 type = "hot";
7302 };
7303
7304 nsp3-critical {
7305 temperature = <125000>;
7306 hysteresis = <0>;
7307 type = "critical";
7308 };
7309 };
7310 };
7311
7312 gpuss-0-thermal {
7313 polling-delay-passive = <10>;
7314
7315 thermal-sensors = <&tsens3 5>;
7316
7317 trips {
7318 trip-point0 {
7319 temperature = <85000>;
7320 hysteresis = <1000>;
7321 type = "passive";
7322 };
7323
7324 trip-point1 {
7325 temperature = <90000>;
7326 hysteresis = <1000>;
7327 type = "hot";
7328 };
7329
7330 trip-point2 {
7331 temperature = <125000>;
7332 hysteresis = <1000>;
7333 type = "critical";
7334 };
7335 };
7336 };
7337
7338 gpuss-1-thermal {
7339 polling-delay-passive = <10>;
7340
7341 thermal-sensors = <&tsens3 6>;
7342
7343 trips {
7344 trip-point0 {
7345 temperature = <85000>;
7346 hysteresis = <1000>;
7347 type = "passive";
7348 };
7349
7350 trip-point1 {
7351 temperature = <90000>;
7352 hysteresis = <1000>;
7353 type = "hot";
7354 };
7355
7356 trip-point2 {
7357 temperature = <125000>;
7358 hysteresis = <1000>;
7359 type = "critical";
7360 };
7361 };
7362 };
7363
7364 gpuss-2-thermal {
7365 polling-delay-passive = <10>;
7366
7367 thermal-sensors = <&tsens3 7>;
7368
7369 trips {
7370 trip-point0 {
7371 temperature = <85000>;
7372 hysteresis = <1000>;
7373 type = "passive";
7374 };
7375
7376 trip-point1 {
7377 temperature = <90000>;
7378 hysteresis = <1000>;
7379 type = "hot";
7380 };
7381
7382 trip-point2 {
7383 temperature = <125000>;
7384 hysteresis = <1000>;
7385 type = "critical";
7386 };
7387 };
7388 };
7389
7390 gpuss-3-thermal {
7391 polling-delay-passive = <10>;
7392
7393 thermal-sensors = <&tsens3 8>;
7394
7395 trips {
7396 trip-point0 {
7397 temperature = <85000>;
7398 hysteresis = <1000>;
7399 type = "passive";
7400 };
7401
7402 trip-point1 {
7403 temperature = <90000>;
7404 hysteresis = <1000>;
7405 type = "hot";
7406 };
7407
7408 trip-point2 {
7409 temperature = <125000>;
7410 hysteresis = <1000>;
7411 type = "critical";
7412 };
7413 };
7414 };
7415
7416 gpuss-4-thermal {
7417 polling-delay-passive = <10>;
7418
7419 thermal-sensors = <&tsens3 9>;
7420
7421 trips {
7422 trip-point0 {
7423 temperature = <85000>;
7424 hysteresis = <1000>;
7425 type = "passive";
7426 };
7427
7428 trip-point1 {
7429 temperature = <90000>;
7430 hysteresis = <1000>;
7431 type = "hot";
7432 };
7433
7434 trip-point2 {
7435 temperature = <125000>;
7436 hysteresis = <1000>;
7437 type = "critical";
7438 };
7439 };
7440 };
7441
7442 gpuss-5-thermal {
7443 polling-delay-passive = <10>;
7444
7445 thermal-sensors = <&tsens3 10>;
7446
7447 trips {
7448 trip-point0 {
7449 temperature = <85000>;
7450 hysteresis = <1000>;
7451 type = "passive";
7452 };
7453
7454 trip-point1 {
7455 temperature = <90000>;
7456 hysteresis = <1000>;
7457 type = "hot";
7458 };
7459
7460 trip-point2 {
7461 temperature = <125000>;
7462 hysteresis = <1000>;
7463 type = "critical";
7464 };
7465 };
7466 };
7467
7468 gpuss-6-thermal {
7469 polling-delay-passive = <10>;
7470
7471 thermal-sensors = <&tsens3 11>;
7472
7473 trips {
7474 trip-point0 {
7475 temperature = <85000>;
7476 hysteresis = <1000>;
7477 type = "passive";
7478 };
7479
7480 trip-point1 {
7481 temperature = <90000>;
7482 hysteresis = <1000>;
7483 type = "hot";
7484 };
7485
7486 trip-point2 {
7487 temperature = <125000>;
7488 hysteresis = <1000>;
7489 type = "critical";
7490 };
7491 };
7492 };
7493
7494 gpuss-7-thermal {
7495 polling-delay-passive = <10>;
7496
7497 thermal-sensors = <&tsens3 12>;
7498
7499 trips {
7500 trip-point0 {
7501 temperature = <85000>;
7502 hysteresis = <1000>;
7503 type = "passive";
7504 };
7505
7506 trip-point1 {
7507 temperature = <90000>;
7508 hysteresis = <1000>;
7509 type = "hot";
7510 };
7511
7512 trip-point2 {
7513 temperature = <125000>;
7514 hysteresis = <1000>;
7515 type = "critical";
7516 };
7517 };
7518 };
7519
7520 camera0-thermal {
7521 thermal-sensors = <&tsens3 13>;
7522
7523 trips {
7524 trip-point0 {
7525 temperature = <90000>;
7526 hysteresis = <2000>;
7527 type = "hot";
7528 };
7529
7530 camera0-critical {
7531 temperature = <115000>;
7532 hysteresis = <0>;
7533 type = "critical";
7534 };
7535 };
7536 };
7537
7538 camera1-thermal {
7539 thermal-sensors = <&tsens3 14>;
7540
7541 trips {
7542 trip-point0 {
7543 temperature = <90000>;
7544 hysteresis = <2000>;
7545 type = "hot";
7546 };
7547
7548 camera0-critical {
7549 temperature = <115000>;
7550 hysteresis = <0>;
7551 type = "critical";
7552 };
7553 };
7554 };
7555 };
7556 };
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