1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the RZ/V2H EVK board
4 *
5 * Copyright (C) 2024 Renesas Electronics Corp.
6 */
7
8 /dts-v1/;
9
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "r9a09g057.dtsi"
13
14 / {
15 model = "Renesas RZ/V2H EVK Board based on r9a09g057h44";
16 compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 i2c6 = &i2c6;
24 i2c7 = &i2c7;
25 i2c8 = &i2c8;
26 mmc1 = &sdhi1;
27 serial0 = &scif;
28 };
29
30 chosen {
31 bootargs = "ignore_loglevel";
32 stdout-path = "serial0:115200n8";
33 };
34
35 memory@48000000 {
36 device_type = "memory";
37 /* first 128MB is reserved for secure area. */
38 reg = <0x0 0x48000000 0x1 0xF8000000>;
39 };
40
41 memory@240000000 {
42 device_type = "memory";
43 reg = <0x2 0x40000000 0x2 0x00000000>;
44 };
45
46 reg_3p3v: regulator1 {
47 compatible = "regulator-fixed";
48
49 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-boot-on;
53 regulator-always-on;
54 };
55
56 vqmmc_sdhi1: regulator-vccq-sdhi1 {
57 compatible = "regulator-gpio";
58 regulator-name = "SDHI1 VccQ";
59 gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <3300000>;
62 gpios-states = <0>;
63 states = <3300000 0>, <1800000 1>;
64 };
65 };
66
67 &audio_extal_clk {
68 clock-frequency = <22579200>;
69 };
70
71 &i2c0 {
72 pinctrl-0 = <&i2c0_pins>;
73 pinctrl-names = "default";
74 clock-frequency = <400000>;
75
76 status = "okay";
77 };
78
79 &i2c1 {
80 pinctrl-0 = <&i2c1_pins>;
81 pinctrl-names = "default";
82 clock-frequency = <400000>;
83
84 status = "okay";
85 };
86
87 &i2c2 {
88 pinctrl-0 = <&i2c2_pins>;
89 pinctrl-names = "default";
90 clock-frequency = <400000>;
91
92 status = "okay";
93 };
94
95 &i2c3 {
96 pinctrl-0 = <&i2c3_pins>;
97 pinctrl-names = "default";
98 clock-frequency = <400000>;
99
100 status = "okay";
101 };
102
103 &i2c6 {
104 pinctrl-0 = <&i2c6_pins>;
105 pinctrl-names = "default";
106 clock-frequency = <400000>;
107
108 status = "okay";
109 };
110
111 &i2c7 {
112 pinctrl-0 = <&i2c7_pins>;
113 pinctrl-names = "default";
114 clock-frequency = <400000>;
115
116 status = "okay";
117 };
118
119 &i2c8 {
120 pinctrl-0 = <&i2c8_pins>;
121 pinctrl-names = "default";
122 clock-frequency = <400000>;
123
124 status = "okay";
125 };
126
127 &ostm0 {
128 status = "okay";
129 };
130
131 &ostm1 {
132 status = "okay";
133 };
134
135 &ostm2 {
136 status = "okay";
137 };
138
139 &ostm3 {
140 status = "okay";
141 };
142
143 &ostm4 {
144 status = "okay";
145 };
146
147 &ostm5 {
148 status = "okay";
149 };
150
151 &ostm6 {
152 status = "okay";
153 };
154
155 &ostm7 {
156 status = "okay";
157 };
158
159 &pinctrl {
160 i2c0_pins: i2c0 {
161 pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
162 <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
163 };
164
165 i2c1_pins: i2c1 {
166 pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
167 <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
168 };
169
170 i2c2_pins: i2c2 {
171 pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
172 <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
173 };
174
175 i2c3_pins: i2c3 {
176 pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
177 <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
178 };
179
180 i2c6_pins: i2c6 {
181 pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
182 <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
183 };
184
185 i2c7_pins: i2c7 {
186 pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
187 <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
188 };
189
190 i2c8_pins: i2c8 {
191 pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
192 <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
193 };
194
195 scif_pins: scif {
196 pins = "SCIF_TXD", "SCIF_RXD";
197 renesas,output-impedance = <1>;
198 };
199
200 sd1-pwr-en-hog {
201 gpio-hog;
202 gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>;
203 output-high;
204 line-name = "sd1_pwr_en";
205 };
206
207 sdhi1_pins: sd1 {
208 sd1_dat_cmd {
209 pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
210 input-enable;
211 renesas,output-impedance = <3>;
212 slew-rate = <0>;
213 };
214
215 sd1_clk {
216 pins = "SD1CLK";
217 renesas,output-impedance = <3>;
218 slew-rate = <0>;
219 };
220
221 sd1_cd {
222 pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
223 };
224 };
225 };
226
227 &qextal_clk {
228 clock-frequency = <24000000>;
229 };
230
231 &rtxin_clk {
232 clock-frequency = <32768>;
233 };
234
235 &scif {
236 pinctrl-0 = <&scif_pins>;
237 pinctrl-names = "default";
238
239 status = "okay";
240 };
241
242 &sdhi1 {
243 pinctrl-0 = <&sdhi1_pins>;
244 pinctrl-1 = <&sdhi1_pins>;
245 pinctrl-names = "default", "state_uhs";
246 vmmc-supply = <®_3p3v>;
247 vqmmc-supply = <&vqmmc_sdhi1>;
248 bus-width = <4>;
249 sd-uhs-sdr50;
250 sd-uhs-sdr104;
251 status = "okay";
252 };
253
254 &wdt1 {
255 status = "okay";
256 };
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