1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11 / {
12 aliases {
13 serial1 = &scif2;
14 i2c3 = &i2c3;
15 };
16
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
21 };
22
23 hdmi-out {
24 compatible = "hdmi-connector";
25 type = "d";
26
27 port {
28 hdmi_con_out: endpoint {
29 remote-endpoint = <&adv7535_out>;
30 };
31 };
32 };
33
34 sound_card {
35 compatible = "audio-graph-card";
36 label = "HDMI-Audio";
37 dais = <&i2s2_port>;
38 };
39 };
40
41 &cpu_dai {
42 sound-dai = <&ssi0>;
43 };
44
45 &dsi {
46 status = "okay";
47
48 ports {
49 port@1 {
50 dsi0_out: endpoint {
51 data-lanes = <1 2 3 4>;
52 remote-endpoint = <&adv7535_in>;
53 };
54 };
55 };
56 };
57
58 &du {
59 status = "okay";
60 };
61
62 &i2c1 {
63 adv7535: hdmi@3d {
64 compatible = "adi,adv7535";
65 reg = <0x3d>;
66
67 interrupt-parent = <&pinctrl>;
68 interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
69 clocks = <&osc1>;
70 clock-names = "cec";
71 avdd-supply = <®_1p8v>;
72 dvdd-supply = <®_1p8v>;
73 pvdd-supply = <®_1p8v>;
74 a2vdd-supply = <®_1p8v>;
75 v3p3-supply = <®_3p3v>;
76 v1p2-supply = <®_1p8v>;
77
78 adi,dsi-lanes = <4>;
79
80 ports {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 port@0 {
85 reg = <0>;
86 adv7535_in: endpoint {
87 remote-endpoint = <&dsi0_out>;
88 };
89 };
90
91 port@1 {
92 reg = <1>;
93 adv7535_out: endpoint {
94 remote-endpoint = <&hdmi_con_out>;
95 };
96 };
97
98 port@2 {
99 reg = <2>;
100 codec_endpoint: endpoint {
101 remote-endpoint = <&i2s2_cpu_endpoint>;
102 };
103 };
104 };
105 };
106 };
107
108 &i2c3 {
109 pinctrl-0 = <&i2c3_pins>;
110 pinctrl-names = "default";
111 clock-frequency = <400000>;
112
113 status = "okay";
114
115 wm8978: codec@1a {
116 compatible = "wlf,wm8978";
117 #sound-dai-cells = <0>;
118 reg = <0x1a>;
119 };
120
121 versa3: clock-generator@68 {
122 compatible = "renesas,5p35023";
123 reg = <0x68>;
124 #clock-cells = <1>;
125 clocks = <&x1>;
126
127 renesas,settings = [
128 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
129 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
130 80 b0 45 c4 95
131 ];
132
133 assigned-clocks = <&versa3 0>, <&versa3 1>,
134 <&versa3 2>, <&versa3 3>,
135 <&versa3 4>, <&versa3 5>;
136 assigned-clock-rates = <24000000>, <11289600>,
137 <11289600>, <12000000>,
138 <25000000>, <12288000>;
139 };
140 };
141
142 #if PMOD_MTU3
143 &mtu3 {
144 pinctrl-0 = <&mtu3_pins>;
145 pinctrl-names = "default";
146
147 status = "okay";
148 };
149
150 #if MTU3_COUNTER_Z_PHASE_SIGNAL
151 /* SDHI cd pin is muxed with counter Z phase signal */
152 &sdhi1 {
153 status = "disabled";
154 };
155 #endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
156
157 &spi1 {
158 status = "disabled";
159 };
160 #endif /* PMOD_MTU3 */
161
162 /*
163 * To enable SCIF2 (SER0) on PMOD1 (CN7)
164 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
165 * SW2 should be at position 2->3 so that SER0_TX line is activated
166 * SW3 should be at position 2->3 so that SER0_RX line is activated
167 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
168 */
169 #if PMOD1_SER0
170 &scif2 {
171 pinctrl-0 = <&scif2_pins>;
172 pinctrl-names = "default";
173
174 uart-has-rtscts;
175 status = "okay";
176 };
177 #endif
178
179 &ssi0 {
180 pinctrl-0 = <&ssi0_pins>;
181 pinctrl-names = "default";
182
183 status = "okay";
184 };
185
186 &ssi1 {
187 pinctrl-0 = <&ssi1_pins>;
188 pinctrl-names = "default";
189
190 status = "okay";
191
192 i2s2_port: port {
193 i2s2_cpu_endpoint: endpoint {
194 remote-endpoint = <&codec_endpoint>;
195 dai-format = "i2s";
196
197 bitclock-master = <&i2s2_cpu_endpoint>;
198 frame-master = <&i2s2_cpu_endpoint>;
199 };
200 };
201 };
202
203 &vccq_sdhi1 {
204 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
205 };
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