1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11 /*
12 * On-board switches' states:
13 * @SW_OFF: switch's state is OFF
14 * @SW_ON: switch's state is ON
15 */
16 #define SW_OFF 0
17 #define SW_ON 1
18
19 /*
20 * SW_CONFIG[x] switches' states:
21 * @SW_CONFIG2:
22 * SW_OFF - SD0 is connected to eMMC
23 * SW_ON - SD0 is connected to uSD0 card
24 * @SW_CONFIG3:
25 * SW_OFF - SD2 is connected to SoC
26 * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
27 */
28 #define SW_CONFIG2 SW_OFF
29 #define SW_CONFIG3 SW_ON
30
31 / {
32 compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
33
34 aliases {
35 i2c1 = &i2c1;
36 mmc0 = &sdhi0;
37 #if SW_CONFIG3 == SW_OFF
38 mmc2 = &sdhi2;
39 #else
40 ethernet0 = ð0;
41 ethernet1 = ð1;
42 #endif
43 };
44
45 chosen {
46 bootargs = "ignore_loglevel";
47 stdout-path = "serial0:115200n8";
48 };
49
50 memory@48000000 {
51 device_type = "memory";
52 /* First 128MB is reserved for secure area. */
53 reg = <0x0 0x48000000 0x0 0x38000000>;
54 };
55
56 vcc_sdhi0: regulator0 {
57 compatible = "regulator-fixed";
58 regulator-name = "SDHI0 Vcc";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 };
64
65 #if SW_CONFIG2 == SW_ON
66 vccq_sdhi0: regulator1 {
67 compatible = "regulator-gpio";
68 regulator-name = "SDHI0 VccQ";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <3300000>;
71 gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
72 gpios-states = <1>;
73 states = <3300000 1>, <1800000 0>;
74 };
75 #else
76 reg_1p8v: regulator1 {
77 compatible = "regulator-fixed";
78 regulator-name = "fixed-1.8V";
79 regulator-min-microvolt = <1800000>;
80 regulator-max-microvolt = <1800000>;
81 regulator-boot-on;
82 regulator-always-on;
83 };
84 #endif
85
86 vcc_sdhi2: regulator2 {
87 compatible = "regulator-fixed";
88 regulator-name = "SDHI2 Vcc";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91 gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
92 enable-active-high;
93 };
94 };
95
96 #if SW_CONFIG3 == SW_ON
97 ð0 {
98 pinctrl-0 = <ð0_pins>;
99 pinctrl-names = "default";
100 phy-handle = <&phy0>;
101 phy-mode = "rgmii-id";
102 status = "okay";
103
104 phy0: ethernet-phy@7 {
105 reg = <7>;
106 interrupt-parent = <&pinctrl>;
107 interrupts = <RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
108 rxc-skew-psec = <0>;
109 txc-skew-psec = <0>;
110 rxdv-skew-psec = <0>;
111 txen-skew-psec = <0>;
112 rxd0-skew-psec = <0>;
113 rxd1-skew-psec = <0>;
114 rxd2-skew-psec = <0>;
115 rxd3-skew-psec = <0>;
116 txd0-skew-psec = <0>;
117 txd1-skew-psec = <0>;
118 txd2-skew-psec = <0>;
119 txd3-skew-psec = <0>;
120 };
121 };
122
123 ð1 {
124 pinctrl-0 = <ð1_pins>;
125 pinctrl-names = "default";
126 phy-handle = <&phy1>;
127 phy-mode = "rgmii-id";
128 status = "okay";
129
130 phy1: ethernet-phy@7 {
131 reg = <7>;
132 interrupt-parent = <&pinctrl>;
133 interrupts = <RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
134 rxc-skew-psec = <0>;
135 txc-skew-psec = <0>;
136 rxdv-skew-psec = <0>;
137 txen-skew-psec = <0>;
138 rxd0-skew-psec = <0>;
139 rxd1-skew-psec = <0>;
140 rxd2-skew-psec = <0>;
141 rxd3-skew-psec = <0>;
142 txd0-skew-psec = <0>;
143 txd1-skew-psec = <0>;
144 txd2-skew-psec = <0>;
145 txd3-skew-psec = <0>;
146 };
147 };
148 #endif
149
150 &extal_clk {
151 clock-frequency = <24000000>;
152 };
153
154 &i2c1 {
155 status = "okay";
156 };
157
158 #if SW_CONFIG2 == SW_ON
159 /* SD0 slot */
160 &sdhi0 {
161 pinctrl-0 = <&sdhi0_pins>;
162 pinctrl-1 = <&sdhi0_uhs_pins>;
163 pinctrl-names = "default", "state_uhs";
164 vmmc-supply = <&vcc_sdhi0>;
165 vqmmc-supply = <&vccq_sdhi0>;
166 bus-width = <4>;
167 sd-uhs-sdr50;
168 sd-uhs-sdr104;
169 max-frequency = <125000000>;
170 status = "okay";
171 };
172 #else
173 /* eMMC */
174 &sdhi0 {
175 pinctrl-0 = <&sdhi0_emmc_pins>;
176 pinctrl-1 = <&sdhi0_emmc_pins>;
177 pinctrl-names = "default", "state_uhs";
178 vmmc-supply = <&vcc_sdhi0>;
179 vqmmc-supply = <®_1p8v>;
180 bus-width = <8>;
181 mmc-hs200-1_8v;
182 non-removable;
183 fixed-emmc-driver-type = <1>;
184 max-frequency = <125000000>;
185 status = "okay";
186 };
187 #endif
188
189 #if SW_CONFIG3 == SW_OFF
190 &sdhi2 {
191 pinctrl-0 = <&sdhi2_pins>;
192 pinctrl-names = "default";
193 vmmc-supply = <&vcc_sdhi2>;
194 bus-width = <4>;
195 max-frequency = <50000000>;
196 status = "okay";
197 };
198 #endif
199
200 &pinctrl {
201 #if SW_CONFIG3 == SW_ON
202 eth0-phy-irq-hog {
203 gpio-hog;
204 gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
205 input;
206 line-name = "eth0-phy-irq";
207 };
208 #endif
209
210 eth0_pins: eth0 {
211 txc {
212 pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
213 power-source = <1800>;
214 output-enable;
215 input-enable;
216 drive-strength-microamp = <5200>;
217 };
218
219 tx_ctl {
220 pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */
221 power-source = <1800>;
222 output-enable;
223 drive-strength-microamp = <5200>;
224 };
225
226 mux {
227 pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
228 <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
229 <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
230 <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
231 <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
232 <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
233 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
234 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
235 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
236 <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
237 <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
238 <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
239 <RZG2L_PORT_PINMUX(4, 5, 1)>; /* ET0_LINKSTA */
240 power-source = <1800>;
241 };
242 };
243
244 #if SW_CONFIG3 == SW_ON
245 eth1-phy-irq-hog {
246 gpio-hog;
247 gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
248 input;
249 line-name = "eth1-phy-irq";
250 };
251 #endif
252
253 eth1_pins: eth1 {
254 txc {
255 pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
256 power-source = <1800>;
257 output-enable;
258 input-enable;
259 drive-strength-microamp = <5200>;
260 };
261
262 tx_ctl {
263 pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* ET1_TX_CTL */
264 power-source = <1800>;
265 output-enable;
266 drive-strength-microamp = <5200>;
267 };
268
269 mux {
270 pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
271 <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
272 <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
273 <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
274 <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
275 <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
276 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
277 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
278 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
279 <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
280 <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
281 <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
282 <RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */
283 power-source = <1800>;
284 };
285 };
286
287 sdhi0_pins: sd0 {
288 data {
289 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
290 power-source = <3300>;
291 };
292
293 ctrl {
294 pins = "SD0_CLK", "SD0_CMD";
295 power-source = <3300>;
296 };
297
298 cd {
299 pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
300 };
301 };
302
303 sdhi0_uhs_pins: sd0-uhs {
304 data {
305 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
306 power-source = <1800>;
307 };
308
309 ctrl {
310 pins = "SD0_CLK", "SD0_CMD";
311 power-source = <1800>;
312 };
313
314 cd {
315 pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
316 };
317 };
318
319 sdhi0_emmc_pins: sd0-emmc {
320 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
321 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
322 "SD0_CLK", "SD0_CMD", "SD0_RST#";
323 power-source = <1800>;
324 };
325
326 sdhi2_pins: sd2 {
327 data {
328 pins = "P11_2", "P11_3", "P12_0", "P12_1";
329 input-enable;
330 };
331
332 ctrl {
333 pins = "P11_1";
334 input-enable;
335 };
336
337 mux {
338 pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
339 <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
340 <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
341 <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
342 <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
343 <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
344 <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
345 };
346 };
347 };
348
349 &wdt0 {
350 timeout-sec = <60>;
351 status = "okay";
352 };
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