1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the common parts shared by the White Hawk CPU and
4 * White Hawk Single boards
5 *
6 * Copyright (C) 2022 Renesas Electronics Corp.
7 */
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12
13 / {
14 aliases {
15 ethernet0 = &avb0;
16 i2c0 = &i2c0;
17 i2c1 = &i2c1;
18 i2c2 = &i2c2;
19 i2c3 = &i2c3;
20 i2c4 = &i2c4;
21 i2c5 = &i2c5;
22 serial0 = &hscif0;
23 };
24
25 chosen {
26 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
27 stdout-path = "serial0:921600n8";
28 };
29
30 sn65dsi86_refclk: clk-x6 {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <38400000>;
34 };
35
36 keys {
37 compatible = "gpio-keys";
38
39 pinctrl-0 = <&keys_pins>;
40 pinctrl-names = "default";
41
42 key-1 {
43 gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_1>;
45 label = "SW47";
46 wakeup-source;
47 debounce-interval = <20>;
48 };
49
50 key-2 {
51 gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
52 linux,code = <KEY_2>;
53 label = "SW48";
54 wakeup-source;
55 debounce-interval = <20>;
56 };
57
58 key-3 {
59 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
60 linux,code = <KEY_3>;
61 label = "SW49";
62 wakeup-source;
63 debounce-interval = <20>;
64 };
65 };
66
67 leds {
68 compatible = "gpio-leds";
69
70 led-1 {
71 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
72 color = <LED_COLOR_ID_GREEN>;
73 function = LED_FUNCTION_INDICATOR;
74 function-enumerator = <1>;
75 };
76
77 led-2 {
78 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
79 color = <LED_COLOR_ID_GREEN>;
80 function = LED_FUNCTION_INDICATOR;
81 function-enumerator = <2>;
82 };
83
84 led-3 {
85 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
86 color = <LED_COLOR_ID_GREEN>;
87 function = LED_FUNCTION_INDICATOR;
88 function-enumerator = <3>;
89 };
90 };
91
92 memory@48000000 {
93 device_type = "memory";
94 /* first 128MB is reserved for secure area. */
95 reg = <0x0 0x48000000 0x0 0x78000000>;
96 };
97
98 memory@480000000 {
99 device_type = "memory";
100 reg = <0x4 0x80000000 0x0 0x80000000>;
101 };
102
103 memory@600000000 {
104 device_type = "memory";
105 reg = <0x6 0x00000000 0x1 0x00000000>;
106 };
107
108 mini-dp-con {
109 compatible = "dp-connector";
110 label = "CN5";
111 type = "mini";
112
113 port {
114 mini_dp_con_in: endpoint {
115 remote-endpoint = <&sn65dsi86_out>;
116 };
117 };
118 };
119
120 pcie_clk: clk-9fgv0841-pci {
121 compatible = "fixed-clock";
122 clock-frequency = <100000000>;
123 #clock-cells = <0>;
124 };
125
126 reg_1p2v: regulator-1p2v {
127 compatible = "regulator-fixed";
128 regulator-name = "fixed-1.2V";
129 regulator-min-microvolt = <1200000>;
130 regulator-max-microvolt = <1200000>;
131 regulator-boot-on;
132 regulator-always-on;
133 };
134
135 reg_1p8v: regulator-1p8v {
136 compatible = "regulator-fixed";
137 regulator-name = "fixed-1.8V";
138 regulator-min-microvolt = <1800000>;
139 regulator-max-microvolt = <1800000>;
140 regulator-boot-on;
141 regulator-always-on;
142 };
143
144 reg_3p3v: regulator-3p3v {
145 compatible = "regulator-fixed";
146 regulator-name = "fixed-3.3V";
147 regulator-min-microvolt = <3300000>;
148 regulator-max-microvolt = <3300000>;
149 regulator-boot-on;
150 regulator-always-on;
151 };
152 };
153
154 &avb0 {
155 pinctrl-0 = <&avb0_pins>;
156 pinctrl-names = "default";
157 phy-handle = <&avb0_phy>;
158 tx-internal-delay-ps = <2000>;
159 status = "okay";
160
161 mdio {
162 #address-cells = <1>;
163 #size-cells = <0>;
164
165 avb0_phy: ethernet-phy@0 {
166 compatible = "ethernet-phy-id0022.1622",
167 "ethernet-phy-ieee802.3-c22";
168 rxc-skew-ps = <1500>;
169 reg = <0>;
170 interrupt-parent = <&gpio7>;
171 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
172 reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
173 };
174 };
175 };
176
177 &dsi0 {
178 status = "okay";
179
180 ports {
181 port@1 {
182 dsi0_out: endpoint {
183 remote-endpoint = <&sn65dsi86_in>;
184 data-lanes = <1 2 3 4>;
185 };
186 };
187 };
188 };
189
190 &du {
191 status = "okay";
192 };
193
194 &extal_clk {
195 clock-frequency = <16666666>;
196 };
197
198 &extalr_clk {
199 clock-frequency = <32768>;
200 };
201
202 &hscif0 {
203 pinctrl-0 = <&hscif0_pins>;
204 pinctrl-names = "default";
205
206 status = "okay";
207 };
208
209 &i2c0 {
210 pinctrl-0 = <&i2c0_pins>;
211 pinctrl-names = "default";
212
213 status = "okay";
214 clock-frequency = <400000>;
215
216 io_expander_a: gpio@20 {
217 compatible = "onnn,pca9654";
218 reg = <0x20>;
219 interrupt-parent = <&gpio0>;
220 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
227 eeprom@50 {
228 compatible = "rohm,br24g01", "atmel,24c01";
229 label = "cpu-board";
230 reg = <0x50>;
231 pagesize = <8>;
232 };
233 };
234
235 &i2c1 {
236 pinctrl-0 = <&i2c1_pins>;
237 pinctrl-names = "default";
238
239 status = "okay";
240 clock-frequency = <400000>;
241
242 bridge@2c {
243 compatible = "ti,sn65dsi86";
244 reg = <0x2c>;
245
246 clocks = <&sn65dsi86_refclk>;
247 clock-names = "refclk";
248
249 interrupt-parent = <&intc_ex>;
250 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
251
252 enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
253
254 vccio-supply = <®_1p8v>;
255 vpll-supply = <®_1p8v>;
256 vcca-supply = <®_1p2v>;
257 vcc-supply = <®_1p2v>;
258
259 ports {
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 port@0 {
264 reg = <0>;
265 sn65dsi86_in: endpoint {
266 remote-endpoint = <&dsi0_out>;
267 };
268 };
269
270 port@1 {
271 reg = <1>;
272 sn65dsi86_out: endpoint {
273 remote-endpoint = <&mini_dp_con_in>;
274 };
275 };
276 };
277 };
278 };
279
280 &mmc0 {
281 pinctrl-0 = <&mmc_pins>;
282 pinctrl-1 = <&mmc_pins>;
283 pinctrl-names = "default", "state_uhs";
284
285 vmmc-supply = <®_3p3v>;
286 vqmmc-supply = <®_1p8v>;
287 mmc-hs200-1_8v;
288 mmc-hs400-1_8v;
289 bus-width = <8>;
290 no-sd;
291 no-sdio;
292 non-removable;
293 full-pwr-cycle-in-suspend;
294 status = "okay";
295 };
296
297 &pcie0_clkref {
298 compatible = "gpio-gate-clock";
299 clocks = <&pcie_clk>;
300 enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
301 /delete-property/ clock-frequency;
302 };
303
304 &pciec0 {
305 reset-gpio = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
306 status = "okay";
307 };
308
309 &pfc {
310 pinctrl-0 = <&scif_clk_pins>;
311 pinctrl-names = "default";
312
313 avb0_pins: avb0 {
314 mux {
315 groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
316 "avb0_txcrefclk";
317 function = "avb0";
318 };
319
320 pins_mdio {
321 groups = "avb0_mdio";
322 drive-strength = <21>;
323 };
324
325 pins_mii {
326 groups = "avb0_rgmii";
327 drive-strength = <21>;
328 };
329
330 };
331
332 hscif0_pins: hscif0 {
333 groups = "hscif0_data";
334 function = "hscif0";
335 };
336
337 i2c0_pins: i2c0 {
338 groups = "i2c0";
339 function = "i2c0";
340 };
341
342 i2c1_pins: i2c1 {
343 groups = "i2c1";
344 function = "i2c1";
345 };
346
347 keys_pins: keys {
348 pins = "GP_5_0", "GP_5_1", "GP_5_2";
349 bias-pull-up;
350 };
351
352 mmc_pins: mmc {
353 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
354 function = "mmc";
355 power-source = <1800>;
356 };
357
358 qspi0_pins: qspi0 {
359 groups = "qspi0_ctrl", "qspi0_data4";
360 function = "qspi0";
361 };
362
363 scif_clk_pins: scif_clk {
364 groups = "scif_clk";
365 function = "scif_clk";
366 };
367 };
368
369 &rpc {
370 pinctrl-0 = <&qspi0_pins>;
371 pinctrl-names = "default";
372
373 status = "okay";
374
375 flash@0 {
376 compatible = "spansion,s25fs512s", "jedec,spi-nor";
377 reg = <0>;
378 spi-max-frequency = <40000000>;
379 spi-rx-bus-width = <4>;
380
381 partitions {
382 compatible = "fixed-partitions";
383 #address-cells = <1>;
384 #size-cells = <1>;
385
386 boot@0 {
387 reg = <0x0 0x1200000>;
388 read-only;
389 };
390 user@1200000 {
391 reg = <0x1200000 0x2e00000>;
392 };
393 };
394 };
395 };
396
397 &rwdt {
398 timeout-sec = <60>;
399 status = "okay";
400 };
401
402 &scif_clk {
403 clock-frequency = <24000000>;
404 };
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