1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Google Gru (and derivatives) board device tree source
4 *
5 * Copyright 2016-2017 Google, Inc
6 */
7
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
10
11 / {
12 aliases {
13 mmc0 = &sdmmc;
14 mmc1 = &sdhci;
15 };
16
17 chosen {
18 stdout-path = "serial2:115200n8";
19 };
20
21 /*
22 * Power Tree
23 *
24 * In general an attempt is made to include all rails called out by
25 * the schematic as long as those rails interact in some way with
26 * the AP. AKA:
27 * - Rails that only connect to the EC (or devices that the EC talks to)
28 * are not included.
29 * - Rails _are_ included if the rails go to the AP even if the AP
30 * doesn't currently care about them / they are always on. The idea
31 * here is that it makes it easier to map to the schematic or extend
32 * later.
33 *
34 * If two rails are substantially the same from the AP's point of
35 * view, though, we won't create a full fixed regulator. We'll just
36 * put the child rail as an alias of the parent rail. Sometimes rails
37 * look the same to the AP because one of these is true:
38 * - The EC controls the enable and the EC always enables a rail as
39 * long as the AP is running.
40 * - The rails are actually connected to each other by a jumper and
41 * the distinction is just there to add clarity/flexibility to the
42 * schematic.
43 */
44
45 ppvar_sys: ppvar-sys {
46 compatible = "regulator-fixed";
47 regulator-name = "ppvar_sys";
48 regulator-always-on;
49 regulator-boot-on;
50 };
51
52 pp1200_lpddr: pp1200-lpddr {
53 compatible = "regulator-fixed";
54 regulator-name = "pp1200_lpddr";
55
56 /* EC turns on w/ lpddr_pwr_en; always on for AP */
57 regulator-always-on;
58 regulator-boot-on;
59 regulator-min-microvolt = <1200000>;
60 regulator-max-microvolt = <1200000>;
61
62 vin-supply = <&ppvar_sys>;
63 };
64
65 pp1800: pp1800 {
66 compatible = "regulator-fixed";
67 regulator-name = "pp1800";
68
69 /* Always on when ppvar_sys shows power good */
70 regulator-always-on;
71 regulator-boot-on;
72 regulator-min-microvolt = <1800000>;
73 regulator-max-microvolt = <1800000>;
74
75 vin-supply = <&ppvar_sys>;
76 };
77
78 pp3300: pp3300 {
79 compatible = "regulator-fixed";
80 regulator-name = "pp3300";
81
82 /* Always on; plain and simple */
83 regulator-always-on;
84 regulator-boot-on;
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87
88 vin-supply = <&ppvar_sys>;
89 };
90
91 pp5000: pp5000 {
92 compatible = "regulator-fixed";
93 regulator-name = "pp5000";
94
95 /* EC turns on w/ pp5000_en; always on for AP */
96 regulator-always-on;
97 regulator-boot-on;
98 regulator-min-microvolt = <5000000>;
99 regulator-max-microvolt = <5000000>;
100
101 vin-supply = <&ppvar_sys>;
102 };
103
104 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
105 compatible = "pwm-regulator";
106 regulator-name = "ppvar_bigcpu_pwm";
107
108 pwms = <&pwm1 0 3337 0>;
109 pwm-supply = <&ppvar_sys>;
110 pwm-dutycycle-range = <100 0>;
111 pwm-dutycycle-unit = <100>;
112
113 /* EC turns on w/ ap_core_en; always on for AP */
114 regulator-always-on;
115 regulator-boot-on;
116 regulator-min-microvolt = <800107>;
117 regulator-max-microvolt = <1302232>;
118 };
119
120 ppvar_bigcpu: ppvar-bigcpu {
121 compatible = "vctrl-regulator";
122 regulator-name = "ppvar_bigcpu";
123
124 regulator-min-microvolt = <800107>;
125 regulator-max-microvolt = <1302232>;
126
127 ctrl-supply = <&ppvar_bigcpu_pwm>;
128 ctrl-voltage-range = <800107 1302232>;
129
130 regulator-settling-time-up-us = <322>;
131 };
132
133 ppvar_litcpu_pwm: ppvar-litcpu-pwm {
134 compatible = "pwm-regulator";
135 regulator-name = "ppvar_litcpu_pwm";
136
137 pwms = <&pwm2 0 3337 0>;
138 pwm-supply = <&ppvar_sys>;
139 pwm-dutycycle-range = <100 0>;
140 pwm-dutycycle-unit = <100>;
141
142 /* EC turns on w/ ap_core_en; always on for AP */
143 regulator-always-on;
144 regulator-boot-on;
145 regulator-min-microvolt = <797743>;
146 regulator-max-microvolt = <1307837>;
147 };
148
149 ppvar_litcpu: ppvar-litcpu {
150 compatible = "vctrl-regulator";
151 regulator-name = "ppvar_litcpu";
152
153 regulator-min-microvolt = <797743>;
154 regulator-max-microvolt = <1307837>;
155
156 ctrl-supply = <&ppvar_litcpu_pwm>;
157 ctrl-voltage-range = <797743 1307837>;
158
159 regulator-settling-time-up-us = <384>;
160 };
161
162 ppvar_gpu_pwm: ppvar-gpu-pwm {
163 compatible = "pwm-regulator";
164 regulator-name = "ppvar_gpu_pwm";
165
166 pwms = <&pwm0 0 3337 0>;
167 pwm-supply = <&ppvar_sys>;
168 pwm-dutycycle-range = <100 0>;
169 pwm-dutycycle-unit = <100>;
170
171 /* EC turns on w/ ap_core_en; always on for AP */
172 regulator-always-on;
173 regulator-boot-on;
174 regulator-min-microvolt = <786384>;
175 regulator-max-microvolt = <1217747>;
176 };
177
178 ppvar_gpu: ppvar-gpu {
179 compatible = "vctrl-regulator";
180 regulator-name = "ppvar_gpu";
181
182 regulator-min-microvolt = <786384>;
183 regulator-max-microvolt = <1217747>;
184
185 ctrl-supply = <&ppvar_gpu_pwm>;
186 ctrl-voltage-range = <786384 1217747>;
187
188 regulator-settling-time-up-us = <390>;
189 };
190
191 /* EC turns on w/ pp900_ddrpll_en */
192 pp900_ddrpll: pp900-ap {
193 };
194
195 /* EC turns on w/ pp900_pll_en */
196 pp900_pll: pp900-ap {
197 };
198
199 /* EC turns on w/ pp900_pmu_en */
200 pp900_pmu: pp900-ap {
201 };
202
203 /* EC turns on w/ pp1800_s0_en_l */
204 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
205 };
206
207 /* EC turns on w/ pp1800_avdd_en_l */
208 pp1800_avdd: pp1800 {
209 };
210
211 /* EC turns on w/ pp1800_lid_en_l */
212 pp1800_lid: pp1800_mic: pp1800 {
213 };
214
215 /* EC turns on w/ lpddr_pwr_en */
216 pp1800_lpddr: pp1800 {
217 };
218
219 /* EC turns on w/ pp1800_pmu_en_l */
220 pp1800_pmu: pp1800 {
221 };
222
223 /* EC turns on w/ pp1800_usb_en_l */
224 pp1800_usb: pp1800 {
225 };
226
227 pp3000_sd_slot: pp3000-sd-slot {
228 compatible = "regulator-fixed";
229 regulator-name = "pp3000_sd_slot";
230 pinctrl-names = "default";
231 pinctrl-0 = <&sd_slot_pwr_en>;
232
233 enable-active-high;
234 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
235
236 vin-supply = <&pp3000>;
237 };
238
239 /*
240 * Technically, this is a small abuse of 'regulator-gpio'; this
241 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
242 * always on though, so it is sufficient to simply control the mux
243 * here.
244 */
245 ppvar_sd_card_io: ppvar-sd-card-io {
246 compatible = "regulator-gpio";
247 regulator-name = "ppvar_sd_card_io";
248 pinctrl-names = "default";
249 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
250
251 enable-active-high;
252 enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
253 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
254 states = <1800000 0x1>,
255 <3000000 0x0>;
256
257 regulator-min-microvolt = <1800000>;
258 regulator-max-microvolt = <3000000>;
259 };
260
261 /* EC turns on w/ pp3300_trackpad_en_l */
262 pp3300_trackpad: pp3300-trackpad {
263 };
264
265 /* EC turns on w/ usb_a_en */
266 pp5000_usb_a_vbus: pp5000 {
267 };
268
269 ap_rtc_clk: ap-rtc-clk {
270 compatible = "fixed-clock";
271 clock-frequency = <32768>;
272 clock-output-names = "xin32k";
273 #clock-cells = <0>;
274 };
275
276 max98357a: max98357a {
277 compatible = "maxim,max98357a";
278 pinctrl-names = "default";
279 pinctrl-0 = <&sdmode_en>;
280 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
281 sdmode-delay = <2>;
282 #sound-dai-cells = <0>;
283 status = "okay";
284 };
285
286 sound: sound {
287 compatible = "rockchip,rk3399-gru-sound";
288 rockchip,cpu = <&i2s0 &spdif>;
289 };
290 };
291
292 &cdn_dp {
293 status = "okay";
294 };
295
296 /*
297 * Set some suspend operating points to avoid OVP in suspend
298 *
299 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
300 * from wherever they're at back to the "default" operating point (whatever
301 * voltage we get when we set the PWM pins to "input").
302 *
303 * This quick transition under light load has the possibility to trigger the
304 * regulator "over voltage protection" (OVP).
305 *
306 * To make extra certain that we don't hit this OVP at suspend time, we'll
307 * transition to a voltage that's much closer to the default (~1.0 V) so that
308 * there will not be a big jump. Technically we only need to get within 200 mV
309 * of the default voltage, but the speed here should be fast enough and we need
310 * suspend/resume to be rock solid.
311 */
312
313 &cluster0_opp {
314 opp05 {
315 opp-suspend;
316 };
317 };
318
319 &cluster1_opp {
320 opp06 {
321 opp-suspend;
322 };
323 };
324
325 &cpu_l0 {
326 cpu-supply = <&ppvar_litcpu>;
327 };
328
329 &cpu_l1 {
330 cpu-supply = <&ppvar_litcpu>;
331 };
332
333 &cpu_l2 {
334 cpu-supply = <&ppvar_litcpu>;
335 };
336
337 &cpu_l3 {
338 cpu-supply = <&ppvar_litcpu>;
339 };
340
341 &cpu_b0 {
342 cpu-supply = <&ppvar_bigcpu>;
343 };
344
345 &cpu_b1 {
346 cpu-supply = <&ppvar_bigcpu>;
347 };
348
349
350 &cru {
351 assigned-clocks =
352 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
353 <&cru PLL_NPLL>,
354 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
355 <&cru PCLK_PERIHP>,
356 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
357 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
358 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
359 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
360 <&cru ACLK_GIC_PRE>,
361 <&cru PCLK_DDR>;
362 assigned-clock-rates =
363 <600000000>, <800000000>,
364 <1000000000>,
365 <150000000>, <75000000>,
366 <37500000>,
367 <100000000>, <100000000>,
368 <50000000>, <800000000>,
369 <100000000>, <50000000>,
370 <400000000>, <400000000>,
371 <200000000>,
372 <200000000>;
373 };
374
375 &dfi {
376 status = "okay";
377 };
378
379 &dmc {
380 status = "okay";
381
382 rockchip,pd-idle-ns = <160>;
383 rockchip,sr-idle-ns = <10240>;
384 rockchip,sr-mc-gate-idle-ns = <40960>;
385 rockchip,srpd-lite-idle-ns = <61440>;
386 rockchip,standby-idle-ns = <81920>;
387
388 rockchip,ddr3_odt_dis_freq = <666000000>;
389 rockchip,lpddr3_odt_dis_freq = <666000000>;
390 rockchip,lpddr4_odt_dis_freq = <666000000>;
391
392 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
393 rockchip,srpd-lite-idle-dis-freq-hz = <0>;
394 rockchip,standby-idle-dis-freq-hz = <928000000>;
395 };
396
397 &dmc_opp_table {
398 opp03 {
399 opp-suspend;
400 };
401 };
402
403 &emmc_phy {
404 status = "okay";
405 };
406
407 &gpu {
408 mali-supply = <&ppvar_gpu>;
409 status = "okay";
410 };
411
412 ap_i2c_ts: &i2c3 {
413 status = "okay";
414
415 clock-frequency = <400000>;
416
417 /* These are relatively safe rise/fall times */
418 i2c-scl-falling-time-ns = <50>;
419 i2c-scl-rising-time-ns = <300>;
420 };
421
422 ap_i2c_audio: &i2c8 {
423 status = "okay";
424
425 clock-frequency = <400000>;
426
427 /* These are relatively safe rise/fall times */
428 i2c-scl-falling-time-ns = <50>;
429 i2c-scl-rising-time-ns = <300>;
430
431 codec: da7219@1a {
432 compatible = "dlg,da7219";
433 reg = <0x1a>;
434 interrupt-parent = <&gpio1>;
435 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
436 clocks = <&cru SCLK_I2S_8CH_OUT>;
437 clock-names = "mclk";
438 dlg,micbias-lvl = <2600>;
439 dlg,mic-amp-in-sel = "diff";
440 pinctrl-names = "default";
441 pinctrl-0 = <&headset_int_l>;
442 VDD-supply = <&pp1800>;
443 VDDMIC-supply = <&pp3300>;
444 VDDIO-supply = <&pp1800>;
445
446 da7219_aad {
447 dlg,adc-1bit-rpt = <1>;
448 dlg,btn-avg = <4>;
449 dlg,btn-cfg = <50>;
450 dlg,mic-det-thr = <500>;
451 dlg,jack-ins-deb = <20>;
452 dlg,jack-det-rate = "32_64";
453 dlg,jack-rem-deb = <1>;
454
455 dlg,a-d-btn-thr = <0xa>;
456 dlg,d-b-btn-thr = <0x16>;
457 dlg,b-c-btn-thr = <0x21>;
458 dlg,c-mic-btn-thr = <0x3E>;
459 };
460 };
461 };
462
463 &i2s0 {
464 status = "okay";
465 };
466
467 &io_domains {
468 status = "okay";
469
470 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
471 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
472 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
473 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
474 };
475
476 &pcie0 {
477 status = "okay";
478
479 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
482 vpcie3v3-supply = <&pp3300_wifi_bt>;
483 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
484 vpcie0v9-supply = <&pp900_pcie>;
485
486 pci_rootport: pcie@0,0 {
487 reg = <0x0000 0 0 0 0>;
488 #address-cells = <3>;
489 #size-cells = <2>;
490 ranges;
491 device_type = "pci";
492 };
493 };
494
495 &pcie_phy {
496 status = "okay";
497 };
498
499 &pmu_io_domains {
500 status = "okay";
501
502 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
503 };
504
505 &pwm0 {
506 status = "okay";
507 };
508
509 &pwm1 {
510 status = "okay";
511 };
512
513 &pwm2 {
514 status = "okay";
515 };
516
517 &pwm3 {
518 status = "okay";
519 };
520
521 &sdhci {
522 /*
523 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
524 * same (or nearly the same) performance for all eMMC that are intended
525 * to be used.
526 */
527 assigned-clock-rates = <150000000>;
528
529 bus-width = <8>;
530 mmc-hs400-1_8v;
531 mmc-hs400-enhanced-strobe;
532 non-removable;
533 status = "okay";
534 };
535
536 &sdmmc {
537 status = "okay";
538
539 /*
540 * Note: configure "sdmmc_cd" as card detect even though it's actually
541 * hooked to ground. Because we specified "cd-gpios" below dw_mmc
542 * should be ignoring card detect anyway. Specifying the pin as
543 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
544 * turned on that the system will still make sure the port is
545 * configured as SDMMC and not JTAG.
546 */
547 pinctrl-names = "default";
548 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin
549 &sdmmc_bus4>;
550
551 bus-width = <4>;
552 cap-mmc-highspeed;
553 cap-sd-highspeed;
554 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
555 disable-wp;
556 sd-uhs-sdr12;
557 sd-uhs-sdr25;
558 sd-uhs-sdr50;
559 sd-uhs-sdr104;
560 vmmc-supply = <&pp3000_sd_slot>;
561 vqmmc-supply = <&ppvar_sd_card_io>;
562 };
563
564 &spdif {
565 status = "okay";
566
567 /*
568 * SPDIF is routed internally to DP; we either don't use these pins, or
569 * mux them to something else.
570 */
571 /delete-property/ pinctrl-0;
572 /delete-property/ pinctrl-names;
573 };
574
575 &spi1 {
576 status = "okay";
577
578 pinctrl-names = "default", "sleep";
579 pinctrl-1 = <&spi1_sleep>;
580
581 flash@0 {
582 compatible = "jedec,spi-nor";
583 reg = <0>;
584
585 /* May run faster once verified. */
586 spi-max-frequency = <10000000>;
587 };
588 };
589
590 &spi2 {
591 status = "okay";
592 };
593
594 &spi5 {
595 status = "okay";
596
597 cros_ec: ec@0 {
598 compatible = "google,cros-ec-spi";
599 reg = <0>;
600 interrupt-parent = <&gpio0>;
601 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&ec_ap_int_l>;
604 spi-max-frequency = <3000000>;
605
606 i2c_tunnel: i2c-tunnel {
607 compatible = "google,cros-ec-i2c-tunnel";
608 google,remote-bus = <4>;
609 #address-cells = <1>;
610 #size-cells = <0>;
611 };
612
613 usbc_extcon0: extcon0 {
614 compatible = "google,extcon-usbc-cros-ec";
615 google,usb-port-id = <0>;
616 };
617 };
618 };
619
620 &tsadc {
621 status = "okay";
622
623 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
624 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
625 };
626
627 &tcphy0 {
628 status = "okay";
629 extcon = <&usbc_extcon0>;
630 };
631
632 &u2phy0 {
633 status = "okay";
634 };
635
636 &u2phy0_host {
637 status = "okay";
638 };
639
640 &u2phy1_host {
641 status = "okay";
642 };
643
644 &u2phy0_otg {
645 status = "okay";
646 };
647
648 &u2phy1_otg {
649 status = "okay";
650 };
651
652 &uart2 {
653 status = "okay";
654 };
655
656 &usb_host0_ohci {
657 status = "okay";
658 };
659
660 &usbdrd3_0 {
661 status = "okay";
662 extcon = <&usbc_extcon0>;
663 };
664
665 &usbdrd_dwc3_0 {
666 status = "okay";
667 dr_mode = "host";
668 };
669
670 &vopb {
671 status = "okay";
672 };
673
674 &vopb_mmu {
675 status = "okay";
676 };
677
678 &vopl {
679 status = "okay";
680 };
681
682 &vopl_mmu {
683 status = "okay";
684 };
685
686 #include <arm/cros-ec-keyboard.dtsi>
687 #include <arm/cros-ec-sbs.dtsi>
688
689 &pinctrl {
690 /*
691 * pinctrl settings for pins that have no real owners.
692 *
693 * At the moment settings are identical for S0 and S3, but if we later
694 * need to configure things differently for S3 we'll adjust here.
695 */
696 pinctrl-names = "default";
697 pinctrl-0 = <
698 &ap_pwroff /* AP will auto-assert this when in S3 */
699 &clk_32k /* This pin is always 32k on gru boards */
700 >;
701
702 pcfg_output_low: pcfg-output-low {
703 output-low;
704 };
705
706 pcfg_output_high: pcfg-output-high {
707 output-high;
708 };
709
710 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
711 bias-disable;
712 drive-strength = <8>;
713 };
714
715 backlight-enable {
716 bl_en: bl-en {
717 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
718 };
719 };
720
721 cros-ec {
722 ec_ap_int_l: ec-ap-int-l {
723 rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
724 };
725 };
726
727 discrete-regulators {
728 sd_io_pwr_en: sd-io-pwr-en {
729 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
730 &pcfg_pull_none>;
731 };
732
733 sd_pwr_1800_sel: sd-pwr-1800-sel {
734 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
735 &pcfg_pull_none>;
736 };
737
738 sd_slot_pwr_en: sd-slot-pwr-en {
739 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
740 &pcfg_pull_none>;
741 };
742 };
743
744 codec {
745 /* Has external pullup */
746 headset_int_l: headset-int-l {
747 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
748 };
749
750 mic_int: mic-int {
751 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
752 };
753 };
754
755 max98357a {
756 sdmode_en: sdmode-en {
757 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
758 };
759 };
760
761 pcie {
762 pcie_clkreqn_cpm: pci-clkreqn-cpm {
763 /*
764 * Since our pcie doesn't support ClockPM(CPM), we want
765 * to hack this as gpio, so the EP could be able to
766 * de-assert it along and make ClockPM(CPM) work.
767 */
768 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
769 };
770 };
771
772 sdmmc {
773 /*
774 * We run sdmmc at max speed; bump up drive strength.
775 * We also have external pulls, so disable the internal ones.
776 */
777 sdmmc_bus4: sdmmc-bus4 {
778 rockchip,pins =
779 <4 RK_PB0 1 &pcfg_pull_none_8ma>,
780 <4 RK_PB1 1 &pcfg_pull_none_8ma>,
781 <4 RK_PB2 1 &pcfg_pull_none_8ma>,
782 <4 RK_PB3 1 &pcfg_pull_none_8ma>;
783 };
784
785 sdmmc_clk: sdmmc-clk {
786 rockchip,pins =
787 <4 RK_PB4 1 &pcfg_pull_none_8ma>;
788 };
789
790 sdmmc_cmd: sdmmc-cmd {
791 rockchip,pins =
792 <4 RK_PB5 1 &pcfg_pull_none_8ma>;
793 };
794
795 /*
796 * In our case the official card detect is hooked to ground
797 * to avoid getting access to JTAG just by sticking something
798 * in the SD card slot (see the force_jtag bit in the TRM).
799 *
800 * We still configure it as card detect because it doesn't
801 * hurt and dw_mmc will ignore it. We make sure to disable
802 * the pull though so we don't burn needless power.
803 */
804 sdmmc_cd: sdmmc-cd {
805 rockchip,pins =
806 <0 RK_PA7 1 &pcfg_pull_none>;
807 };
808
809 /* This is where we actually hook up CD; has external pull */
810 sdmmc_cd_pin: sdmmc-cd-pin {
811 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
812 };
813 };
814
815 spi1 {
816 spi1_sleep: spi1-sleep {
817 /*
818 * Pull down SPI1 CLK/CS/RX/TX during suspend, to
819 * prevent leakage.
820 */
821 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
822 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
823 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
824 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
825 };
826 };
827
828 touchscreen {
829 touch_int_l: touch-int-l {
830 rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
831 };
832
833 touch_reset_l: touch-reset-l {
834 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
835 };
836 };
837
838 trackpad {
839 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
840 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
841 };
842
843 trackpad_int_l: trackpad-int-l {
844 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
845 };
846 };
847
848 wifi: wifi {
849 wlan_module_reset_l: wlan-module-reset-l {
850 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
851 };
852
853 bt_host_wake_l: bt-host-wake-l {
854 /* Kevin has an external pull up, but Gru does not */
855 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
856 };
857 };
858
859 write-protect {
860 ap_fw_wp: ap-fw-wp {
861 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
862 };
863 };
864 };
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