1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
4 */
5
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/usb/pd.h>
12 #include "rk3588.dtsi"
13
14 / {
15 model = "Theobroma Systems RK3588-SBC Jaguar";
16 compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
17
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
22 keyup-threshold-microvolt = <1800000>;
23 poll-interval = <100>;
24
25 /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */
26 button-bios-disable {
27 label = "BIOS_DISABLE";
28 linux,code = <KEY_VENDOR>;
29 press-threshold-microvolt = <0>;
30 };
31 };
32
33 aliases {
34 ethernet0 = &gmac0;
35 mmc0 = &sdhci;
36 mmc1 = &sdmmc;
37 rtc0 = &rtc_twi;
38 };
39
40 chosen {
41 stdout-path = "serial2:115200n8";
42 };
43
44 /* DCIN is 12-24V but standard is 12V */
45 dc_12v: dc-12v-regulator {
46 compatible = "regulator-fixed";
47 regulator-name = "dc_12v";
48 regulator-always-on;
49 regulator-boot-on;
50 regulator-min-microvolt = <12000000>;
51 regulator-max-microvolt = <12000000>;
52 };
53
54 emmc_pwrseq: emmc-pwrseq {
55 compatible = "mmc-pwrseq-emmc";
56 pinctrl-0 = <&emmc_reset>;
57 pinctrl-names = "default";
58 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
59 };
60
61 leds {
62 compatible = "gpio-leds";
63 pinctrl-names = "default";
64 pinctrl-0 = <&led1_pin>;
65
66 /* LED1 on PCB */
67 led-1 {
68 gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
69 function = LED_FUNCTION_HEARTBEAT;
70 linux,default-trigger = "heartbeat";
71 color = <LED_COLOR_ID_AMBER>;
72 };
73 };
74
75 /*
76 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
77 * clock generator.
78 * The clock output is gated via the OE pin on the clock generator.
79 * This is modeled as a fixed-clock plus a gpio-gate-clock.
80 */
81 pcie_refclk_gen: pcie-refclk-gen-clock {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <100000000>;
85 };
86
87 pcie_refclk: pcie-refclk-clock {
88 compatible = "gpio-gate-clock";
89 clocks = <&pcie_refclk_gen>;
90 #clock-cells = <0>;
91 enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
92 pinctrl-names = "default";
93 pinctrl-0 = <&pcie30x4_clkreqn_m0>;
94 };
95
96 pps {
97 compatible = "pps-gpio";
98 gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
99 };
100
101 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
102 compatible = "regulator-fixed";
103 regulator-name = "vcc_1v1_nldo_s3";
104 regulator-always-on;
105 regulator-boot-on;
106 regulator-min-microvolt = <1100000>;
107 regulator-max-microvolt = <1100000>;
108 vin-supply = <&vcc5v0_sys>;
109 };
110
111 vcc_1v2_s3: vcc-1v2-s3-regulator {
112 compatible = "regulator-fixed";
113 regulator-name = "vcc_1v2_s3";
114 regulator-always-on;
115 regulator-boot-on;
116 regulator-min-microvolt = <1200000>;
117 regulator-max-microvolt = <1200000>;
118 vin-supply = <&vcc5v0_sys>;
119 };
120
121 /* Exposed on P14 and P15 */
122 vcc_2v8_s3: vcc-2v8-s3-regulator {
123 compatible = "regulator-fixed";
124 regulator-name = "vcc_2v8_s3";
125 regulator-always-on;
126 regulator-boot-on;
127 regulator-min-microvolt = <2800000>;
128 regulator-max-microvolt = <2800000>;
129 vin-supply = <&vcc_3v3_s3>;
130 };
131
132 vcc_5v0_usb_a: vcc-5v0-usb-a-regulator {
133 compatible = "regulator-fixed";
134 regulator-name = "usb_a_vcc";
135 regulator-min-microvolt = <5000000>;
136 regulator-max-microvolt = <5000000>;
137 vin-supply = <&vcc5v0_sys>;
138 gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 };
141
142 vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator {
143 compatible = "regulator-fixed";
144 regulator-name = "5v_usbc1";
145 regulator-min-microvolt = <5000000>;
146 regulator-max-microvolt = <5000000>;
147 vin-supply = <&vcc5v0_usb>;
148 gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
149 enable-active-high;
150 };
151
152 vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator {
153 compatible = "regulator-fixed";
154 regulator-name = "5v_usbc2";
155 regulator-min-microvolt = <5000000>;
156 regulator-max-microvolt = <5000000>;
157 vin-supply = <&vcc5v0_usb>;
158 gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
159 enable-active-high;
160 };
161
162 vcc3v3_mdot2: vcc3v3-mdot2-regulator {
163 compatible = "regulator-fixed";
164 regulator-name = "vcc3v3_mdot2";
165 regulator-always-on;
166 regulator-boot-on;
167 regulator-min-microvolt = <3300000>;
168 regulator-max-microvolt = <3300000>;
169 vin-supply = <&dc_12v>;
170 };
171
172 vcc5v0_sys: vcc5v0-sys-regulator {
173 compatible = "regulator-fixed";
174 regulator-name = "vcc5v0_sys";
175 regulator-always-on;
176 regulator-boot-on;
177 regulator-min-microvolt = <5000000>;
178 regulator-max-microvolt = <5000000>;
179 vin-supply = <&dc_12v>;
180 };
181
182 vcc5v0_usb: vcc5v0-usb-regulator {
183 compatible = "regulator-fixed";
184 regulator-name = "vcc5v0_usb";
185 regulator-always-on;
186 regulator-boot-on;
187 regulator-min-microvolt = <5000000>;
188 regulator-max-microvolt = <5000000>;
189 vin-supply = <&vcc5v0_sys>;
190 };
191 };
192
193 &combphy1_ps {
194 status = "okay";
195 };
196
197 &cpu_b0 {
198 cpu-supply = <&vdd_cpu_big0_s0>;
199 };
200
201 &cpu_b1 {
202 cpu-supply = <&vdd_cpu_big0_s0>;
203 };
204
205 &cpu_b2 {
206 cpu-supply = <&vdd_cpu_big1_s0>;
207 };
208
209 &cpu_b3 {
210 cpu-supply = <&vdd_cpu_big1_s0>;
211 };
212
213 &cpu_l0 {
214 cpu-supply = <&vdd_cpu_lit_s0>;
215 };
216
217 &cpu_l1 {
218 cpu-supply = <&vdd_cpu_lit_s0>;
219 };
220
221 &cpu_l2 {
222 cpu-supply = <&vdd_cpu_lit_s0>;
223 };
224
225 &cpu_l3 {
226 cpu-supply = <&vdd_cpu_lit_s0>;
227 };
228
229 &gmac0 {
230 clock_in_out = "output";
231 phy-handle = <&rgmii_phy>;
232 phy-mode = "rgmii";
233 phy-supply = <&vcc_1v2_s3>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&gmac0_miim
236 &gmac0_rx_bus2
237 &gmac0_tx_bus2
238 &gmac0_rgmii_clk
239 &gmac0_rgmii_bus
240 ð0_pins
241 ð_reset>;
242 tx_delay = <0x10>;
243 rx_delay = <0x10>;
244 snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
245 snps,reset-active-low;
246 snps,reset-delays-us = <0 10000 100000>;
247
248 status = "okay";
249 };
250
251 &gpio1 {
252 mdot2e-w-disable1-n-hog {
253 gpios = <RK_PB1 GPIO_ACTIVE_LOW>;
254 output-low;
255 line-name = "m.2 E-key W_DISABLE1#";
256 gpio-hog;
257 };
258 };
259
260 &gpio4 {
261 mdot2e-w-disable2-n-hog {
262 gpios = <RK_PC1 GPIO_ACTIVE_LOW>;
263 output-low;
264 line-name = "m.2 E-key W_DISABLE2#";
265 gpio-hog;
266 };
267 };
268
269 &gpu {
270 mali-supply = <&vdd_gpu_s0>;
271 status = "okay";
272 };
273
274 &i2c0 {
275 pinctrl-0 = <&i2c0m2_xfer>;
276 status = "okay";
277
278 fan@18 {
279 compatible = "ti,amc6821";
280 reg = <0x18>;
281 };
282
283 vdd_npu_s0: regulator@42 {
284 compatible = "rockchip,rk8602";
285 reg = <0x42>;
286 fcs,suspend-voltage-selector = <1>;
287 regulator-name = "vdd_npu_s0";
288 regulator-always-on;
289 regulator-boot-on;
290 regulator-min-microvolt = <550000>;
291 regulator-max-microvolt = <950000>;
292 regulator-ramp-delay = <2300>;
293 vin-supply = <&vcc5v0_sys>;
294
295 regulator-state-mem {
296 regulator-off-in-suspend;
297 };
298 };
299
300 vdd_cpu_big1_s0: regulator@43 {
301 compatible = "rockchip,rk8603", "rockchip,rk8602";
302 reg = <0x43>;
303 fcs,suspend-voltage-selector = <1>;
304 regulator-name = "vdd_cpu_big1_s0";
305 regulator-always-on;
306 regulator-boot-on;
307 regulator-min-microvolt = <550000>;
308 regulator-max-microvolt = <1050000>;
309 regulator-ramp-delay = <2300>;
310 vin-supply = <&vcc5v0_sys>;
311
312 regulator-state-mem {
313 regulator-off-in-suspend;
314 };
315 };
316
317 rtc_twi: rtc@6f {
318 compatible = "isil,isl1208";
319 reg = <0x6f>;
320 };
321 };
322
323 &i2c1 {
324 pinctrl-0 = <&i2c1m4_xfer>;
325 };
326
327 &i2c6 {
328 pinctrl-0 = <&i2c6m4_xfer>;
329 };
330
331 &i2c7 {
332 status = "okay";
333
334 /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */
335
336 /* Also on 0x55 */
337 eeprom@54 {
338 compatible = "st,24c04", "atmel,24c04";
339 reg = <0x54>;
340 pagesize = <16>;
341 vcc-supply = <&vcc_3v3_s3>;
342 };
343 };
344
345 &i2c8 {
346 pinctrl-0 = <&i2c8m2_xfer>;
347 status = "okay";
348
349 vdd_cpu_big0_s0: regulator@42 {
350 compatible = "rockchip,rk8602";
351 reg = <0x42>;
352 fcs,suspend-voltage-selector = <1>;
353 regulator-name = "vdd_cpu_big0_s0";
354 regulator-always-on;
355 regulator-boot-on;
356 regulator-min-microvolt = <550000>;
357 regulator-max-microvolt = <1050000>;
358 regulator-ramp-delay = <2300>;
359 vin-supply = <&vcc5v0_sys>;
360
361 regulator-state-mem {
362 regulator-off-in-suspend;
363 };
364 };
365 };
366
367 &mdio0 {
368 rgmii_phy: ethernet-phy@6 {
369 /* KSZ9031 or KSZ9131 */
370 compatible = "ethernet-phy-ieee802.3-c22";
371 reg = <0x6>;
372 clocks = <&cru REFCLKO25M_ETH0_OUT>;
373 };
374 };
375
376 &pcie2x1l0 {
377 reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */
378 vpcie3v3-supply = <&vcc3v3_mdot2>;
379 status = "okay";
380 };
381
382 &pcie30phy {
383 status = "okay";
384 };
385
386 &pcie3x4 {
387 /*
388 * The board has a gpio-controlled "pcie_refclk" generator,
389 * so add it to the list of clocks.
390 */
391 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
392 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
393 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
394 <&pcie_refclk>;
395 clock-names = "aclk_mst", "aclk_slv",
396 "aclk_dbi", "pclk",
397 "aux", "pipe",
398 "ref";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>;
401 reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
402 vpcie3v3-supply = <&vcc3v3_mdot2>;
403 status = "okay";
404 };
405
406 &pinctrl {
407 emmc {
408 emmc_reset: emmc-reset {
409 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
410 };
411 };
412
413 ethernet {
414 eth_reset: eth-reset {
415 rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
416 };
417 };
418
419 leds {
420 led1_pin: led1-pin {
421 rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
422 };
423 };
424
425 pcie30x4 {
426 pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
427 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
428 };
429
430 pcie30x4_perstn_m0: pcie30x4-perstn-m0 {
431 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
432 };
433
434 pcie30x4_waken_m0: pcie30x4-waken-m0 {
435 rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>;
436 };
437 };
438 };
439
440 &saradc {
441 vref-supply = <&vcc_1v8_s0>;
442 status = "okay";
443 };
444
445 &sdhci {
446 bus-width = <8>;
447 cap-mmc-highspeed;
448 mmc-ddr-1_8v;
449 mmc-hs200-1_8v;
450 mmc-hs400-1_8v;
451 mmc-hs400-enhanced-strobe;
452 mmc-pwrseq = <&emmc_pwrseq>;
453 no-sdio;
454 no-sd;
455 non-removable;
456 pinctrl-names = "default";
457 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>;
458 supports-cqe;
459 vmmc-supply = <&vcc_3v3_s3>;
460 vqmmc-supply = <&vcc_1v8_s3>;
461 status = "okay";
462 };
463
464 &sdmmc {
465 broken-cd;
466 bus-width = <4>;
467 cap-sd-highspeed;
468 disable-wp;
469 max-frequency = <150000000>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>;
472 sd-uhs-sdr12;
473 sd-uhs-sdr25;
474 sd-uhs-sdr50;
475 sd-uhs-ddr50;
476 sd-uhs-sdr104;
477 vmmc-supply = <&vcc_3v3_s3>;
478 vqmmc-supply = <&vccio_sd_s0>;
479 status = "okay";
480 };
481
482 &spi2 {
483 assigned-clocks = <&cru CLK_SPI2>;
484 assigned-clock-rates = <200000000>;
485 num-cs = <1>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
488 status = "okay";
489
490 pmic@0 {
491 compatible = "rockchip,rk806";
492 reg = <0x0>;
493 interrupt-parent = <&gpio0>;
494 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
495 gpio-controller;
496 #gpio-cells = <2>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
499 <&rk806_dvs2_null>, <&rk806_dvs3_null>;
500 spi-max-frequency = <1000000>;
501 system-power-controller;
502 vcc1-supply = <&vcc5v0_sys>;
503 vcc2-supply = <&vcc5v0_sys>;
504 vcc3-supply = <&vcc5v0_sys>;
505 vcc4-supply = <&vcc5v0_sys>;
506 vcc5-supply = <&vcc5v0_sys>;
507 vcc6-supply = <&vcc5v0_sys>;
508 vcc7-supply = <&vcc5v0_sys>;
509 vcc8-supply = <&vcc5v0_sys>;
510 vcc9-supply = <&vcc5v0_sys>;
511 vcc10-supply = <&vcc5v0_sys>;
512 vcc11-supply = <&vcc_2v0_pldo_s3>;
513 vcc12-supply = <&vcc5v0_sys>;
514 vcc13-supply = <&vcc_1v1_nldo_s3>;
515 vcc14-supply = <&vcc_1v1_nldo_s3>;
516 vcca-supply = <&vcc5v0_sys>;
517
518 rk806_dvs1_null: dvs1-null-pins {
519 pins = "gpio_pwrctrl1";
520 function = "pin_fun0";
521 };
522
523 rk806_dvs2_null: dvs2-null-pins {
524 pins = "gpio_pwrctrl2";
525 function = "pin_fun0";
526 };
527
528 rk806_dvs3_null: dvs3-null-pins {
529 pins = "gpio_pwrctrl3";
530 function = "pin_fun0";
531 };
532
533 regulators {
534 vdd_gpu_s0: dcdc-reg1 {
535 regulator-boot-on;
536 regulator-min-microvolt = <550000>;
537 regulator-max-microvolt = <950000>;
538 regulator-ramp-delay = <12500>;
539 regulator-name = "vdd_gpu_s0";
540 regulator-enable-ramp-delay = <400>;
541
542 regulator-state-mem {
543 regulator-off-in-suspend;
544 };
545 };
546
547 vdd_cpu_lit_s0: dcdc-reg2 {
548 regulator-name = "vdd_cpu_lit_s0";
549 regulator-always-on;
550 regulator-boot-on;
551 regulator-min-microvolt = <550000>;
552 regulator-max-microvolt = <950000>;
553 regulator-ramp-delay = <12500>;
554
555 regulator-state-mem {
556 regulator-off-in-suspend;
557 };
558 };
559
560 vdd_log_s0: dcdc-reg3 {
561 regulator-name = "vdd_log_s0";
562 regulator-always-on;
563 regulator-boot-on;
564 regulator-min-microvolt = <675000>;
565 regulator-max-microvolt = <750000>;
566 regulator-ramp-delay = <12500>;
567
568 regulator-state-mem {
569 regulator-off-in-suspend;
570 regulator-suspend-microvolt = <750000>;
571 };
572 };
573
574 vdd_vdenc_s0: dcdc-reg4 {
575 regulator-name = "vdd_vdenc_s0";
576 regulator-always-on;
577 regulator-boot-on;
578 regulator-min-microvolt = <550000>;
579 regulator-max-microvolt = <950000>;
580 regulator-ramp-delay = <12500>;
581
582 regulator-state-mem {
583 regulator-off-in-suspend;
584 };
585 };
586
587 vdd_ddr_s0: dcdc-reg5 {
588 regulator-name = "vdd_ddr_s0";
589 regulator-always-on;
590 regulator-boot-on;
591 regulator-min-microvolt = <675000>;
592 regulator-max-microvolt = <900000>;
593 regulator-ramp-delay = <12500>;
594
595 regulator-state-mem {
596 regulator-off-in-suspend;
597 regulator-suspend-microvolt = <850000>;
598 };
599 };
600
601 vdd2_ddr_s3: dcdc-reg6 {
602 regulator-name = "vdd2_ddr_s3";
603 regulator-always-on;
604 regulator-boot-on;
605
606 regulator-state-mem {
607 regulator-on-in-suspend;
608 };
609 };
610
611 vcc_2v0_pldo_s3: dcdc-reg7 {
612 regulator-name = "vdd_2v0_pldo_s3";
613 regulator-always-on;
614 regulator-boot-on;
615 regulator-min-microvolt = <2000000>;
616 regulator-max-microvolt = <2000000>;
617 regulator-ramp-delay = <12500>;
618
619 regulator-state-mem {
620 regulator-on-in-suspend;
621 regulator-suspend-microvolt = <2000000>;
622 };
623 };
624
625 vcc_3v3_s3: dcdc-reg8 {
626 regulator-name = "vcc_3v3_s3";
627 regulator-always-on;
628 regulator-boot-on;
629 regulator-min-microvolt = <3300000>;
630 regulator-max-microvolt = <3300000>;
631
632 regulator-state-mem {
633 regulator-on-in-suspend;
634 regulator-suspend-microvolt = <3300000>;
635 };
636 };
637
638 vddq_ddr_s0: dcdc-reg9 {
639 regulator-name = "vddq_ddr_s0";
640 regulator-always-on;
641 regulator-boot-on;
642
643 regulator-state-mem {
644 regulator-off-in-suspend;
645 };
646 };
647
648 vcc_1v8_s3: dcdc-reg10 {
649 regulator-name = "vcc_1v8_s3";
650 regulator-always-on;
651 regulator-boot-on;
652 regulator-min-microvolt = <1800000>;
653 regulator-max-microvolt = <1800000>;
654
655 regulator-state-mem {
656 regulator-on-in-suspend;
657 regulator-suspend-microvolt = <1800000>;
658 };
659 };
660
661 vcca_1v8_s0: pldo-reg1 {
662 regulator-name = "vcca_1v8_s0";
663 regulator-always-on;
664 regulator-boot-on;
665 regulator-min-microvolt = <1800000>;
666 regulator-max-microvolt = <1800000>;
667
668 regulator-state-mem {
669 regulator-off-in-suspend;
670 };
671 };
672
673 vcc_1v8_s0: pldo-reg2 {
674 regulator-name = "vcc_1v8_s0";
675 regulator-always-on;
676 regulator-boot-on;
677 regulator-min-microvolt = <1800000>;
678 regulator-max-microvolt = <1800000>;
679
680 regulator-state-mem {
681 regulator-off-in-suspend;
682 regulator-suspend-microvolt = <1800000>;
683 };
684 };
685
686 vdda_1v2_s0: pldo-reg3 {
687 regulator-name = "vdda_1v2_s0";
688 regulator-always-on;
689 regulator-boot-on;
690 regulator-min-microvolt = <1200000>;
691 regulator-max-microvolt = <1200000>;
692
693 regulator-state-mem {
694 regulator-off-in-suspend;
695 };
696 };
697
698 vcca_3v3_s0: pldo-reg4 {
699 regulator-name = "vcca_3v3_s0";
700 regulator-always-on;
701 regulator-boot-on;
702 regulator-min-microvolt = <3300000>;
703 regulator-max-microvolt = <3300000>;
704 regulator-ramp-delay = <12500>;
705
706 regulator-state-mem {
707 regulator-off-in-suspend;
708 };
709 };
710
711 vccio_sd_s0: pldo-reg5 {
712 regulator-name = "vccio_sd_s0";
713 regulator-always-on;
714 regulator-boot-on;
715 regulator-min-microvolt = <1800000>;
716 regulator-max-microvolt = <3300000>;
717 regulator-ramp-delay = <12500>;
718
719 regulator-state-mem {
720 regulator-off-in-suspend;
721 };
722 };
723
724 pldo6_s3: pldo-reg6 {
725 regulator-name = "pldo6_s3";
726 regulator-always-on;
727 regulator-boot-on;
728 regulator-min-microvolt = <1800000>;
729 regulator-max-microvolt = <1800000>;
730
731 regulator-state-mem {
732 regulator-on-in-suspend;
733 regulator-suspend-microvolt = <1800000>;
734 };
735 };
736
737 vdd_0v75_s3: nldo-reg1 {
738 regulator-name = "vdd_0v75_s3";
739 regulator-always-on;
740 regulator-boot-on;
741 regulator-min-microvolt = <750000>;
742 regulator-max-microvolt = <750000>;
743
744 regulator-state-mem {
745 regulator-on-in-suspend;
746 regulator-suspend-microvolt = <750000>;
747 };
748 };
749
750 vdda_ddr_pll_s0: nldo-reg2 {
751 regulator-name = "vdda_ddr_pll_s0";
752 regulator-always-on;
753 regulator-boot-on;
754 regulator-min-microvolt = <850000>;
755 regulator-max-microvolt = <850000>;
756
757 regulator-state-mem {
758 regulator-off-in-suspend;
759 regulator-suspend-microvolt = <850000>;
760 };
761 };
762
763 vdda_0v75_s0: nldo-reg3 {
764 regulator-name = "vdda_0v75_s0";
765 regulator-always-on;
766 regulator-boot-on;
767 regulator-min-microvolt = <750000>;
768 regulator-max-microvolt = <750000>;
769
770 regulator-state-mem {
771 regulator-off-in-suspend;
772 };
773 };
774
775 vdda_0v85_s0: nldo-reg4 {
776 regulator-name = "vdda_0v85_s0";
777 regulator-always-on;
778 regulator-boot-on;
779 regulator-min-microvolt = <850000>;
780 regulator-max-microvolt = <850000>;
781
782 regulator-state-mem {
783 regulator-off-in-suspend;
784 };
785 };
786
787 vdd_0v75_s0: nldo-reg5 {
788 regulator-name = "vdd_0v75_s0";
789 regulator-always-on;
790 regulator-boot-on;
791 regulator-min-microvolt = <750000>;
792 regulator-max-microvolt = <750000>;
793
794 regulator-state-mem {
795 regulator-off-in-suspend;
796 };
797 };
798 };
799 };
800 };
801
802 &tsadc {
803 status = "okay";
804 };
805
806 &u2phy2 {
807 status = "okay";
808 };
809
810 &u2phy2_host {
811 phy-supply = <&vcc_5v0_usb_a>;
812 status = "okay";
813 };
814
815 &u2phy3 {
816 status = "okay";
817 };
818
819 &u2phy3_host {
820 status = "okay";
821 };
822
823 /* Mule-ATtiny debug UART; typically baudrate 9600 */
824 &uart0 {
825 pinctrl-0 = <&uart0m0_xfer>;
826 status = "okay";
827 };
828
829 /* Main debug interface on P20 micro-USB B port and P21 header */
830 &uart2 {
831 pinctrl-0 = <&uart2m0_xfer>;
832 status = "okay";
833 };
834
835 /* RS485 on P19 */
836 &uart3 {
837 pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>;
838 linux,rs485-enabled-at-boot-time;
839 status = "okay";
840 };
841
842 /* Mule-ATtiny UPDI flashing UART */
843 &uart7 {
844 pinctrl-0 = <&uart7m0_xfer>;
845 status = "okay";
846 };
847
848 /* host0 on P10 USB-A */
849 &usb_host0_ehci {
850 status = "okay";
851 };
852
853 /* host0 on P10 USB-A */
854 &usb_host0_ohci {
855 status = "okay";
856 };
857
858 /* host1 on M.2 E-key */
859 &usb_host1_ehci {
860 status = "okay";
861 };
862
863 /* host1 on M.2 E-key */
864 &usb_host1_ohci {
865 status = "okay";
866 };
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