1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2 /*
3 * Spreadtrum SC9836 SoC DTS file
4 *
5 * Copyright (C) 2014, Spreadtrum Communications Inc.
6 */
7
8 #include "sharkl64.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10
11 / {
12 compatible = "sprd,sc9836";
13
14 cpus {
15 #address-cells = <2>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a53";
21 reg = <0x0 0x0>;
22 enable-method = "psci";
23 };
24
25 cpu1: cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a53";
28 reg = <0x0 0x1>;
29 enable-method = "psci";
30 };
31
32 cpu2: cpu@2 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a53";
35 reg = <0x0 0x2>;
36 enable-method = "psci";
37 };
38
39 cpu3: cpu@3 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a53";
42 reg = <0x0 0x3>;
43 enable-method = "psci";
44 };
45 };
46
47 etf@10003000 {
48 compatible = "arm,coresight-tmc", "arm,primecell";
49 reg = <0 0x10003000 0 0x1000>;
50 clocks = <&clk26mhz>;
51 clock-names = "apb_pclk";
52 in-ports {
53 port {
54 etf_in: endpoint {
55 remote-endpoint = <&funnel_out_port0>;
56 };
57 };
58 };
59 };
60
61 funnel@10001000 {
62 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
63 reg = <0 0x10001000 0 0x1000>;
64 clocks = <&clk26mhz>;
65 clock-names = "apb_pclk";
66
67 out-ports {
68 port {
69 funnel_out_port0: endpoint {
70 remote-endpoint = <&etf_in>;
71 };
72 };
73 };
74
75 in-ports {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 port@0 {
80 reg = <0>;
81 funnel_in_port0: endpoint {
82 remote-endpoint = <&etm0_out>;
83 };
84 };
85
86 port@1 {
87 reg = <1>;
88 funnel_in_port1: endpoint {
89 remote-endpoint = <&etm1_out>;
90 };
91 };
92
93 port@2 {
94 reg = <2>;
95 funnel_in_port2: endpoint {
96 remote-endpoint = <&etm2_out>;
97 };
98 };
99
100 port@3 {
101 reg = <3>;
102 funnel_in_port3: endpoint {
103 remote-endpoint = <&etm3_out>;
104 };
105 };
106
107 port@4 {
108 reg = <4>;
109 funnel_in_port4: endpoint {
110 remote-endpoint = <&stm_out>;
111 };
112 };
113 /* Other input ports aren't connected to anyone */
114 };
115 };
116
117 etm@10440000 {
118 compatible = "arm,coresight-etm4x", "arm,primecell";
119 reg = <0 0x10440000 0 0x1000>;
120
121 cpu = <&cpu0>;
122 clocks = <&clk26mhz>;
123 clock-names = "apb_pclk";
124 out-ports {
125 port {
126 etm0_out: endpoint {
127 remote-endpoint = <&funnel_in_port0>;
128 };
129 };
130 };
131 };
132
133 etm@10540000 {
134 compatible = "arm,coresight-etm4x", "arm,primecell";
135 reg = <0 0x10540000 0 0x1000>;
136
137 cpu = <&cpu1>;
138 clocks = <&clk26mhz>;
139 clock-names = "apb_pclk";
140 out-ports {
141 port {
142 etm1_out: endpoint {
143 remote-endpoint = <&funnel_in_port1>;
144 };
145 };
146 };
147 };
148
149 etm@10640000 {
150 compatible = "arm,coresight-etm4x", "arm,primecell";
151 reg = <0 0x10640000 0 0x1000>;
152
153 cpu = <&cpu2>;
154 clocks = <&clk26mhz>;
155 clock-names = "apb_pclk";
156 out-ports {
157 port {
158 etm2_out: endpoint {
159 remote-endpoint = <&funnel_in_port2>;
160 };
161 };
162 };
163 };
164
165 etm@10740000 {
166 compatible = "arm,coresight-etm4x", "arm,primecell";
167 reg = <0 0x10740000 0 0x1000>;
168
169 cpu = <&cpu3>;
170 clocks = <&clk26mhz>;
171 clock-names = "apb_pclk";
172 out-ports {
173 port {
174 etm3_out: endpoint {
175 remote-endpoint = <&funnel_in_port3>;
176 };
177 };
178 };
179 };
180
181 stm@10006000 {
182 compatible = "arm,coresight-stm", "arm,primecell";
183 reg = <0 0x10006000 0 0x1000>,
184 <0 0x01000000 0 0x180000>;
185 reg-names = "stm-base", "stm-stimulus-base";
186 clocks = <&clk26mhz>;
187 clock-names = "apb_pclk";
188 out-ports {
189 port {
190 stm_out: endpoint {
191 remote-endpoint = <&funnel_in_port4>;
192 };
193 };
194 };
195 };
196
197 gic: interrupt-controller@12001000 {
198 compatible = "arm,gic-400";
199 reg = <0 0x12001000 0 0x1000>,
200 <0 0x12002000 0 0x2000>,
201 <0 0x12004000 0 0x2000>,
202 <0 0x12006000 0 0x2000>;
203 #interrupt-cells = <3>;
204 interrupt-controller;
205 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206 };
207
208 psci {
209 compatible = "arm,psci";
210 method = "smc";
211 cpu_on = <0xc4000003>;
212 cpu_off = <0x84000002>;
213 cpu_suspend = <0xc4000001>;
214 };
215
216 timer {
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
222 };
223 };
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