1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6 /dts-v1/;
7 /plugin/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "k3-pinctrl.h"
11
12 &mcasp1 {
13 status = "disabled";
14 };
15
16 &main_pmx0 {
17 gpmc0_pins_default: gpmc0-pins-default {
18 pinctrl-single,pins = <
19 AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
20 AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
21 AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
22 AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
23 AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
24 AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
25 AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
26 AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */
27 AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
28 AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
29 AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */
30 AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */
31 AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */
32 AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */
33 AM62X_IOPAD(0x00a0, PIN_OUTPUT, 0) /* (J20) GPMC0_WPn */
34 >;
35 };
36 };
37
38 &elm0 {
39 status = "okay";
40 };
41
42 &gpmc0 {
43 status = "okay";
44 pinctrl-names = "default";
45 pinctrl-0 = <&gpmc0_pins_default>;
46 #address-cells = <2>;
47 #size-cells = <1>;
48
49 nand@0,0 {
50 compatible = "ti,am64-nand";
51 reg = <0 0 64>; /* device IO registers */
52 interrupt-parent = <&gpmc0>;
53 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
54 <1 IRQ_TYPE_NONE>; /* termcount */
55 rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
56 ti,nand-xfer-type = "prefetch-polled";
57 ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
58 ti,elm-id = <&elm0>;
59 nand-bus-width = <8>;
60 gpmc,device-width = <1>;
61 gpmc,sync-clk-ps = <0>;
62 gpmc,cs-on-ns = <0>;
63 gpmc,cs-rd-off-ns = <40>;
64 gpmc,cs-wr-off-ns = <40>;
65 gpmc,adv-on-ns = <0>;
66 gpmc,adv-rd-off-ns = <25>;
67 gpmc,adv-wr-off-ns = <25>;
68 gpmc,we-on-ns = <0>;
69 gpmc,we-off-ns = <20>;
70 gpmc,oe-on-ns = <3>;
71 gpmc,oe-off-ns = <30>;
72 gpmc,access-ns = <30>;
73 gpmc,rd-cycle-ns = <40>;
74 gpmc,wr-cycle-ns = <40>;
75 gpmc,bus-turnaround-ns = <0>;
76 gpmc,cycle2cycle-delay-ns = <0>;
77 gpmc,clk-activation-ns = <0>;
78 gpmc,wr-access-ns = <40>;
79 gpmc,wr-data-mux-bus-ns = <0>;
80
81 partitions {
82 compatible = "fixed-partitions";
83 #address-cells = <1>;
84 #size-cells = <1>;
85
86 partition@0 {
87 label = "NAND.tiboot3";
88 reg = <0x00000000 0x00200000>; /* 2M */
89 };
90 partition@200000 {
91 label = "NAND.tispl";
92 reg = <0x00200000 0x00200000>; /* 2M */
93 };
94 partition@400000 {
95 label = "NAND.tiboot3.backup"; /* 2M */
96 reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
97 };
98 partition@600000 {
99 label = "NAND.u-boot";
100 reg = <0x00600000 0x00400000>; /* 4M */
101 };
102 partition@a00000 {
103 label = "NAND.u-boot-env";
104 reg = <0x00a00000 0x00040000>; /* 256K */
105 };
106 partition@a40000 {
107 label = "NAND.u-boot-env.backup";
108 reg = <0x00a40000 0x00040000>; /* 256K */
109 };
110 partition@a80000 {
111 label = "NAND.file-system";
112 reg = <0x00a80000 0x3f580000>;
113 };
114 };
115 };
116 };
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