1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for AM625 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_main {
9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x00 0x70000000 0x00 0x10000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
15 };
16
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
21 ranges;
22 #interrupt-cells = <3>;
23 interrupt-controller;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
30 /*
31 * vcpumntirq:
32 * virtual CPU interface maintenance interrupt
33 */
34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
35
36 gic_its: msi-controller@1820000 {
37 compatible = "arm,gic-v3-its";
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
40 msi-controller;
41 #msi-cells = <1>;
42 };
43 };
44
45 main_conf: bus@100000 {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges = <0x0 0x00 0x00100000 0x20000>;
50
51 phy_gmii_sel: phy@4044 {
52 compatible = "ti,am654-phy-gmii-sel";
53 reg = <0x4044 0x8>;
54 #phy-cells = <1>;
55 };
56
57 epwm_tbclk: clock-controller@4130 {
58 compatible = "ti,am62-epwm-tbclk";
59 reg = <0x4130 0x4>;
60 #clock-cells = <1>;
61 };
62
63 audio_refclk0: clock-controller@82e0 {
64 compatible = "ti,am62-audio-refclk";
65 reg = <0x82e0 0x4>;
66 clocks = <&k3_clks 157 0>;
67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
69 #clock-cells = <0>;
70 };
71
72 audio_refclk1: clock-controller@82e4 {
73 compatible = "ti,am62-audio-refclk";
74 reg = <0x82e4 0x4>;
75 clocks = <&k3_clks 157 10>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
78 #clock-cells = <0>;
79 };
80 };
81
82 dmss: bus@48000000 {
83 bootph-all;
84 compatible = "simple-bus";
85 #address-cells = <2>;
86 #size-cells = <2>;
87 dma-ranges;
88 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
89
90 ti,sci-dev-id = <25>;
91
92 secure_proxy_main: mailbox@4d000000 {
93 bootph-all;
94 compatible = "ti,am654-secure-proxy";
95 #mbox-cells = <1>;
96 reg-names = "target_data", "rt", "scfg";
97 reg = <0x00 0x4d000000 0x00 0x80000>,
98 <0x00 0x4a600000 0x00 0x80000>,
99 <0x00 0x4a400000 0x00 0x80000>;
100 interrupt-names = "rx_012";
101 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
102 };
103
104 inta_main_dmss: interrupt-controller@48000000 {
105 compatible = "ti,sci-inta";
106 reg = <0x00 0x48000000 0x00 0x100000>;
107 #interrupt-cells = <0>;
108 interrupt-controller;
109 interrupt-parent = <&gic500>;
110 msi-controller;
111 ti,sci = <&dmsc>;
112 ti,sci-dev-id = <28>;
113 ti,interrupt-ranges = <4 68 36>;
114 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
115 };
116
117 main_bcdma: dma-controller@485c0100 {
118 compatible = "ti,am64-dmss-bcdma";
119 reg = <0x00 0x485c0100 0x00 0x100>,
120 <0x00 0x4c000000 0x00 0x20000>,
121 <0x00 0x4a820000 0x00 0x20000>,
122 <0x00 0x4aa40000 0x00 0x20000>,
123 <0x00 0x4bc00000 0x00 0x100000>,
124 <0x00 0x48600000 0x00 0x8000>,
125 <0x00 0x484a4000 0x00 0x2000>,
126 <0x00 0x484c2000 0x00 0x2000>,
127 <0x00 0x48420000 0x00 0x2000>;
128 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
129 "ring", "tchan", "rchan", "bchan";
130 msi-parent = <&inta_main_dmss>;
131 #dma-cells = <3>;
132
133 ti,sci = <&dmsc>;
134 ti,sci-dev-id = <26>;
135 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
136 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
137 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
138 };
139
140 main_pktdma: dma-controller@485c0000 {
141 compatible = "ti,am64-dmss-pktdma";
142 reg = <0x00 0x485c0000 0x00 0x100>,
143 <0x00 0x4a800000 0x00 0x20000>,
144 <0x00 0x4aa00000 0x00 0x20000>,
145 <0x00 0x4b800000 0x00 0x200000>,
146 <0x00 0x485e0000 0x00 0x10000>,
147 <0x00 0x484a0000 0x00 0x2000>,
148 <0x00 0x484c0000 0x00 0x2000>,
149 <0x00 0x48430000 0x00 0x1000>;
150 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
151 "ring", "tchan", "rchan", "rflow";
152 msi-parent = <&inta_main_dmss>;
153 #dma-cells = <2>;
154
155 ti,sci = <&dmsc>;
156 ti,sci-dev-id = <30>;
157 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
158 <0x24>, /* CPSW_TX_CHAN */
159 <0x25>, /* SAUL_TX_0_CHAN */
160 <0x26>; /* SAUL_TX_1_CHAN */
161 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
162 <0x11>, /* RING_CPSW_TX_CHAN */
163 <0x12>, /* RING_SAUL_TX_0_CHAN */
164 <0x13>; /* RING_SAUL_TX_1_CHAN */
165 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
166 <0x2b>, /* CPSW_RX_CHAN */
167 <0x2d>, /* SAUL_RX_0_CHAN */
168 <0x2f>, /* SAUL_RX_1_CHAN */
169 <0x31>, /* SAUL_RX_2_CHAN */
170 <0x33>; /* SAUL_RX_3_CHAN */
171 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
172 <0x2c>, /* FLOW_CPSW_RX_CHAN */
173 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
174 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
175 };
176 };
177
178 dmsc: system-controller@44043000 {
179 bootph-all;
180 compatible = "ti,k2g-sci";
181 ti,host-id = <12>;
182 mbox-names = "rx", "tx";
183 mboxes = <&secure_proxy_main 12>,
184 <&secure_proxy_main 13>;
185 reg-names = "debug_messages";
186 reg = <0x00 0x44043000 0x00 0xfe0>;
187
188 k3_pds: power-controller {
189 bootph-all;
190 compatible = "ti,sci-pm-domain";
191 #power-domain-cells = <2>;
192 };
193
194 k3_clks: clock-controller {
195 bootph-all;
196 compatible = "ti,k2g-sci-clk";
197 #clock-cells = <2>;
198 };
199
200 k3_reset: reset-controller {
201 bootph-all;
202 compatible = "ti,sci-reset";
203 #reset-cells = <2>;
204 };
205 };
206
207 crypto: crypto@40900000 {
208 compatible = "ti,am62-sa3ul";
209 reg = <0x00 0x40900000 0x00 0x1200>;
210 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
211 <&main_pktdma 0x7507 0>;
212 dma-names = "tx", "rx1", "rx2";
213 };
214
215 secure_proxy_sa3: mailbox@43600000 {
216 bootph-pre-ram;
217 compatible = "ti,am654-secure-proxy";
218 #mbox-cells = <1>;
219 reg-names = "target_data", "rt", "scfg";
220 reg = <0x00 0x43600000 0x00 0x10000>,
221 <0x00 0x44880000 0x00 0x20000>,
222 <0x00 0x44860000 0x00 0x20000>;
223 /*
224 * Marked Disabled:
225 * Node is incomplete as it is meant for bootloaders and
226 * firmware on non-MPU processors
227 */
228 status = "disabled";
229 };
230
231 main_pmx0: pinctrl@f4000 {
232 bootph-all;
233 compatible = "pinctrl-single";
234 reg = <0x00 0xf4000 0x00 0x2ac>;
235 #pinctrl-cells = <1>;
236 pinctrl-single,register-width = <32>;
237 pinctrl-single,function-mask = <0xffffffff>;
238 };
239
240 main_esm: esm@420000 {
241 bootph-pre-ram;
242 compatible = "ti,j721e-esm";
243 reg = <0x00 0x420000 0x00 0x1000>;
244 /* Interrupt sources: rti0, rti1, rti15, wrti0, rti2, rti3 */
245 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
246 };
247
248 main_timer0: timer@2400000 {
249 bootph-all;
250 compatible = "ti,am654-timer";
251 reg = <0x00 0x2400000 0x00 0x400>;
252 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&k3_clks 36 2>;
254 clock-names = "fck";
255 assigned-clocks = <&k3_clks 36 2>;
256 assigned-clock-parents = <&k3_clks 36 3>;
257 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
258 ti,timer-pwm;
259 };
260
261 main_timer1: timer@2410000 {
262 compatible = "ti,am654-timer";
263 reg = <0x00 0x2410000 0x00 0x400>;
264 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&k3_clks 37 2>;
266 clock-names = "fck";
267 assigned-clocks = <&k3_clks 37 2>;
268 assigned-clock-parents = <&k3_clks 37 3>;
269 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
270 ti,timer-pwm;
271 };
272
273 main_timer2: timer@2420000 {
274 compatible = "ti,am654-timer";
275 reg = <0x00 0x2420000 0x00 0x400>;
276 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&k3_clks 38 2>;
278 clock-names = "fck";
279 assigned-clocks = <&k3_clks 38 2>;
280 assigned-clock-parents = <&k3_clks 38 3>;
281 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
282 ti,timer-pwm;
283 };
284
285 main_timer3: timer@2430000 {
286 compatible = "ti,am654-timer";
287 reg = <0x00 0x2430000 0x00 0x400>;
288 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&k3_clks 39 2>;
290 clock-names = "fck";
291 assigned-clocks = <&k3_clks 39 2>;
292 assigned-clock-parents = <&k3_clks 39 3>;
293 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
294 ti,timer-pwm;
295 };
296
297 main_timer4: timer@2440000 {
298 compatible = "ti,am654-timer";
299 reg = <0x00 0x2440000 0x00 0x400>;
300 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&k3_clks 40 2>;
302 clock-names = "fck";
303 assigned-clocks = <&k3_clks 40 2>;
304 assigned-clock-parents = <&k3_clks 40 3>;
305 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
306 ti,timer-pwm;
307 };
308
309 main_timer5: timer@2450000 {
310 compatible = "ti,am654-timer";
311 reg = <0x00 0x2450000 0x00 0x400>;
312 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&k3_clks 41 2>;
314 clock-names = "fck";
315 assigned-clocks = <&k3_clks 41 2>;
316 assigned-clock-parents = <&k3_clks 41 3>;
317 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
318 ti,timer-pwm;
319 };
320
321 main_timer6: timer@2460000 {
322 compatible = "ti,am654-timer";
323 reg = <0x00 0x2460000 0x00 0x400>;
324 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&k3_clks 42 2>;
326 clock-names = "fck";
327 assigned-clocks = <&k3_clks 42 2>;
328 assigned-clock-parents = <&k3_clks 42 3>;
329 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
330 ti,timer-pwm;
331 };
332
333 main_timer7: timer@2470000 {
334 compatible = "ti,am654-timer";
335 reg = <0x00 0x2470000 0x00 0x400>;
336 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&k3_clks 43 2>;
338 clock-names = "fck";
339 assigned-clocks = <&k3_clks 43 2>;
340 assigned-clock-parents = <&k3_clks 43 3>;
341 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
342 ti,timer-pwm;
343 };
344
345 main_uart0: serial@2800000 {
346 compatible = "ti,am64-uart", "ti,am654-uart";
347 reg = <0x00 0x02800000 0x00 0x100>;
348 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
349 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
350 clocks = <&k3_clks 146 0>;
351 clock-names = "fclk";
352 status = "disabled";
353 };
354
355 main_uart1: serial@2810000 {
356 compatible = "ti,am64-uart", "ti,am654-uart";
357 reg = <0x00 0x02810000 0x00 0x100>;
358 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
359 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
360 clocks = <&k3_clks 152 0>;
361 clock-names = "fclk";
362 status = "disabled";
363 };
364
365 main_uart2: serial@2820000 {
366 compatible = "ti,am64-uart", "ti,am654-uart";
367 reg = <0x00 0x02820000 0x00 0x100>;
368 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
369 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
370 clocks = <&k3_clks 153 0>;
371 clock-names = "fclk";
372 status = "disabled";
373 };
374
375 main_uart3: serial@2830000 {
376 compatible = "ti,am64-uart", "ti,am654-uart";
377 reg = <0x00 0x02830000 0x00 0x100>;
378 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
379 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
380 clocks = <&k3_clks 154 0>;
381 clock-names = "fclk";
382 status = "disabled";
383 };
384
385 main_uart4: serial@2840000 {
386 compatible = "ti,am64-uart", "ti,am654-uart";
387 reg = <0x00 0x02840000 0x00 0x100>;
388 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
389 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
390 clocks = <&k3_clks 155 0>;
391 clock-names = "fclk";
392 status = "disabled";
393 };
394
395 main_uart5: serial@2850000 {
396 compatible = "ti,am64-uart", "ti,am654-uart";
397 reg = <0x00 0x02850000 0x00 0x100>;
398 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
399 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
400 clocks = <&k3_clks 156 0>;
401 clock-names = "fclk";
402 status = "disabled";
403 };
404
405 main_uart6: serial@2860000 {
406 compatible = "ti,am64-uart", "ti,am654-uart";
407 reg = <0x00 0x02860000 0x00 0x100>;
408 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
409 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
410 clocks = <&k3_clks 158 0>;
411 clock-names = "fclk";
412 status = "disabled";
413 };
414
415 main_i2c0: i2c@20000000 {
416 compatible = "ti,am64-i2c", "ti,omap4-i2c";
417 reg = <0x00 0x20000000 0x00 0x100>;
418 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
422 clocks = <&k3_clks 102 2>;
423 clock-names = "fck";
424 status = "disabled";
425 };
426
427 main_i2c1: i2c@20010000 {
428 compatible = "ti,am64-i2c", "ti,omap4-i2c";
429 reg = <0x00 0x20010000 0x00 0x100>;
430 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
434 clocks = <&k3_clks 103 2>;
435 clock-names = "fck";
436 status = "disabled";
437 };
438
439 main_i2c2: i2c@20020000 {
440 compatible = "ti,am64-i2c", "ti,omap4-i2c";
441 reg = <0x00 0x20020000 0x00 0x100>;
442 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
446 clocks = <&k3_clks 104 2>;
447 clock-names = "fck";
448 status = "disabled";
449 };
450
451 main_i2c3: i2c@20030000 {
452 compatible = "ti,am64-i2c", "ti,omap4-i2c";
453 reg = <0x00 0x20030000 0x00 0x100>;
454 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
458 clocks = <&k3_clks 105 2>;
459 clock-names = "fck";
460 status = "disabled";
461 };
462
463 main_spi0: spi@20100000 {
464 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
465 reg = <0x00 0x20100000 0x00 0x400>;
466 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
470 clocks = <&k3_clks 141 0>;
471 status = "disabled";
472 };
473
474 main_spi1: spi@20110000 {
475 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
476 reg = <0x00 0x20110000 0x00 0x400>;
477 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
481 clocks = <&k3_clks 142 0>;
482 status = "disabled";
483 };
484
485 main_spi2: spi@20120000 {
486 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
487 reg = <0x00 0x20120000 0x00 0x400>;
488 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
492 clocks = <&k3_clks 143 0>;
493 status = "disabled";
494 };
495
496 main_gpio_intr: interrupt-controller@a00000 {
497 compatible = "ti,sci-intr";
498 reg = <0x00 0x00a00000 0x00 0x800>;
499 ti,intr-trigger-type = <1>;
500 interrupt-controller;
501 interrupt-parent = <&gic500>;
502 #interrupt-cells = <1>;
503 ti,sci = <&dmsc>;
504 ti,sci-dev-id = <3>;
505 ti,interrupt-ranges = <0 32 16>;
506 };
507
508 main_gpio0: gpio@600000 {
509 compatible = "ti,am64-gpio", "ti,keystone-gpio";
510 reg = <0x0 0x00600000 0x0 0x100>;
511 gpio-ranges = <&main_pmx0 0 0 32>,
512 <&main_pmx0 32 33 38>,
513 <&main_pmx0 70 72 22>;
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-parent = <&main_gpio_intr>;
517 interrupts = <190>, <191>, <192>,
518 <193>, <194>, <195>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
521 ti,ngpio = <92>;
522 ti,davinci-gpio-unbanked = <0>;
523 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
524 clocks = <&k3_clks 77 0>;
525 clock-names = "gpio";
526 };
527
528 main_gpio1: gpio@601000 {
529 compatible = "ti,am64-gpio", "ti,keystone-gpio";
530 reg = <0x0 0x00601000 0x0 0x100>;
531 gpio-controller;
532 gpio-ranges = <&main_pmx0 0 94 41>,
533 <&main_pmx0 41 136 6>,
534 <&main_pmx0 47 143 3>,
535 <&main_pmx0 50 149 2>;
536 #gpio-cells = <2>;
537 interrupt-parent = <&main_gpio_intr>;
538 interrupts = <180>, <181>, <182>,
539 <183>, <184>, <185>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 ti,ngpio = <52>;
543 ti,davinci-gpio-unbanked = <0>;
544 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
545 clocks = <&k3_clks 78 0>;
546 clock-names = "gpio";
547 };
548
549 sdhci0: mmc@fa10000 {
550 compatible = "ti,am62-sdhci";
551 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
552 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
553 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
554 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
555 clock-names = "clk_ahb", "clk_xin";
556 assigned-clocks = <&k3_clks 57 6>;
557 assigned-clock-parents = <&k3_clks 57 8>;
558 bus-width = <8>;
559 mmc-ddr-1_8v;
560 mmc-hs200-1_8v;
561 ti,clkbuf-sel = <0x7>;
562 ti,otap-del-sel-legacy = <0x0>;
563 ti,otap-del-sel-mmc-hs = <0x0>;
564 ti,otap-del-sel-ddr52 = <0x5>;
565 ti,otap-del-sel-hs200 = <0x5>;
566 ti,itap-del-sel-legacy = <0xa>;
567 ti,itap-del-sel-mmc-hs = <0x1>;
568 status = "disabled";
569 };
570
571 sdhci1: mmc@fa00000 {
572 compatible = "ti,am62-sdhci";
573 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
574 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
575 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
576 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
577 clock-names = "clk_ahb", "clk_xin";
578 bus-width = <4>;
579 ti,clkbuf-sel = <0x7>;
580 ti,otap-del-sel-legacy = <0x8>;
581 ti,otap-del-sel-sd-hs = <0x0>;
582 ti,otap-del-sel-sdr12 = <0x0>;
583 ti,otap-del-sel-sdr25 = <0x0>;
584 ti,otap-del-sel-sdr50 = <0x8>;
585 ti,otap-del-sel-sdr104 = <0x7>;
586 ti,otap-del-sel-ddr50 = <0x4>;
587 ti,itap-del-sel-legacy = <0xa>;
588 ti,itap-del-sel-sd-hs = <0x1>;
589 ti,itap-del-sel-sdr12 = <0xa>;
590 ti,itap-del-sel-sdr25 = <0x1>;
591 status = "disabled";
592 };
593
594 sdhci2: mmc@fa20000 {
595 compatible = "ti,am62-sdhci";
596 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
597 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
598 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
599 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
600 clock-names = "clk_ahb", "clk_xin";
601 bus-width = <4>;
602 ti,clkbuf-sel = <0x7>;
603 ti,otap-del-sel-legacy = <0x8>;
604 ti,otap-del-sel-sd-hs = <0x0>;
605 ti,otap-del-sel-sdr12 = <0x0>;
606 ti,otap-del-sel-sdr25 = <0x0>;
607 ti,otap-del-sel-sdr50 = <0x8>;
608 ti,otap-del-sel-sdr104 = <0x7>;
609 ti,otap-del-sel-ddr50 = <0x8>;
610 ti,itap-del-sel-legacy = <0xa>;
611 ti,itap-del-sel-sd-hs = <0xa>;
612 ti,itap-del-sel-sdr12 = <0xa>;
613 ti,itap-del-sel-sdr25 = <0x1>;
614 status = "disabled";
615 };
616
617 usbss0: dwc3-usb@f900000 {
618 compatible = "ti,am62-usb";
619 reg = <0x00 0x0f900000 0x00 0x800>,
620 <0x00 0x0f908000 0x00 0x400>;
621 clocks = <&k3_clks 161 3>;
622 clock-names = "ref";
623 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
624 #address-cells = <2>;
625 #size-cells = <2>;
626 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
627 ranges;
628 status = "disabled";
629
630 usb0: usb@31000000 {
631 compatible = "snps,dwc3";
632 reg = <0x00 0x31000000 0x00 0x50000>;
633 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
634 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
635 interrupt-names = "host", "peripheral";
636 maximum-speed = "high-speed";
637 dr_mode = "otg";
638 snps,usb2-gadget-lpm-disable;
639 snps,usb2-lpm-disable;
640 };
641 };
642
643 usbss1: dwc3-usb@f910000 {
644 compatible = "ti,am62-usb";
645 reg = <0x00 0x0f910000 0x00 0x800>,
646 <0x00 0x0f918000 0x00 0x400>;
647 clocks = <&k3_clks 162 3>;
648 clock-names = "ref";
649 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
650 #address-cells = <2>;
651 #size-cells = <2>;
652 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
653 ranges;
654 status = "disabled";
655
656 usb1: usb@31100000 {
657 compatible = "snps,dwc3";
658 reg = <0x00 0x31100000 0x00 0x50000>;
659 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
660 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
661 interrupt-names = "host", "peripheral";
662 maximum-speed = "high-speed";
663 dr_mode = "otg";
664 snps,usb2-gadget-lpm-disable;
665 snps,usb2-lpm-disable;
666 };
667 };
668
669 fss: bus@fc00000 {
670 compatible = "simple-bus";
671 reg = <0x00 0x0fc00000 0x00 0x70000>;
672 #address-cells = <2>;
673 #size-cells = <2>;
674 ranges;
675
676 ospi0: spi@fc40000 {
677 compatible = "ti,am654-ospi", "cdns,qspi-nor";
678 reg = <0x00 0x0fc40000 0x00 0x100>,
679 <0x05 0x00000000 0x01 0x00000000>;
680 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
681 cdns,fifo-depth = <256>;
682 cdns,fifo-width = <4>;
683 cdns,trigger-address = <0x0>;
684 clocks = <&k3_clks 75 7>;
685 assigned-clocks = <&k3_clks 75 7>;
686 assigned-clock-parents = <&k3_clks 75 8>;
687 assigned-clock-rates = <166666666>;
688 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
689 #address-cells = <1>;
690 #size-cells = <0>;
691 status = "disabled";
692 };
693 };
694
695 gpu: gpu@fd00000 {
696 compatible = "ti,am62-gpu", "img,img-axe";
697 reg = <0x00 0x0fd00000 0x00 0x20000>;
698 clocks = <&k3_clks 187 0>;
699 clock-names = "core";
700 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
701 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
702 };
703
704 cpsw3g: ethernet@8000000 {
705 compatible = "ti,am642-cpsw-nuss";
706 #address-cells = <2>;
707 #size-cells = <2>;
708 reg = <0x00 0x08000000 0x00 0x200000>;
709 reg-names = "cpsw_nuss";
710 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
711 clocks = <&k3_clks 13 0>;
712 assigned-clocks = <&k3_clks 13 3>;
713 assigned-clock-parents = <&k3_clks 13 11>;
714 clock-names = "fck";
715 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
716
717 dmas = <&main_pktdma 0xc600 15>,
718 <&main_pktdma 0xc601 15>,
719 <&main_pktdma 0xc602 15>,
720 <&main_pktdma 0xc603 15>,
721 <&main_pktdma 0xc604 15>,
722 <&main_pktdma 0xc605 15>,
723 <&main_pktdma 0xc606 15>,
724 <&main_pktdma 0xc607 15>,
725 <&main_pktdma 0x4600 15>;
726 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
727 "tx7", "rx";
728
729 ethernet-ports {
730 #address-cells = <1>;
731 #size-cells = <0>;
732
733 cpsw_port1: port@1 {
734 reg = <1>;
735 ti,mac-only;
736 label = "port1";
737 phys = <&phy_gmii_sel 1>;
738 mac-address = [00 00 00 00 00 00];
739 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
740 };
741
742 cpsw_port2: port@2 {
743 reg = <2>;
744 ti,mac-only;
745 label = "port2";
746 phys = <&phy_gmii_sel 2>;
747 mac-address = [00 00 00 00 00 00];
748 };
749 };
750
751 cpsw3g_mdio: mdio@f00 {
752 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
753 reg = <0x00 0xf00 0x00 0x100>;
754 #address-cells = <1>;
755 #size-cells = <0>;
756 clocks = <&k3_clks 13 0>;
757 clock-names = "fck";
758 bus_freq = <1000000>;
759 status = "disabled";
760 };
761
762 cpts@3d000 {
763 compatible = "ti,j721e-cpts";
764 reg = <0x00 0x3d000 0x00 0x400>;
765 clocks = <&k3_clks 13 3>;
766 clock-names = "cpts";
767 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
768 interrupt-names = "cpts";
769 ti,cpts-ext-ts-inputs = <4>;
770 ti,cpts-periodic-outputs = <2>;
771 };
772 };
773
774 dss: dss@30200000 {
775 compatible = "ti,am625-dss";
776 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
777 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
778 <0x00 0x30206000 0x00 0x1000>, /* vid */
779 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
780 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
781 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
782 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
783 <0x00 0x30201000 0x00 0x1000>; /* common1 */
784 reg-names = "common", "vidl1", "vid",
785 "ovr1", "ovr2", "vp1", "vp2", "common1";
786 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
787 clocks = <&k3_clks 186 6>,
788 <&dss_vp1_clk>,
789 <&k3_clks 186 2>;
790 clock-names = "fck", "vp1", "vp2";
791 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
792 status = "disabled";
793
794 dss_ports: ports {
795 #address-cells = <1>;
796 #size-cells = <0>;
797 };
798 };
799
800 hwspinlock: spinlock@2a000000 {
801 compatible = "ti,am64-hwspinlock";
802 reg = <0x00 0x2a000000 0x00 0x1000>;
803 #hwlock-cells = <1>;
804 };
805
806 mailbox0_cluster0: mailbox@29000000 {
807 compatible = "ti,am64-mailbox";
808 reg = <0x00 0x29000000 0x00 0x200>;
809 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
811 #mbox-cells = <1>;
812 ti,mbox-num-users = <4>;
813 ti,mbox-num-fifos = <16>;
814 };
815
816 ecap0: pwm@23100000 {
817 compatible = "ti,am3352-ecap";
818 #pwm-cells = <3>;
819 reg = <0x00 0x23100000 0x00 0x100>;
820 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
821 clocks = <&k3_clks 51 0>;
822 clock-names = "fck";
823 status = "disabled";
824 };
825
826 ecap1: pwm@23110000 {
827 compatible = "ti,am3352-ecap";
828 #pwm-cells = <3>;
829 reg = <0x00 0x23110000 0x00 0x100>;
830 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
831 clocks = <&k3_clks 52 0>;
832 clock-names = "fck";
833 status = "disabled";
834 };
835
836 ecap2: pwm@23120000 {
837 compatible = "ti,am3352-ecap";
838 #pwm-cells = <3>;
839 reg = <0x00 0x23120000 0x00 0x100>;
840 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
841 clocks = <&k3_clks 53 0>;
842 clock-names = "fck";
843 status = "disabled";
844 };
845
846 main_mcan0: can@20701000 {
847 compatible = "bosch,m_can";
848 reg = <0x00 0x20701000 0x00 0x200>,
849 <0x00 0x20708000 0x00 0x8000>;
850 reg-names = "m_can", "message_ram";
851 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
852 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
853 clock-names = "hclk", "cclk";
854 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
856 interrupt-names = "int0", "int1";
857 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
858 status = "disabled";
859 };
860
861 main_rti0: watchdog@e000000 {
862 compatible = "ti,j7-rti-wdt";
863 reg = <0x00 0x0e000000 0x00 0x100>;
864 clocks = <&k3_clks 125 0>;
865 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
866 assigned-clocks = <&k3_clks 125 0>;
867 assigned-clock-parents = <&k3_clks 125 2>;
868 };
869
870 main_rti1: watchdog@e010000 {
871 compatible = "ti,j7-rti-wdt";
872 reg = <0x00 0x0e010000 0x00 0x100>;
873 clocks = <&k3_clks 126 0>;
874 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
875 assigned-clocks = <&k3_clks 126 0>;
876 assigned-clock-parents = <&k3_clks 126 2>;
877 };
878
879 main_rti2: watchdog@e020000 {
880 compatible = "ti,j7-rti-wdt";
881 reg = <0x00 0x0e020000 0x00 0x100>;
882 clocks = <&k3_clks 127 0>;
883 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
884 assigned-clocks = <&k3_clks 127 0>;
885 assigned-clock-parents = <&k3_clks 127 2>;
886 };
887
888 main_rti3: watchdog@e030000 {
889 compatible = "ti,j7-rti-wdt";
890 reg = <0x00 0x0e030000 0x00 0x100>;
891 clocks = <&k3_clks 128 0>;
892 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
893 assigned-clocks = <&k3_clks 128 0>;
894 assigned-clock-parents = <&k3_clks 128 2>;
895 };
896
897 main_rti15: watchdog@e0f0000 {
898 compatible = "ti,j7-rti-wdt";
899 reg = <0x00 0x0e0f0000 0x00 0x100>;
900 clocks = <&k3_clks 130 0>;
901 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
902 assigned-clocks = <&k3_clks 130 0>;
903 assigned-clock-parents = <&k3_clks 130 2>;
904 };
905
906 epwm0: pwm@23000000 {
907 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
908 #pwm-cells = <3>;
909 reg = <0x00 0x23000000 0x00 0x100>;
910 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
911 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
912 clock-names = "tbclk", "fck";
913 status = "disabled";
914 };
915
916 epwm1: pwm@23010000 {
917 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
918 #pwm-cells = <3>;
919 reg = <0x00 0x23010000 0x00 0x100>;
920 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
921 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
922 clock-names = "tbclk", "fck";
923 status = "disabled";
924 };
925
926 epwm2: pwm@23020000 {
927 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
928 #pwm-cells = <3>;
929 reg = <0x00 0x23020000 0x00 0x100>;
930 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
931 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
932 clock-names = "tbclk", "fck";
933 status = "disabled";
934 };
935
936 mcasp0: audio-controller@2b00000 {
937 compatible = "ti,am33xx-mcasp-audio";
938 reg = <0x00 0x02b00000 0x00 0x2000>,
939 <0x00 0x02b08000 0x00 0x400>;
940 reg-names = "mpu", "dat";
941 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
943 interrupt-names = "tx", "rx";
944
945 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
946 dma-names = "tx", "rx";
947
948 clocks = <&k3_clks 190 0>;
949 clock-names = "fck";
950 assigned-clocks = <&k3_clks 190 0>;
951 assigned-clock-parents = <&k3_clks 190 2>;
952 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
953 status = "disabled";
954 };
955
956 mcasp1: audio-controller@2b10000 {
957 compatible = "ti,am33xx-mcasp-audio";
958 reg = <0x00 0x02b10000 0x00 0x2000>,
959 <0x00 0x02b18000 0x00 0x400>;
960 reg-names = "mpu", "dat";
961 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
963 interrupt-names = "tx", "rx";
964
965 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
966 dma-names = "tx", "rx";
967
968 clocks = <&k3_clks 191 0>;
969 clock-names = "fck";
970 assigned-clocks = <&k3_clks 191 0>;
971 assigned-clock-parents = <&k3_clks 191 2>;
972 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
973 status = "disabled";
974 };
975
976 mcasp2: audio-controller@2b20000 {
977 compatible = "ti,am33xx-mcasp-audio";
978 reg = <0x00 0x02b20000 0x00 0x2000>,
979 <0x00 0x02b28000 0x00 0x400>;
980 reg-names = "mpu", "dat";
981 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
983 interrupt-names = "tx", "rx";
984
985 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
986 dma-names = "tx", "rx";
987
988 clocks = <&k3_clks 192 0>;
989 clock-names = "fck";
990 assigned-clocks = <&k3_clks 192 0>;
991 assigned-clock-parents = <&k3_clks 192 2>;
992 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
993 status = "disabled";
994 };
995
996 ti_csi2rx0: ticsi2rx@30102000 {
997 compatible = "ti,j721e-csi2rx-shim";
998 dmas = <&main_bcdma 0 0x4700 0>;
999 dma-names = "rx0";
1000 reg = <0x00 0x30102000 0x00 0x1000>;
1001 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1002 #address-cells = <2>;
1003 #size-cells = <2>;
1004 ranges;
1005 status = "disabled";
1006
1007 cdns_csi2rx0: csi-bridge@30101000 {
1008 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1009 reg = <0x00 0x30101000 0x00 0x1000>;
1010 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1011 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1012 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1013 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1014 phys = <&dphy0>;
1015 phy-names = "dphy";
1016
1017 ports {
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020
1021 csi0_port0: port@0 {
1022 reg = <0>;
1023 status = "disabled";
1024 };
1025
1026 csi0_port1: port@1 {
1027 reg = <1>;
1028 status = "disabled";
1029 };
1030
1031 csi0_port2: port@2 {
1032 reg = <2>;
1033 status = "disabled";
1034 };
1035
1036 csi0_port3: port@3 {
1037 reg = <3>;
1038 status = "disabled";
1039 };
1040
1041 csi0_port4: port@4 {
1042 reg = <4>;
1043 status = "disabled";
1044 };
1045 };
1046 };
1047 };
1048
1049 dphy0: phy@30110000 {
1050 compatible = "cdns,dphy-rx";
1051 reg = <0x00 0x30110000 0x00 0x1100>;
1052 #phy-cells = <0>;
1053 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1054 status = "disabled";
1055 };
1056
1057 gpmc0: memory-controller@3b000000 {
1058 compatible = "ti,am64-gpmc";
1059 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
1060 clocks = <&k3_clks 80 0>;
1061 clock-names = "fck";
1062 reg = <0x00 0x03b000000 0x00 0x400>,
1063 <0x00 0x050000000 0x00 0x8000000>;
1064 reg-names = "cfg", "data";
1065 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1066 gpmc,num-cs = <3>;
1067 gpmc,num-waitpins = <2>;
1068 #address-cells = <2>;
1069 #size-cells = <1>;
1070 interrupt-controller;
1071 #interrupt-cells = <2>;
1072 gpio-controller;
1073 #gpio-cells = <2>;
1074 status = "disabled";
1075 };
1076
1077 elm0: ecc@25010000 {
1078 compatible = "ti,am64-elm";
1079 reg = <0x00 0x25010000 0x00 0x2000>;
1080 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1081 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1082 clocks = <&k3_clks 54 0>;
1083 clock-names = "fck";
1084 status = "disabled";
1085 };
1086 };
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