1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for AM625 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_mcu {
9 mcu_pmx0: pinctrl@4084000 {
10 bootph-all;
11 compatible = "pinctrl-single";
12 reg = <0x00 0x04084000 0x00 0x88>;
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
16 };
17
18 mcu_esm: esm@4100000 {
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
21 reg = <0x00 0x4100000 0x00 0x1000>;
22 /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
23 ti,esm-pins = <0>, <1>, <2>, <85>;
24 };
25
26 /*
27 * The MCU domain timer interrupts are routed only to the ESM module,
28 * and not currently available for Linux. The MCU domain timers are
29 * of limited use without interrupts, and likely reserved by the ESM.
30 */
31 mcu_timer0: timer@4800000 {
32 compatible = "ti,am654-timer";
33 reg = <0x00 0x4800000 0x00 0x400>;
34 clocks = <&k3_clks 35 2>;
35 clock-names = "fck";
36 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
37 ti,timer-pwm;
38 status = "reserved";
39 };
40
41 mcu_timer1: timer@4810000 {
42 compatible = "ti,am654-timer";
43 reg = <0x00 0x4810000 0x00 0x400>;
44 clocks = <&k3_clks 48 2>;
45 clock-names = "fck";
46 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
47 ti,timer-pwm;
48 status = "reserved";
49 };
50
51 mcu_timer2: timer@4820000 {
52 compatible = "ti,am654-timer";
53 reg = <0x00 0x4820000 0x00 0x400>;
54 clocks = <&k3_clks 49 2>;
55 clock-names = "fck";
56 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
57 ti,timer-pwm;
58 status = "reserved";
59 };
60
61 mcu_timer3: timer@4830000 {
62 compatible = "ti,am654-timer";
63 reg = <0x00 0x4830000 0x00 0x400>;
64 clocks = <&k3_clks 50 2>;
65 clock-names = "fck";
66 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
67 ti,timer-pwm;
68 status = "reserved";
69 };
70
71 mcu_uart0: serial@4a00000 {
72 compatible = "ti,am64-uart", "ti,am654-uart";
73 reg = <0x00 0x04a00000 0x00 0x100>;
74 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
75 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
76 clocks = <&k3_clks 149 0>;
77 clock-names = "fclk";
78 status = "disabled";
79 };
80
81 mcu_i2c0: i2c@4900000 {
82 compatible = "ti,am64-i2c", "ti,omap4-i2c";
83 reg = <0x00 0x04900000 0x00 0x100>;
84 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
88 clocks = <&k3_clks 106 2>;
89 clock-names = "fck";
90 status = "disabled";
91 };
92
93 mcu_spi0: spi@4b00000 {
94 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
95 reg = <0x00 0x04b00000 0x00 0x400>;
96 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
100 clocks = <&k3_clks 147 0>;
101 status = "disabled";
102 };
103
104 mcu_spi1: spi@4b10000 {
105 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
106 reg = <0x00 0x04b10000 0x00 0x400>;
107 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
111 clocks = <&k3_clks 148 0>;
112 status = "disabled";
113 };
114
115 mcu_gpio_intr: interrupt-controller@4210000 {
116 compatible = "ti,sci-intr";
117 reg = <0x00 0x04210000 0x00 0x200>;
118 ti,intr-trigger-type = <1>;
119 interrupt-controller;
120 interrupt-parent = <&gic500>;
121 #interrupt-cells = <1>;
122 ti,sci = <&dmsc>;
123 ti,sci-dev-id = <5>;
124 ti,interrupt-ranges = <0 104 4>;
125 };
126
127 mcu_gpio0: gpio@4201000 {
128 compatible = "ti,am64-gpio", "ti,keystone-gpio";
129 reg = <0x00 0x4201000 0x00 0x100>;
130 gpio-controller;
131 #gpio-cells = <2>;
132 interrupt-parent = <&mcu_gpio_intr>;
133 interrupts = <30>, <31>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
136 ti,ngpio = <24>;
137 ti,davinci-gpio-unbanked = <0>;
138 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
139 clocks = <&k3_clks 79 0>;
140 clock-names = "gpio";
141 };
142
143 mcu_rti0: watchdog@4880000 {
144 compatible = "ti,j7-rti-wdt";
145 reg = <0x00 0x04880000 0x00 0x100>;
146 clocks = <&k3_clks 131 0>;
147 power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
148 assigned-clocks = <&k3_clks 131 0>;
149 assigned-clock-parents = <&k3_clks 131 2>;
150 /* Tightly coupled to M4F */
151 status = "reserved";
152 };
153
154 mcu_mcan0: can@4e08000 {
155 compatible = "bosch,m_can";
156 reg = <0x00 0x4e08000 0x00 0x200>,
157 <0x00 0x4e00000 0x00 0x8000>;
158 reg-names = "m_can", "message_ram";
159 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
160 clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
161 clock-names = "hclk", "cclk";
162 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
163 status = "disabled";
164 };
165
166 mcu_mcan1: can@4e18000 {
167 compatible = "bosch,m_can";
168 reg = <0x00 0x4e18000 0x00 0x200>,
169 <0x00 0x4e10000 0x00 0x8000>;
170 reg-names = "m_can", "message_ram";
171 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
172 clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
173 clock-names = "hclk", "cclk";
174 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
175 status = "disabled";
176 };
177 };
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