1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
4 * Author: Matt McKee <mmckee@phytec.com>
5 *
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
7 * Author: Wadim Egorov <w.egorov@phytec.de>
8 *
9 * Product homepage:
10 * https://www.phytec.com/product/phyboard-am64x
11 */
12
13 /dts-v1/;
14
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
18 #include <dt-bindings/leds/leds-pca9532.h>
19 #include <dt-bindings/phy/phy.h>
20 #include "k3-am642.dtsi"
21 #include "k3-am64-phycore-som.dtsi"
22
23 #include "k3-serdes.h"
24
25 / {
26 compatible = "phytec,am642-phyboard-electra-rdk",
27 "phytec,am64-phycore-som", "ti,am642";
28 model = "PHYTEC phyBOARD-Electra-AM64x RDK";
29
30 aliases {
31 ethernet1 = &icssg0_emac0;
32 ethernet2 = &icssg0_emac1;
33 mmc1 = &sdhci1;
34 serial2 = &main_uart0;
35 serial3 = &main_uart1;
36 };
37
38 chosen {
39 stdout-path = &main_uart0;
40 };
41
42 can_tc1: can-phy0 {
43 compatible = "ti,tcan1042";
44 pinctrl-names = "default";
45 pinctrl-0 = <&can_tc1_pins_default>;
46 #phy-cells = <0>;
47 max-bitrate = <8000000>;
48 standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
49 };
50
51 can_tc2: can-phy1 {
52 compatible = "ti,tcan1042";
53 pinctrl-names = "default";
54 pinctrl-0 = <&can_tc2_pins_default>;
55 #phy-cells = <0>;
56 max-bitrate = <8000000>;
57 standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>;
58 };
59
60 /* Dual Ethernet application node on PRU-ICSSG0 */
61 ethernet {
62 compatible = "ti,am642-icssg-prueth";
63 pinctrl-names = "default";
64 pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
65
66 interrupt-parent = <&icssg0_intc>;
67 interrupts = <24 0 2>, <25 1 3>;
68 interrupt-names = "tx_ts0", "tx_ts1";
69
70 sram = <&oc_sram>;
71 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
72 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
73 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
74 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
75 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
76 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
77
78 dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
79 <&main_pktdma 0xc101 15>, /* egress slice 0 */
80 <&main_pktdma 0xc102 15>, /* egress slice 0 */
81 <&main_pktdma 0xc103 15>, /* egress slice 0 */
82 <&main_pktdma 0xc104 15>, /* egress slice 1 */
83 <&main_pktdma 0xc105 15>, /* egress slice 1 */
84 <&main_pktdma 0xc106 15>, /* egress slice 1 */
85 <&main_pktdma 0xc107 15>, /* egress slice 1 */
86 <&main_pktdma 0x4100 15>, /* ingress slice 0 */
87 <&main_pktdma 0x4101 15>; /* ingress slice 1 */
88 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
89 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
90 "rx0", "rx1";
91
92 ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
93 ti,pruss-gp-mux-sel = <2>, /* MII mode */
94 <2>,
95 <2>,
96 <2>, /* MII mode */
97 <2>,
98 <2>;
99
100 ti,mii-g-rt = <&icssg0_mii_g_rt>;
101 ti,mii-rt = <&icssg0_mii_rt>;
102 ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
103
104 ethernet-ports {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 icssg0_emac0: port@0 {
108 reg = <0>;
109 phy-handle = <&icssg0_phy1>;
110 phy-mode = "rgmii-id";
111 /* Filled in by bootloader */
112 local-mac-address = [00 00 00 00 00 00];
113 ti,syscon-rgmii-delay = <&main_conf 0x4100>;
114 };
115
116 icssg0_emac1: port@1 {
117 reg = <1>;
118 phy-handle = <&icssg0_phy2>;
119 phy-mode = "rgmii-id";
120 /* Filled in by bootloader */
121 local-mac-address = [00 00 00 00 00 00];
122 ti,syscon-rgmii-delay = <&main_conf 0x4104>;
123 };
124 };
125 };
126
127 keys {
128 compatible = "gpio-keys";
129 autorepeat;
130 pinctrl-names = "default";
131 pinctrl-0 = <&gpio_keys_pins_default>;
132
133 key-home {
134 label = "home";
135 linux,code = <KEY_HOME>;
136 gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>;
137 };
138
139 key-menu {
140 label = "menu";
141 linux,code = <KEY_MENU>;
142 gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
143 };
144 };
145
146 leds {
147 compatible = "gpio-leds";
148 pinctrl-names = "default";
149 pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
150
151 led-1 {
152 color = <LED_COLOR_ID_RED>;
153 gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>;
154 linux,default-trigger = "mmc0";
155 function = LED_FUNCTION_DISK;
156 };
157
158 led-2 {
159 color = <LED_COLOR_ID_GREEN>;
160 gpios = <&main_gpio0 16 GPIO_ACTIVE_HIGH>;
161 linux,default-trigger = "mmc1";
162 function = LED_FUNCTION_DISK;
163 };
164 };
165
166 vcc_3v3_mmc: regulator-sd {
167 /* TPS22963C */
168 compatible = "regulator-fixed";
169 regulator-name = "VCC_3V3_MMC";
170 regulator-min-microvolt = <3300000>;
171 regulator-max-microvolt = <3300000>;
172 regulator-boot-on;
173 regulator-always-on;
174 };
175 };
176
177 &main_pmx0 {
178 can_tc1_pins_default: can-tc1-default-pins {
179 pinctrl-single,pins = <
180 AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */
181 >;
182 };
183
184 can_tc2_pins_default: can-tc2-default-pins {
185 pinctrl-single,pins = <
186 AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
187 >;
188 };
189
190 clkout0_pins_default: clkout0-default-pins {
191 pinctrl-single,pins = <
192 AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* (A19) EXT_REFCLK1.CLKOUT0 */
193 >;
194 };
195
196 gpio_keys_pins_default: gpio-keys-default-pins {
197 pinctrl-single,pins = <
198 AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
199 AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */
200 >;
201 };
202
203 icssg0_mdio_pins_default: icssg0-mdio-default-pins {
204 pinctrl-single,pins = <
205 AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
206 AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
207 AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
208 AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
209 >;
210 };
211
212 icssg0_rgmii1_pins_default: icssg0-rgmii1-default-pins {
213 pinctrl-single,pins = <
214 AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
215 AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
216 AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
217 AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
218 AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
219 AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
220 AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
221 AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
222 AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
223 AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
224 AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
225 AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
226 >;
227 };
228
229 icssg0_rgmii2_pins_default: icssg0-rgmii2-default-pins {
230 pinctrl-single,pins = <
231 AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
232 AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
233 AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
234 AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
235 AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
236 AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
237 AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */
238 AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */
239 AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */
240 AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */
241 AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */
242 AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
243 >;
244 };
245
246 main_i2c1_pins_default: main-i2c1-default-pins {
247 pinctrl-single,pins = <
248 AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */
249 AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */
250 >;
251 };
252
253 main_mcan0_pins_default: main-mcan0-default-pins {
254 pinctrl-single,pins = <
255 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
256 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
257 >;
258 };
259
260 main_mcan1_pins_default: main-mcan1-default-pins {
261 pinctrl-single,pins = <
262 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
263 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
264 >;
265 };
266
267 main_mmc1_pins_default: main-mmc1-default-pins {
268 pinctrl-single,pins = <
269 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
270 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
271 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
272 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
273 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
274 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
275 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
276 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
277 >;
278 };
279
280 main_spi0_pins_default: main-spi0-default-pins {
281 pinctrl-single,pins = <
282 AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) /* (C13) SPI0_CS1.GPIO1_43 */
283 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
284 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
285 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
286 >;
287 };
288
289 main_uart0_pins_default: main-uart0-default-pins {
290 pinctrl-single,pins = <
291 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
292 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
293 >;
294 };
295
296 main_uart1_pins_default: main-uart1-default-pins {
297 pinctrl-single,pins = <
298 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
299 AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
300 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
301 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
302 >;
303 };
304
305 main_usb0_pins_default: main-usb0-default-pins {
306 pinctrl-single,pins = <
307 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
308 >;
309 };
310
311 user_leds_pins_default: user-leds-default-pins {
312 pinctrl-single,pins = <
313 AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
314 AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
315 >;
316 };
317 };
318
319 &icssg0_mdio {
320 pinctrl-names = "default";
321 pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
322 status = "okay";
323
324 icssg0_phy1: ethernet-phy@1 {
325 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
326 reg = <0x1>;
327 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
328 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
329 reset-gpios = <&main_gpio1 18 GPIO_ACTIVE_LOW>;
330 reset-assert-us = <1000>;
331 reset-deassert-us = <1000>;
332 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
333 };
334
335 icssg0_phy2: ethernet-phy@2 {
336 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
337 reg = <0x2>;
338 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
339 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
340 reset-gpios = <&main_gpio1 19 GPIO_ACTIVE_LOW>;
341 reset-assert-us = <1000>;
342 reset-deassert-us = <1000>;
343 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
344 };
345 };
346
347 &main_i2c1 {
348 status = "okay";
349 pinctrl-names = "default";
350 pinctrl-0 = <&main_i2c1_pins_default>;
351 clock-frequency = <400000>;
352
353 eeprom@51 {
354 compatible = "atmel,24c02";
355 pagesize = <16>;
356 reg = <0x51>;
357 };
358
359 led-controller@62 {
360 compatible = "nxp,pca9533";
361 reg = <0x62>;
362
363 led-3 {
364 label = "red:user";
365 type = <PCA9532_TYPE_LED>;
366 };
367
368 led-4 {
369 label = "green:user";
370 type = <PCA9532_TYPE_LED>;
371 };
372
373 led-5 {
374 label = "blue:user";
375 type = <PCA9532_TYPE_LED>;
376 };
377 };
378 };
379
380 &main_mcan0 {
381 status = "okay";
382 pinctrl-names = "default";
383 pinctrl-0 = <&main_mcan0_pins_default>;
384 phys = <&can_tc1>;
385 };
386
387 &main_mcan1 {
388 status = "okay";
389 pinctrl-names = "default";
390 pinctrl-0 = <&main_mcan1_pins_default>;
391 phys = <&can_tc2>;
392 };
393
394 &main_spi0 {
395 status = "okay";
396 pinctrl-names = "default";
397 pinctrl-0 = <&main_spi0_pins_default>;
398 cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>;
399 ti,pindir-d0-out-d1-in;
400
401 tpm@1 {
402 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
403 reg = <1>;
404 spi-max-frequency = <10000000>;
405 };
406 };
407
408 &main_uart0 {
409 status = "okay";
410 pinctrl-names = "default";
411 pinctrl-0 = <&main_uart0_pins_default>;
412 };
413
414 &main_uart1 {
415 status = "okay";
416 pinctrl-names = "default";
417 pinctrl-0 = <&main_uart1_pins_default>;
418 uart-has-rtscts;
419 };
420
421 &sdhci1 {
422 status = "okay";
423 vmmc-supply = <&vcc_3v3_mmc>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&main_mmc1_pins_default>;
426 bus-width = <4>;
427 disable-wp;
428 no-1-8-v;
429 };
430
431 &serdes0 {
432 serdes0_pcie_usb_link: phy@0 {
433 reg = <0>;
434 cdns,num-lanes = <1>;
435 #phy-cells = <0>;
436 cdns,phy-type = <PHY_TYPE_USB3>;
437 resets = <&serdes_wiz0 1>;
438 };
439 };
440
441 &serdes_ln_ctrl {
442 idle-states = <AM64_SERDES0_LANE0_USB>;
443 };
444
445 &usbss0 {
446 ti,vbus-divider;
447 };
448
449 &usb0 {
450 pinctrl-names = "default";
451 pinctrl-0 = <&main_usb0_pins_default>;
452 dr_mode = "host";
453 maximum-speed = "super-speed";
454 phys = <&serdes0_pcie_usb_link>;
455 phy-names = "cdns3,usb3-phy";
456 };
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