1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
5 */
6
7 #include "k3-am642.dtsi"
8
9 / {
10 aliases {
11 i2c0 = &main_i2c0;
12 mmc0 = &sdhci0;
13 spi0 = &ospi0;
14 };
15
16 memory@80000000 {
17 device_type = "memory";
18 /* 1G RAM - default variant */
19 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
20
21 };
22
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
26 ranges;
27
28 secure_ddr: optee@9e800000 {
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
31 no-map;
32 };
33
34 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
35 compatible = "shared-dma-pool";
36 reg = <0x00 0xa0000000 0x00 0x100000>;
37 no-map;
38 };
39
40 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
41 compatible = "shared-dma-pool";
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 no-map;
44 };
45
46 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
47 compatible = "shared-dma-pool";
48 reg = <0x00 0xa1000000 0x00 0x100000>;
49 no-map;
50 };
51
52 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
53 compatible = "shared-dma-pool";
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 no-map;
56 };
57
58 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
59 compatible = "shared-dma-pool";
60 reg = <0x00 0xa2000000 0x00 0x100000>;
61 no-map;
62 };
63
64 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
65 compatible = "shared-dma-pool";
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
67 no-map;
68 };
69
70 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
71 compatible = "shared-dma-pool";
72 reg = <0x00 0xa3000000 0x00 0x100000>;
73 no-map;
74 };
75
76 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
77 compatible = "shared-dma-pool";
78 reg = <0x00 0xa3100000 0x00 0xf00000>;
79 no-map;
80 };
81
82 rtos_ipc_memory_region: ipc-memories@a5000000 {
83 reg = <0x00 0xa5000000 0x00 0x00800000>;
84 alignment = <0x1000>;
85 no-map;
86 };
87 };
88
89 reg_1v8: regulator-1v8 {
90 compatible = "regulator-fixed";
91 regulator-name = "V_1V8";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 regulator-always-on;
95 regulator-boot-on;
96 };
97 };
98
99 &main_i2c0 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&main_i2c0_pins>;
102 clock-frequency = <400000>;
103 status = "okay";
104
105 tmp1075: temperature-sensor@4a {
106 compatible = "ti,tmp1075";
107 reg = <0x4a>;
108 vs-supply = <®_1v8>;
109 };
110
111 eeprom0: eeprom@50 {
112 compatible = "st,24c02", "atmel,24c02";
113 reg = <0x50>;
114 vcc-supply = <®_1v8>;
115 pagesize = <16>;
116 read-only;
117 };
118
119 pcf85063: rtc@51 {
120 compatible = "nxp,pcf85063a";
121 reg = <0x51>;
122 quartz-load-femtofarads = <12500>;
123 };
124
125 eeprom1: eeprom@54 {
126 compatible = "st,24c64", "atmel,24c64";
127 reg = <0x54>;
128 vcc-supply = <®_1v8>;
129 pagesize = <32>;
130 };
131 };
132
133 &mailbox0_cluster2 {
134 status = "okay";
135
136 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
137 ti,mbox-rx = <0 0 2>;
138 ti,mbox-tx = <1 0 2>;
139 };
140
141 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
142 ti,mbox-rx = <2 0 2>;
143 ti,mbox-tx = <3 0 2>;
144 };
145 };
146
147 &mailbox0_cluster4 {
148 status = "okay";
149
150 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
151 ti,mbox-rx = <0 0 2>;
152 ti,mbox-tx = <1 0 2>;
153 };
154
155 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
156 ti,mbox-rx = <2 0 2>;
157 ti,mbox-tx = <3 0 2>;
158 };
159 };
160
161 &mailbox0_cluster6 {
162 status = "okay";
163
164 mbox_m4_0: mbox-m4-0 {
165 ti,mbox-rx = <0 0 2>;
166 ti,mbox-tx = <1 0 2>;
167 };
168 };
169
170 &main_r5fss0_core0 {
171 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
172 memory-region = <&main_r5fss0_core0_dma_memory_region>,
173 <&main_r5fss0_core0_memory_region>;
174 };
175
176 &main_r5fss0_core1 {
177 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
178 memory-region = <&main_r5fss0_core1_dma_memory_region>,
179 <&main_r5fss0_core1_memory_region>;
180 };
181
182 &main_r5fss1_core0 {
183 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
184 memory-region = <&main_r5fss1_core0_dma_memory_region>,
185 <&main_r5fss1_core0_memory_region>;
186 };
187
188 &main_r5fss1_core1 {
189 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
190 memory-region = <&main_r5fss1_core1_dma_memory_region>,
191 <&main_r5fss1_core1_memory_region>;
192 };
193
194 &ospi0 {
195 status = "okay";
196 pinctrl-names = "default";
197 pinctrl-0 = <&ospi0_pins>;
198
199 flash@0 {
200 compatible = "jedec,spi-nor";
201 reg = <0>;
202 spi-tx-bus-width = <8>;
203 spi-rx-bus-width = <8>;
204 spi-max-frequency = <84000000>;
205 cdns,tshsl-ns = <60>;
206 cdns,tsd2d-ns = <60>;
207 cdns,tchsh-ns = <60>;
208 cdns,tslch-ns = <60>;
209 cdns,read-delay = <2>;
210
211 partitions {
212 compatible = "fixed-partitions";
213 #address-cells = <1>;
214 #size-cells = <1>;
215
216 /* Filled by bootloader */
217 };
218 };
219 };
220
221 &sdhci0 {
222 status = "okay";
223 non-removable;
224 disable-wp;
225 no-sdio;
226 no-sd;
227 ti,driver-strength-ohm = <50>;
228 };
229
230 &main_pmx0 {
231 main_i2c0_pins: main-i2c0-pins {
232 pinctrl-single,pins = <
233 /* (A18) I2C0_SCL */
234 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0)
235 /* (B18) I2C0_SDA */
236 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0)
237 >;
238 };
239
240 ospi0_pins: ospi0-pins {
241 pinctrl-single,pins = <
242 /* (N20) OSPI0_CLK */
243 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0)
244 /* (L19) OSPI0_CSn0 */
245 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0)
246 /* (M19) OSPI0_D0 */
247 AM64X_IOPAD(0x000c, PIN_INPUT, 0)
248 /* (M18) OSPI0_D1 */
249 AM64X_IOPAD(0x0010, PIN_INPUT, 0)
250 /* (M20) OSPI0_D2 */
251 AM64X_IOPAD(0x0014, PIN_INPUT, 0)
252 /* (M21) OSPI0_D3 */
253 AM64X_IOPAD(0x0018, PIN_INPUT, 0)
254 /* (P21) OSPI0_D4 */
255 AM64X_IOPAD(0x001c, PIN_INPUT, 0)
256 /* (P20) OSPI0_D5 */
257 AM64X_IOPAD(0x0020, PIN_INPUT, 0)
258 /* (N18) OSPI0_D6 */
259 AM64X_IOPAD(0x0024, PIN_INPUT, 0)
260 /* (M17) OSPI0_D7 */
261 AM64X_IOPAD(0x0028, PIN_INPUT, 0)
262 /* (N19) OSPI0_DQS */
263 AM64X_IOPAD(0x0008, PIN_INPUT, 0)
264 >;
265 };
266 };
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