1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7 #include <dt-bindings/phy/phy-am654-serdes.h>
8
9 &cbass_main {
10 msmc_ram: sram@70000000 {
11 compatible = "mmio-sram";
12 reg = <0x0 0x70000000 0x0 0x200000>;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
16
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
19 };
20
21 sysfw-sram@f0000 {
22 reg = <0xf0000 0x10000>;
23 };
24
25 l3cache-sram@100000 {
26 reg = <0x100000 0x100000>;
27 };
28 };
29
30 gic500: interrupt-controller@1800000 {
31 compatible = "arm,gic-v3";
32 #address-cells = <2>;
33 #size-cells = <2>;
34 ranges;
35 #interrupt-cells = <3>;
36 interrupt-controller;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
42 /*
43 * vcpumntirq:
44 * virtual CPU interface maintenance interrupt
45 */
46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
47
48 gic_its: msi-controller@1820000 {
49 compatible = "arm,gic-v3-its";
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
52 msi-controller;
53 #msi-cells = <1>;
54 };
55 };
56
57 main_esm: esm@700000 {
58 compatible = "ti,j721e-esm";
59 reg = <0x00 0x700000 0x00 0x1000>;
60 bootph-pre-ram;
61 /* Interrupt sources: rti0, rti1, rti2, rti3 */
62 ti,esm-pins = <224>, <225>, <226>, <227>;
63 };
64
65 serdes0: serdes@900000 {
66 compatible = "ti,phy-am654-serdes";
67 reg = <0x0 0x900000 0x0 0x2000>;
68 reg-names = "serdes";
69 #phy-cells = <2>;
70 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
71 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
72 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
73 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
74 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
75 ti,serdes-clk = <&serdes0_clk>;
76 #clock-cells = <1>;
77 mux-controls = <&serdes0_mux 0>;
78 };
79
80 serdes1: serdes@910000 {
81 compatible = "ti,phy-am654-serdes";
82 reg = <0x0 0x910000 0x0 0x2000>;
83 reg-names = "serdes";
84 #phy-cells = <2>;
85 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
86 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
87 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
88 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
89 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
90 ti,serdes-clk = <&serdes1_clk>;
91 #clock-cells = <1>;
92 mux-controls = <&serdes1_mux 0>;
93 };
94
95 main_uart0: serial@2800000 {
96 compatible = "ti,am654-uart";
97 reg = <0x00 0x02800000 0x00 0x100>;
98 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
99 clock-frequency = <48000000>;
100 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
101 status = "disabled";
102 };
103
104 main_uart1: serial@2810000 {
105 compatible = "ti,am654-uart";
106 reg = <0x00 0x02810000 0x00 0x100>;
107 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
108 clock-frequency = <48000000>;
109 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
110 status = "disabled";
111 };
112
113 main_uart2: serial@2820000 {
114 compatible = "ti,am654-uart";
115 reg = <0x00 0x02820000 0x00 0x100>;
116 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
117 clock-frequency = <48000000>;
118 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
119 status = "disabled";
120 };
121
122 crypto: crypto@4e00000 {
123 compatible = "ti,am654-sa2ul";
124 reg = <0x0 0x4e00000 0x0 0x1200>;
125 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
126 #address-cells = <2>;
127 #size-cells = <2>;
128 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
129
130 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
131 <&main_udmap 0x4003>;
132 dma-names = "tx", "rx1", "rx2";
133
134 rng: rng@4e10000 {
135 compatible = "inside-secure,safexcel-eip76";
136 reg = <0x0 0x4e10000 0x0 0x7d>;
137 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
138 status = "disabled"; /* Used by OP-TEE */
139 };
140 };
141
142 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
143 main_timerio_input: pinctrl@104200 {
144 compatible = "pinctrl-single";
145 reg = <0x0 0x104200 0x0 0x30>;
146 #pinctrl-cells = <1>;
147 pinctrl-single,register-width = <32>;
148 pinctrl-single,function-mask = <0x0000001ff>;
149 };
150
151 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
152 main_timerio_output: pinctrl@104280 {
153 compatible = "pinctrl-single";
154 reg = <0x0 0x104280 0x0 0x20>;
155 #pinctrl-cells = <1>;
156 pinctrl-single,register-width = <32>;
157 pinctrl-single,function-mask = <0x0000000f>;
158 };
159
160 main_pmx0: pinctrl@11c000 {
161 compatible = "pinctrl-single";
162 reg = <0x0 0x11c000 0x0 0x2e4>;
163 #pinctrl-cells = <1>;
164 pinctrl-single,register-width = <32>;
165 pinctrl-single,function-mask = <0xffffffff>;
166 };
167
168 main_pmx1: pinctrl@11c2e8 {
169 compatible = "pinctrl-single";
170 reg = <0x0 0x11c2e8 0x0 0x24>;
171 #pinctrl-cells = <1>;
172 pinctrl-single,register-width = <32>;
173 pinctrl-single,function-mask = <0xffffffff>;
174 };
175
176 main_i2c0: i2c@2000000 {
177 compatible = "ti,am654-i2c", "ti,omap4-i2c";
178 reg = <0x0 0x2000000 0x0 0x100>;
179 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 clock-names = "fck";
183 clocks = <&k3_clks 110 1>;
184 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
185 status = "disabled";
186 };
187
188 main_i2c1: i2c@2010000 {
189 compatible = "ti,am654-i2c", "ti,omap4-i2c";
190 reg = <0x0 0x2010000 0x0 0x100>;
191 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 clock-names = "fck";
195 clocks = <&k3_clks 111 1>;
196 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
197 status = "disabled";
198 };
199
200 main_i2c2: i2c@2020000 {
201 compatible = "ti,am654-i2c", "ti,omap4-i2c";
202 reg = <0x0 0x2020000 0x0 0x100>;
203 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 clock-names = "fck";
207 clocks = <&k3_clks 112 1>;
208 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
209 status = "disabled";
210 };
211
212 main_i2c3: i2c@2030000 {
213 compatible = "ti,am654-i2c", "ti,omap4-i2c";
214 reg = <0x0 0x2030000 0x0 0x100>;
215 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
216 #address-cells = <1>;
217 #size-cells = <0>;
218 clock-names = "fck";
219 clocks = <&k3_clks 113 1>;
220 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
221 status = "disabled";
222 };
223
224 ecap0: pwm@3100000 {
225 compatible = "ti,am654-ecap", "ti,am3352-ecap";
226 #pwm-cells = <3>;
227 reg = <0x0 0x03100000 0x0 0x60>;
228 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
229 clocks = <&k3_clks 39 0>;
230 clock-names = "fck";
231 status = "disabled";
232 };
233
234 main_spi0: spi@2100000 {
235 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
236 reg = <0x0 0x2100000 0x0 0x400>;
237 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&k3_clks 137 1>;
239 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
243 dma-names = "tx0", "rx0";
244 status = "disabled";
245 };
246
247 main_spi1: spi@2110000 {
248 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
249 reg = <0x0 0x2110000 0x0 0x400>;
250 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&k3_clks 138 1>;
252 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 assigned-clocks = <&k3_clks 137 1>;
256 assigned-clock-rates = <48000000>;
257 status = "disabled";
258 };
259
260 main_spi2: spi@2120000 {
261 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
262 reg = <0x0 0x2120000 0x0 0x400>;
263 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&k3_clks 139 1>;
265 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 status = "disabled";
269 };
270
271 main_spi3: spi@2130000 {
272 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
273 reg = <0x0 0x2130000 0x0 0x400>;
274 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&k3_clks 140 1>;
276 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 status = "disabled";
280 };
281
282 main_spi4: spi@2140000 {
283 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
284 reg = <0x0 0x2140000 0x0 0x400>;
285 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&k3_clks 141 1>;
287 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 status = "disabled";
291 };
292
293 main_timer0: timer@2400000 {
294 compatible = "ti,am654-timer";
295 reg = <0x00 0x2400000 0x00 0x400>;
296 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&k3_clks 23 0>;
298 clock-names = "fck";
299 assigned-clocks = <&k3_clks 23 0>;
300 assigned-clock-parents = <&k3_clks 23 1>;
301 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
302 ti,timer-pwm;
303 };
304
305 main_timer1: timer@2410000 {
306 compatible = "ti,am654-timer";
307 reg = <0x00 0x2410000 0x00 0x400>;
308 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&k3_clks 24 0>;
310 clock-names = "fck";
311 assigned-clocks = <&k3_clks 24 0>;
312 assigned-clock-parents = <&k3_clks 24 1>;
313 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
314 ti,timer-pwm;
315 };
316
317 main_timer2: timer@2420000 {
318 compatible = "ti,am654-timer";
319 reg = <0x00 0x2420000 0x00 0x400>;
320 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&k3_clks 27 0>;
322 clock-names = "fck";
323 assigned-clocks = <&k3_clks 27 0>;
324 assigned-clock-parents = <&k3_clks 27 1>;
325 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
326 ti,timer-pwm;
327 };
328
329 main_timer3: timer@2430000 {
330 compatible = "ti,am654-timer";
331 reg = <0x00 0x2430000 0x00 0x400>;
332 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&k3_clks 28 0>;
334 clock-names = "fck";
335 assigned-clocks = <&k3_clks 28 0>;
336 assigned-clock-parents = <&k3_clks 28 1>;
337 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
338 ti,timer-pwm;
339 };
340
341 main_timer4: timer@2440000 {
342 compatible = "ti,am654-timer";
343 reg = <0x00 0x2440000 0x00 0x400>;
344 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&k3_clks 29 0>;
346 clock-names = "fck";
347 assigned-clocks = <&k3_clks 29 0>;
348 assigned-clock-parents = <&k3_clks 29 1>;
349 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
350 ti,timer-pwm;
351 };
352
353 main_timer5: timer@2450000 {
354 compatible = "ti,am654-timer";
355 reg = <0x00 0x2450000 0x00 0x400>;
356 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&k3_clks 30 0>;
358 clock-names = "fck";
359 assigned-clocks = <&k3_clks 30 0>;
360 assigned-clock-parents = <&k3_clks 30 1>;
361 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
362 ti,timer-pwm;
363 };
364
365 main_timer6: timer@2460000 {
366 compatible = "ti,am654-timer";
367 reg = <0x00 0x2460000 0x00 0x400>;
368 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&k3_clks 31 0>;
370 assigned-clocks = <&k3_clks 31 0>;
371 assigned-clock-parents = <&k3_clks 31 1>;
372 clock-names = "fck";
373 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
374 ti,timer-pwm;
375 };
376
377 main_timer7: timer@2470000 {
378 compatible = "ti,am654-timer";
379 reg = <0x00 0x2470000 0x00 0x400>;
380 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&k3_clks 32 0>;
382 clock-names = "fck";
383 assigned-clocks = <&k3_clks 32 0>;
384 assigned-clock-parents = <&k3_clks 32 1>;
385 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
386 ti,timer-pwm;
387 };
388
389 main_timer8: timer@2480000 {
390 compatible = "ti,am654-timer";
391 reg = <0x00 0x2480000 0x00 0x400>;
392 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&k3_clks 33 0>;
394 clock-names = "fck";
395 assigned-clocks = <&k3_clks 33 0>;
396 assigned-clock-parents = <&k3_clks 33 1>;
397 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
398 ti,timer-pwm;
399 };
400
401 main_timer9: timer@2490000 {
402 compatible = "ti,am654-timer";
403 reg = <0x00 0x2490000 0x00 0x400>;
404 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&k3_clks 34 0>;
406 clock-names = "fck";
407 assigned-clocks = <&k3_clks 34 0>;
408 assigned-clock-parents = <&k3_clks 34 1>;
409 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
410 ti,timer-pwm;
411 };
412
413 main_timer10: timer@24a0000 {
414 compatible = "ti,am654-timer";
415 reg = <0x00 0x24a0000 0x00 0x400>;
416 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&k3_clks 25 0>;
418 clock-names = "fck";
419 assigned-clocks = <&k3_clks 25 0>;
420 assigned-clock-parents = <&k3_clks 25 1>;
421 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
422 ti,timer-pwm;
423 };
424
425 main_timer11: timer@24b0000 {
426 compatible = "ti,am654-timer";
427 reg = <0x00 0x24b0000 0x00 0x400>;
428 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&k3_clks 26 0>;
430 clock-names = "fck";
431 assigned-clocks = <&k3_clks 26 0>;
432 assigned-clock-parents = <&k3_clks 26 1>;
433 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
434 ti,timer-pwm;
435 };
436
437 sdhci0: mmc@4f80000 {
438 compatible = "ti,am654-sdhci-5.1";
439 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
440 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
441 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
442 clock-names = "clk_ahb", "clk_xin";
443 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
444 mmc-ddr-1_8v;
445 mmc-hs200-1_8v;
446 ti,clkbuf-sel = <0x7>;
447 ti,trm-icp = <0x8>;
448 ti,otap-del-sel-legacy = <0x0>;
449 ti,otap-del-sel-mmc-hs = <0x0>;
450 ti,otap-del-sel-ddr52 = <0x5>;
451 ti,otap-del-sel-hs200 = <0x5>;
452 ti,itap-del-sel-ddr52 = <0x0>;
453 dma-coherent;
454 status = "disabled";
455 };
456
457 sdhci1: mmc@4fa0000 {
458 compatible = "ti,am654-sdhci-5.1";
459 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
460 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
461 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
462 clock-names = "clk_ahb", "clk_xin";
463 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
464 ti,clkbuf-sel = <0x7>;
465 ti,trm-icp = <0x8>;
466 ti,otap-del-sel-legacy = <0x0>;
467 ti,otap-del-sel-sd-hs = <0x0>;
468 ti,otap-del-sel-sdr12 = <0xf>;
469 ti,otap-del-sel-sdr25 = <0xf>;
470 ti,otap-del-sel-sdr50 = <0x8>;
471 ti,otap-del-sel-sdr104 = <0x7>;
472 ti,otap-del-sel-ddr50 = <0x4>;
473 ti,itap-del-sel-legacy = <0xa>;
474 ti,itap-del-sel-sd-hs = <0x1>;
475 ti,itap-del-sel-sdr12 = <0xa>;
476 ti,itap-del-sel-sdr25 = <0x1>;
477 dma-coherent;
478 status = "disabled";
479 };
480
481 scm_conf: scm-conf@100000 {
482 compatible = "syscon", "simple-mfd";
483 reg = <0 0x00100000 0 0x1c000>;
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges = <0x0 0x0 0x00100000 0x1c000>;
487
488 serdes0_clk: clock@4080 {
489 compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
490 reg = <0x4080 0x4>;
491
492 serdes0_mux: mux-controller {
493 compatible = "mmio-mux";
494 #mux-control-cells = <1>;
495 mux-reg-masks = <0x0 0x3>; /* lane select */
496 };
497 };
498
499 serdes1_clk: clock@4090 {
500 compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
501 reg = <0x4090 0x4>;
502
503 serdes1_mux: mux-controller {
504 compatible = "mmio-mux";
505 #mux-control-cells = <1>;
506 mux-reg-masks = <0x0 0x3>; /* lane select */
507 };
508 };
509
510 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
511 compatible = "ti,am654-dss-oldi-io-ctrl", "syscon";
512 reg = <0x41e0 0x14>;
513 };
514
515 ehrpwm_tbclk: clock-controller@4140 {
516 compatible = "ti,am654-ehrpwm-tbclk";
517 reg = <0x4140 0x18>;
518 #clock-cells = <1>;
519 };
520 };
521
522 dwc3_0: dwc3@4000000 {
523 compatible = "ti,am654-dwc3";
524 reg = <0x0 0x4000000 0x0 0x4000>;
525 #address-cells = <1>;
526 #size-cells = <1>;
527 ranges = <0x0 0x0 0x4000000 0x20000>;
528 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
529 dma-coherent;
530 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
531 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
532 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
533 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
534 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
535
536 usb0: usb@10000 {
537 compatible = "snps,dwc3";
538 reg = <0x10000 0x10000>;
539 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-names = "peripheral",
543 "host",
544 "otg";
545 maximum-speed = "high-speed";
546 dr_mode = "otg";
547 phys = <&usb0_phy>;
548 phy-names = "usb2-phy";
549 snps,dis_u3_susphy_quirk;
550 };
551 };
552
553 usb0_phy: phy@4100000 {
554 compatible = "ti,am654-usb2", "ti,omap-usb2";
555 reg = <0x0 0x4100000 0x0 0x54>;
556 syscon-phy-power = <&scm_conf 0x4000>;
557 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
558 clock-names = "wkupclk", "refclk";
559 #phy-cells = <0>;
560 };
561
562 dwc3_1: dwc3@4020000 {
563 compatible = "ti,am654-dwc3";
564 reg = <0x0 0x4020000 0x0 0x4000>;
565 #address-cells = <1>;
566 #size-cells = <1>;
567 ranges = <0x0 0x0 0x4020000 0x20000>;
568 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
569 dma-coherent;
570 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
571 clocks = <&k3_clks 152 2>;
572 assigned-clocks = <&k3_clks 152 2>;
573 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
574
575 usb1: usb@10000 {
576 compatible = "snps,dwc3";
577 reg = <0x10000 0x10000>;
578 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "peripheral",
582 "host",
583 "otg";
584 maximum-speed = "high-speed";
585 dr_mode = "otg";
586 phys = <&usb1_phy>;
587 phy-names = "usb2-phy";
588 };
589 };
590
591 usb1_phy: phy@4110000 {
592 compatible = "ti,am654-usb2", "ti,omap-usb2";
593 reg = <0x0 0x4110000 0x0 0x54>;
594 syscon-phy-power = <&scm_conf 0x4020>;
595 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
596 clock-names = "wkupclk", "refclk";
597 #phy-cells = <0>;
598 };
599
600 intr_main_gpio: interrupt-controller@a00000 {
601 compatible = "ti,sci-intr";
602 reg = <0x0 0x00a00000 0x0 0x400>;
603 ti,intr-trigger-type = <1>;
604 interrupt-controller;
605 interrupt-parent = <&gic500>;
606 #interrupt-cells = <1>;
607 ti,sci = <&dmsc>;
608 ti,sci-dev-id = <100>;
609 ti,interrupt-ranges = <0 392 32>;
610 };
611
612 main_navss: bus@30800000 {
613 compatible = "simple-bus";
614 #address-cells = <2>;
615 #size-cells = <2>;
616 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
617 dma-coherent;
618 dma-ranges;
619
620 ti,sci-dev-id = <118>;
621
622 intr_main_navss: interrupt-controller@310e0000 {
623 compatible = "ti,sci-intr";
624 reg = <0x0 0x310e0000 0x0 0x2000>;
625 ti,intr-trigger-type = <4>;
626 interrupt-controller;
627 interrupt-parent = <&gic500>;
628 #interrupt-cells = <1>;
629 ti,sci = <&dmsc>;
630 ti,sci-dev-id = <182>;
631 ti,interrupt-ranges = <0 64 64>,
632 <64 448 64>;
633 };
634
635 inta_main_udmass: interrupt-controller@33d00000 {
636 compatible = "ti,sci-inta";
637 reg = <0x0 0x33d00000 0x0 0x100000>;
638 interrupt-controller;
639 interrupt-parent = <&intr_main_navss>;
640 msi-controller;
641 #interrupt-cells = <0>;
642 ti,sci = <&dmsc>;
643 ti,sci-dev-id = <179>;
644 ti,interrupt-ranges = <0 0 256>;
645 };
646
647 secure_proxy_main: mailbox@32c00000 {
648 compatible = "ti,am654-secure-proxy";
649 #mbox-cells = <1>;
650 reg-names = "target_data", "rt", "scfg";
651 reg = <0x00 0x32c00000 0x00 0x100000>,
652 <0x00 0x32400000 0x00 0x100000>,
653 <0x00 0x32800000 0x00 0x100000>;
654 interrupt-names = "rx_011";
655 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
656 };
657
658 hwspinlock: spinlock@30e00000 {
659 compatible = "ti,am654-hwspinlock";
660 reg = <0x00 0x30e00000 0x00 0x1000>;
661 #hwlock-cells = <1>;
662 };
663
664 mailbox0_cluster0: mailbox@31f80000 {
665 compatible = "ti,am654-mailbox";
666 reg = <0x00 0x31f80000 0x00 0x200>;
667 #mbox-cells = <1>;
668 ti,mbox-num-users = <4>;
669 ti,mbox-num-fifos = <16>;
670 interrupt-parent = <&intr_main_navss>;
671 status = "disabled";
672 };
673
674 mailbox0_cluster1: mailbox@31f81000 {
675 compatible = "ti,am654-mailbox";
676 reg = <0x00 0x31f81000 0x00 0x200>;
677 #mbox-cells = <1>;
678 ti,mbox-num-users = <4>;
679 ti,mbox-num-fifos = <16>;
680 interrupt-parent = <&intr_main_navss>;
681 status = "disabled";
682 };
683
684 mailbox0_cluster2: mailbox@31f82000 {
685 compatible = "ti,am654-mailbox";
686 reg = <0x00 0x31f82000 0x00 0x200>;
687 #mbox-cells = <1>;
688 ti,mbox-num-users = <4>;
689 ti,mbox-num-fifos = <16>;
690 interrupt-parent = <&intr_main_navss>;
691 status = "disabled";
692 };
693
694 mailbox0_cluster3: mailbox@31f83000 {
695 compatible = "ti,am654-mailbox";
696 reg = <0x00 0x31f83000 0x00 0x200>;
697 #mbox-cells = <1>;
698 ti,mbox-num-users = <4>;
699 ti,mbox-num-fifos = <16>;
700 interrupt-parent = <&intr_main_navss>;
701 status = "disabled";
702 };
703
704 mailbox0_cluster4: mailbox@31f84000 {
705 compatible = "ti,am654-mailbox";
706 reg = <0x00 0x31f84000 0x00 0x200>;
707 #mbox-cells = <1>;
708 ti,mbox-num-users = <4>;
709 ti,mbox-num-fifos = <16>;
710 interrupt-parent = <&intr_main_navss>;
711 status = "disabled";
712 };
713
714 mailbox0_cluster5: mailbox@31f85000 {
715 compatible = "ti,am654-mailbox";
716 reg = <0x00 0x31f85000 0x00 0x200>;
717 #mbox-cells = <1>;
718 ti,mbox-num-users = <4>;
719 ti,mbox-num-fifos = <16>;
720 interrupt-parent = <&intr_main_navss>;
721 status = "disabled";
722 };
723
724 mailbox0_cluster6: mailbox@31f86000 {
725 compatible = "ti,am654-mailbox";
726 reg = <0x00 0x31f86000 0x00 0x200>;
727 #mbox-cells = <1>;
728 ti,mbox-num-users = <4>;
729 ti,mbox-num-fifos = <16>;
730 interrupt-parent = <&intr_main_navss>;
731 status = "disabled";
732 };
733
734 mailbox0_cluster7: mailbox@31f87000 {
735 compatible = "ti,am654-mailbox";
736 reg = <0x00 0x31f87000 0x00 0x200>;
737 #mbox-cells = <1>;
738 ti,mbox-num-users = <4>;
739 ti,mbox-num-fifos = <16>;
740 interrupt-parent = <&intr_main_navss>;
741 status = "disabled";
742 };
743
744 mailbox0_cluster8: mailbox@31f88000 {
745 compatible = "ti,am654-mailbox";
746 reg = <0x00 0x31f88000 0x00 0x200>;
747 #mbox-cells = <1>;
748 ti,mbox-num-users = <4>;
749 ti,mbox-num-fifos = <16>;
750 interrupt-parent = <&intr_main_navss>;
751 status = "disabled";
752 };
753
754 mailbox0_cluster9: mailbox@31f89000 {
755 compatible = "ti,am654-mailbox";
756 reg = <0x00 0x31f89000 0x00 0x200>;
757 #mbox-cells = <1>;
758 ti,mbox-num-users = <4>;
759 ti,mbox-num-fifos = <16>;
760 interrupt-parent = <&intr_main_navss>;
761 status = "disabled";
762 };
763
764 mailbox0_cluster10: mailbox@31f8a000 {
765 compatible = "ti,am654-mailbox";
766 reg = <0x00 0x31f8a000 0x00 0x200>;
767 #mbox-cells = <1>;
768 ti,mbox-num-users = <4>;
769 ti,mbox-num-fifos = <16>;
770 interrupt-parent = <&intr_main_navss>;
771 status = "disabled";
772 };
773
774 mailbox0_cluster11: mailbox@31f8b000 {
775 compatible = "ti,am654-mailbox";
776 reg = <0x00 0x31f8b000 0x00 0x200>;
777 #mbox-cells = <1>;
778 ti,mbox-num-users = <4>;
779 ti,mbox-num-fifos = <16>;
780 interrupt-parent = <&intr_main_navss>;
781 status = "disabled";
782 };
783
784 ringacc: ringacc@3c000000 {
785 compatible = "ti,am654-navss-ringacc";
786 reg = <0x0 0x3c000000 0x0 0x400000>,
787 <0x0 0x38000000 0x0 0x400000>,
788 <0x0 0x31120000 0x0 0x100>,
789 <0x0 0x33000000 0x0 0x40000>,
790 <0x0 0x31080000 0x0 0x40000>;
791 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
792 ti,num-rings = <818>;
793 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
794 ti,sci = <&dmsc>;
795 ti,sci-dev-id = <187>;
796 msi-parent = <&inta_main_udmass>;
797 };
798
799 main_udmap: dma-controller@31150000 {
800 compatible = "ti,am654-navss-main-udmap";
801 reg = <0x0 0x31150000 0x0 0x100>,
802 <0x0 0x34000000 0x0 0x100000>,
803 <0x0 0x35000000 0x0 0x100000>,
804 <0x0 0x30b00000 0x0 0x10000>,
805 <0x0 0x30c00000 0x0 0x10000>,
806 <0x0 0x30d00000 0x0 0x8000>;
807 reg-names = "gcfg", "rchanrt", "tchanrt",
808 "tchan", "rchan", "rflow";
809 msi-parent = <&inta_main_udmass>;
810 #dma-cells = <1>;
811
812 ti,sci = <&dmsc>;
813 ti,sci-dev-id = <188>;
814 ti,ringacc = <&ringacc>;
815
816 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
817 <0xd>; /* TX_CHAN */
818 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
819 <0xa>; /* RX_CHAN */
820 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
821 };
822
823 cpts@310d0000 {
824 compatible = "ti,am65-cpts";
825 reg = <0x0 0x310d0000 0x0 0x400>;
826 reg-names = "cpts";
827 clocks = <&main_cpts_mux>;
828 clock-names = "cpts";
829 interrupts-extended = <&intr_main_navss 391>;
830 interrupt-names = "cpts";
831 ti,cpts-periodic-outputs = <6>;
832 ti,cpts-ext-ts-inputs = <8>;
833
834 main_cpts_mux: refclk-mux {
835 #clock-cells = <0>;
836 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
837 <&k3_clks 118 6>, <&k3_clks 118 3>,
838 <&k3_clks 118 8>, <&k3_clks 118 14>,
839 <&k3_clks 120 3>, <&k3_clks 121 3>;
840 assigned-clocks = <&main_cpts_mux>;
841 assigned-clock-parents = <&k3_clks 118 5>;
842 };
843 };
844 };
845
846 main_gpio0: gpio@600000 {
847 compatible = "ti,am654-gpio", "ti,keystone-gpio";
848 reg = <0x0 0x600000 0x0 0x100>;
849 gpio-controller;
850 #gpio-cells = <2>;
851 interrupt-parent = <&intr_main_gpio>;
852 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
853 interrupt-controller;
854 #interrupt-cells = <2>;
855 ti,ngpio = <96>;
856 ti,davinci-gpio-unbanked = <0>;
857 clocks = <&k3_clks 57 0>;
858 clock-names = "gpio";
859 };
860
861 main_gpio1: gpio@601000 {
862 compatible = "ti,am654-gpio", "ti,keystone-gpio";
863 reg = <0x0 0x601000 0x0 0x100>;
864 gpio-controller;
865 #gpio-cells = <2>;
866 interrupt-parent = <&intr_main_gpio>;
867 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
868 interrupt-controller;
869 #interrupt-cells = <2>;
870 ti,ngpio = <90>;
871 ti,davinci-gpio-unbanked = <0>;
872 clocks = <&k3_clks 58 0>;
873 clock-names = "gpio";
874 };
875
876 pcie0_rc: pcie@5500000 {
877 compatible = "ti,am654-pcie-rc";
878 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
879 reg-names = "app", "dbics", "config", "atu";
880 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
881 #address-cells = <3>;
882 #size-cells = <2>;
883 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
884 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
885 ti,syscon-pcie-id = <&scm_conf 0x210>;
886 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
887 bus-range = <0x0 0xff>;
888 num-viewport = <16>;
889 max-link-speed = <2>;
890 dma-coherent;
891 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
892 msi-map = <0x0 &gic_its 0x0 0x10000>;
893 device_type = "pci";
894 status = "disabled";
895 };
896
897 pcie1_rc: pcie@5600000 {
898 compatible = "ti,am654-pcie-rc";
899 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
900 reg-names = "app", "dbics", "config", "atu";
901 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
902 #address-cells = <3>;
903 #size-cells = <2>;
904 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
905 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
906 ti,syscon-pcie-id = <&scm_conf 0x210>;
907 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
908 bus-range = <0x0 0xff>;
909 num-viewport = <16>;
910 max-link-speed = <2>;
911 dma-coherent;
912 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
913 msi-map = <0x0 &gic_its 0x10000 0x10000>;
914 device_type = "pci";
915 status = "disabled";
916 };
917
918 mcasp0: mcasp@2b00000 {
919 compatible = "ti,am33xx-mcasp-audio";
920 reg = <0x0 0x02b00000 0x0 0x2000>,
921 <0x0 0x02b08000 0x0 0x1000>;
922 reg-names = "mpu","dat";
923 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
925 interrupt-names = "tx", "rx";
926
927 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
928 dma-names = "tx", "rx";
929
930 clocks = <&k3_clks 104 0>;
931 clock-names = "fck";
932 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
933 status = "disabled";
934 };
935
936 mcasp1: mcasp@2b10000 {
937 compatible = "ti,am33xx-mcasp-audio";
938 reg = <0x0 0x02b10000 0x0 0x2000>,
939 <0x0 0x02b18000 0x0 0x1000>;
940 reg-names = "mpu","dat";
941 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
943 interrupt-names = "tx", "rx";
944
945 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
946 dma-names = "tx", "rx";
947
948 clocks = <&k3_clks 105 0>;
949 clock-names = "fck";
950 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
951 status = "disabled";
952 };
953
954 mcasp2: mcasp@2b20000 {
955 compatible = "ti,am33xx-mcasp-audio";
956 reg = <0x0 0x02b20000 0x0 0x2000>,
957 <0x0 0x02b28000 0x0 0x1000>;
958 reg-names = "mpu","dat";
959 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
961 interrupt-names = "tx", "rx";
962
963 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
964 dma-names = "tx", "rx";
965
966 clocks = <&k3_clks 106 0>;
967 clock-names = "fck";
968 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
969 status = "disabled";
970 };
971
972 cal: cal@6f03000 {
973 compatible = "ti,am654-cal";
974 reg = <0x0 0x06f03000 0x0 0x400>,
975 <0x0 0x06f03800 0x0 0x40>;
976 reg-names = "cal_top",
977 "cal_rx_core0";
978 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
979 ti,camerrx-control = <&scm_conf 0x40c0>;
980 clock-names = "fck";
981 clocks = <&k3_clks 2 0>;
982 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
983
984 ports {
985 #address-cells = <1>;
986 #size-cells = <0>;
987
988 csi2_0: port@0 {
989 reg = <0>;
990 };
991 };
992 };
993
994 dss: dss@4a00000 {
995 compatible = "ti,am65x-dss";
996 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
997 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
998 <0x0 0x04a06000 0x0 0x1000>, /* vid */
999 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
1000 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
1001 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
1002 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */
1003 <0x0 0x04a01000 0x0 0x1000>; /* common1 */
1004 reg-names = "common", "vidl1", "vid",
1005 "ovr1", "ovr2", "vp1", "vp2", "common1";
1006
1007 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
1008
1009 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1010
1011 clocks = <&k3_clks 67 1>,
1012 <&k3_clks 216 1>,
1013 <&k3_clks 67 2>;
1014 clock-names = "fck", "vp1", "vp2";
1015
1016 /*
1017 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
1018 * DIV1. See "Figure 12-3365. DSS Integration"
1019 * in AM65x TRM for details.
1020 */
1021 assigned-clocks = <&k3_clks 67 2>;
1022 assigned-clock-parents = <&k3_clks 67 5>;
1023
1024 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1025
1026 dma-coherent;
1027
1028 dss_ports: ports {
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 };
1032 };
1033
1034 gpu: gpu@7000000 {
1035 compatible = "ti,am6548-gpu", "img,powervr-sgx544";
1036 reg = <0x0 0x7000000 0x0 0x10000>;
1037 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1038 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1039 };
1040
1041 ehrpwm0: pwm@3000000 {
1042 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1043 #pwm-cells = <3>;
1044 reg = <0x0 0x3000000 0x0 0x100>;
1045 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
1046 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1047 clock-names = "tbclk", "fck";
1048 status = "disabled";
1049 };
1050
1051 ehrpwm1: pwm@3010000 {
1052 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1053 #pwm-cells = <3>;
1054 reg = <0x0 0x3010000 0x0 0x100>;
1055 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
1056 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1057 clock-names = "tbclk", "fck";
1058 status = "disabled";
1059 };
1060
1061 ehrpwm2: pwm@3020000 {
1062 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1063 #pwm-cells = <3>;
1064 reg = <0x0 0x3020000 0x0 0x100>;
1065 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
1066 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1067 clock-names = "tbclk", "fck";
1068 status = "disabled";
1069 };
1070
1071 ehrpwm3: pwm@3030000 {
1072 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1073 #pwm-cells = <3>;
1074 reg = <0x0 0x3030000 0x0 0x100>;
1075 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
1076 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1077 clock-names = "tbclk", "fck";
1078 status = "disabled";
1079 };
1080
1081 ehrpwm4: pwm@3040000 {
1082 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1083 #pwm-cells = <3>;
1084 reg = <0x0 0x3040000 0x0 0x100>;
1085 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
1086 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1087 clock-names = "tbclk", "fck";
1088 status = "disabled";
1089 };
1090
1091 ehrpwm5: pwm@3050000 {
1092 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1093 #pwm-cells = <3>;
1094 reg = <0x0 0x3050000 0x0 0x100>;
1095 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
1096 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1097 clock-names = "tbclk", "fck";
1098 status = "disabled";
1099 };
1100
1101 icssg0: icssg@b000000 {
1102 compatible = "ti,am654-icssg";
1103 reg = <0x00 0xb000000 0x00 0x80000>;
1104 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1105 #address-cells = <1>;
1106 #size-cells = <1>;
1107 ranges = <0x0 0x00 0xb000000 0x80000>;
1108
1109 icssg0_mem: memories@0 {
1110 reg = <0x0 0x2000>,
1111 <0x2000 0x2000>,
1112 <0x10000 0x10000>;
1113 reg-names = "dram0", "dram1",
1114 "shrdram2";
1115 };
1116
1117 icssg0_cfg: cfg@26000 {
1118 compatible = "ti,pruss-cfg", "syscon";
1119 reg = <0x26000 0x200>;
1120 #address-cells = <1>;
1121 #size-cells = <1>;
1122 ranges = <0x0 0x26000 0x2000>;
1123
1124 clocks {
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127
1128 icssg0_coreclk_mux: coreclk-mux@3c {
1129 reg = <0x3c>;
1130 #clock-cells = <0>;
1131 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
1132 <&k3_clks 62 3>; /* icssg0_iclk */
1133 assigned-clocks = <&icssg0_coreclk_mux>;
1134 assigned-clock-parents = <&k3_clks 62 3>;
1135 };
1136
1137 icssg0_iepclk_mux: iepclk-mux@30 {
1138 reg = <0x30>;
1139 #clock-cells = <0>;
1140 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
1141 <&icssg0_coreclk_mux>; /* core_clk */
1142 assigned-clocks = <&icssg0_iepclk_mux>;
1143 assigned-clock-parents = <&icssg0_coreclk_mux>;
1144 };
1145 };
1146 };
1147
1148 icssg0_iep0: iep@2e000 {
1149 compatible = "ti,am654-icss-iep";
1150 reg = <0x2e000 0x1000>;
1151 clocks = <&icssg0_iepclk_mux>;
1152 };
1153
1154 icssg0_iep1: iep@2f000 {
1155 compatible = "ti,am654-icss-iep";
1156 reg = <0x2f000 0x1000>;
1157 clocks = <&icssg0_iepclk_mux>;
1158 };
1159
1160 icssg0_mii_rt: mii-rt@32000 {
1161 compatible = "ti,pruss-mii", "syscon";
1162 reg = <0x32000 0x100>;
1163 };
1164
1165 icssg0_mii_g_rt: mii-g-rt@33000 {
1166 compatible = "ti,pruss-mii-g", "syscon";
1167 reg = <0x33000 0x1000>;
1168 };
1169
1170 icssg0_intc: interrupt-controller@20000 {
1171 compatible = "ti,icssg-intc";
1172 reg = <0x20000 0x2000>;
1173 interrupt-controller;
1174 #interrupt-cells = <3>;
1175 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1178 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1183 interrupt-names = "host_intr0", "host_intr1",
1184 "host_intr2", "host_intr3",
1185 "host_intr4", "host_intr5",
1186 "host_intr6", "host_intr7";
1187 };
1188
1189 pru0_0: pru@34000 {
1190 compatible = "ti,am654-pru";
1191 reg = <0x34000 0x4000>,
1192 <0x22000 0x100>,
1193 <0x22400 0x100>;
1194 reg-names = "iram", "control", "debug";
1195 firmware-name = "am65x-pru0_0-fw";
1196 interrupt-parent = <&icssg0_intc>;
1197 interrupts = <16 2 2>;
1198 interrupt-names = "vring";
1199 };
1200
1201 rtu0_0: rtu@4000 {
1202 compatible = "ti,am654-rtu";
1203 reg = <0x4000 0x2000>,
1204 <0x23000 0x100>,
1205 <0x23400 0x100>;
1206 reg-names = "iram", "control", "debug";
1207 firmware-name = "am65x-rtu0_0-fw";
1208 interrupt-parent = <&icssg0_intc>;
1209 interrupts = <20 4 4>;
1210 interrupt-names = "vring";
1211 };
1212
1213 tx_pru0_0: txpru@a000 {
1214 compatible = "ti,am654-tx-pru";
1215 reg = <0xa000 0x1800>,
1216 <0x25000 0x100>,
1217 <0x25400 0x100>;
1218 reg-names = "iram", "control", "debug";
1219 firmware-name = "am65x-txpru0_0-fw";
1220 };
1221
1222 pru0_1: pru@38000 {
1223 compatible = "ti,am654-pru";
1224 reg = <0x38000 0x4000>,
1225 <0x24000 0x100>,
1226 <0x24400 0x100>;
1227 reg-names = "iram", "control", "debug";
1228 firmware-name = "am65x-pru0_1-fw";
1229 interrupt-parent = <&icssg0_intc>;
1230 interrupts = <18 3 3>;
1231 interrupt-names = "vring";
1232 };
1233
1234 rtu0_1: rtu@6000 {
1235 compatible = "ti,am654-rtu";
1236 reg = <0x6000 0x2000>,
1237 <0x23800 0x100>,
1238 <0x23c00 0x100>;
1239 reg-names = "iram", "control", "debug";
1240 firmware-name = "am65x-rtu0_1-fw";
1241 interrupt-parent = <&icssg0_intc>;
1242 interrupts = <22 5 5>;
1243 interrupt-names = "vring";
1244 };
1245
1246 tx_pru0_1: txpru@c000 {
1247 compatible = "ti,am654-tx-pru";
1248 reg = <0xc000 0x1800>,
1249 <0x25800 0x100>,
1250 <0x25c00 0x100>;
1251 reg-names = "iram", "control", "debug";
1252 firmware-name = "am65x-txpru0_1-fw";
1253 };
1254
1255 icssg0_mdio: mdio@32400 {
1256 compatible = "ti,davinci_mdio";
1257 reg = <0x32400 0x100>;
1258 clocks = <&k3_clks 62 3>;
1259 clock-names = "fck";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1262 bus_freq = <1000000>;
1263 status = "disabled";
1264 };
1265 };
1266
1267 icssg1: icssg@b100000 {
1268 compatible = "ti,am654-icssg";
1269 reg = <0x00 0xb100000 0x00 0x80000>;
1270 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1273 ranges = <0x0 0x00 0xb100000 0x80000>;
1274
1275 icssg1_mem: memories@0 {
1276 reg = <0x0 0x2000>,
1277 <0x2000 0x2000>,
1278 <0x10000 0x10000>;
1279 reg-names = "dram0", "dram1",
1280 "shrdram2";
1281 };
1282
1283 icssg1_cfg: cfg@26000 {
1284 compatible = "ti,pruss-cfg", "syscon";
1285 reg = <0x26000 0x200>;
1286 #address-cells = <1>;
1287 #size-cells = <1>;
1288 ranges = <0x0 0x26000 0x2000>;
1289
1290 clocks {
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1293
1294 icssg1_coreclk_mux: coreclk-mux@3c {
1295 reg = <0x3c>;
1296 #clock-cells = <0>;
1297 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
1298 <&k3_clks 63 3>; /* icssg1_iclk */
1299 assigned-clocks = <&icssg1_coreclk_mux>;
1300 assigned-clock-parents = <&k3_clks 63 3>;
1301 };
1302
1303 icssg1_iepclk_mux: iepclk-mux@30 {
1304 reg = <0x30>;
1305 #clock-cells = <0>;
1306 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
1307 <&icssg1_coreclk_mux>; /* core_clk */
1308 assigned-clocks = <&icssg1_iepclk_mux>;
1309 assigned-clock-parents = <&icssg1_coreclk_mux>;
1310 };
1311 };
1312 };
1313
1314 icssg1_iep0: iep@2e000 {
1315 compatible = "ti,am654-icss-iep";
1316 reg = <0x2e000 0x1000>;
1317 clocks = <&icssg1_iepclk_mux>;
1318 };
1319
1320 icssg1_iep1: iep@2f000 {
1321 compatible = "ti,am654-icss-iep";
1322 reg = <0x2f000 0x1000>;
1323 clocks = <&icssg1_iepclk_mux>;
1324 };
1325
1326 icssg1_mii_rt: mii-rt@32000 {
1327 compatible = "ti,pruss-mii", "syscon";
1328 reg = <0x32000 0x100>;
1329 };
1330
1331 icssg1_mii_g_rt: mii-g-rt@33000 {
1332 compatible = "ti,pruss-mii-g", "syscon";
1333 reg = <0x33000 0x1000>;
1334 };
1335
1336 icssg1_intc: interrupt-controller@20000 {
1337 compatible = "ti,icssg-intc";
1338 reg = <0x20000 0x2000>;
1339 interrupt-controller;
1340 #interrupt-cells = <3>;
1341 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1349 interrupt-names = "host_intr0", "host_intr1",
1350 "host_intr2", "host_intr3",
1351 "host_intr4", "host_intr5",
1352 "host_intr6", "host_intr7";
1353 };
1354
1355 pru1_0: pru@34000 {
1356 compatible = "ti,am654-pru";
1357 reg = <0x34000 0x4000>,
1358 <0x22000 0x100>,
1359 <0x22400 0x100>;
1360 reg-names = "iram", "control", "debug";
1361 firmware-name = "am65x-pru1_0-fw";
1362 interrupt-parent = <&icssg1_intc>;
1363 interrupts = <16 2 2>;
1364 interrupt-names = "vring";
1365 };
1366
1367 rtu1_0: rtu@4000 {
1368 compatible = "ti,am654-rtu";
1369 reg = <0x4000 0x2000>,
1370 <0x23000 0x100>,
1371 <0x23400 0x100>;
1372 reg-names = "iram", "control", "debug";
1373 firmware-name = "am65x-rtu1_0-fw";
1374 interrupt-parent = <&icssg1_intc>;
1375 interrupts = <20 4 4>;
1376 interrupt-names = "vring";
1377 };
1378
1379 tx_pru1_0: txpru@a000 {
1380 compatible = "ti,am654-tx-pru";
1381 reg = <0xa000 0x1800>,
1382 <0x25000 0x100>,
1383 <0x25400 0x100>;
1384 reg-names = "iram", "control", "debug";
1385 firmware-name = "am65x-txpru1_0-fw";
1386 };
1387
1388 pru1_1: pru@38000 {
1389 compatible = "ti,am654-pru";
1390 reg = <0x38000 0x4000>,
1391 <0x24000 0x100>,
1392 <0x24400 0x100>;
1393 reg-names = "iram", "control", "debug";
1394 firmware-name = "am65x-pru1_1-fw";
1395 interrupt-parent = <&icssg1_intc>;
1396 interrupts = <18 3 3>;
1397 interrupt-names = "vring";
1398 };
1399
1400 rtu1_1: rtu@6000 {
1401 compatible = "ti,am654-rtu";
1402 reg = <0x6000 0x2000>,
1403 <0x23800 0x100>,
1404 <0x23c00 0x100>;
1405 reg-names = "iram", "control", "debug";
1406 firmware-name = "am65x-rtu1_1-fw";
1407 interrupt-parent = <&icssg1_intc>;
1408 interrupts = <22 5 5>;
1409 interrupt-names = "vring";
1410 };
1411
1412 tx_pru1_1: txpru@c000 {
1413 compatible = "ti,am654-tx-pru";
1414 reg = <0xc000 0x1800>,
1415 <0x25800 0x100>,
1416 <0x25c00 0x100>;
1417 reg-names = "iram", "control", "debug";
1418 firmware-name = "am65x-txpru1_1-fw";
1419 };
1420
1421 icssg1_mdio: mdio@32400 {
1422 compatible = "ti,davinci_mdio";
1423 reg = <0x32400 0x100>;
1424 clocks = <&k3_clks 63 3>;
1425 clock-names = "fck";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428 bus_freq = <1000000>;
1429 status = "disabled";
1430 };
1431 };
1432
1433 icssg2: icssg@b200000 {
1434 compatible = "ti,am654-icssg";
1435 reg = <0x00 0xb200000 0x00 0x80000>;
1436 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1437 #address-cells = <1>;
1438 #size-cells = <1>;
1439 ranges = <0x0 0x00 0xb200000 0x80000>;
1440
1441 icssg2_mem: memories@0 {
1442 reg = <0x0 0x2000>,
1443 <0x2000 0x2000>,
1444 <0x10000 0x10000>;
1445 reg-names = "dram0", "dram1",
1446 "shrdram2";
1447 };
1448
1449 icssg2_cfg: cfg@26000 {
1450 compatible = "ti,pruss-cfg", "syscon";
1451 reg = <0x26000 0x200>;
1452 #address-cells = <1>;
1453 #size-cells = <1>;
1454 ranges = <0x0 0x26000 0x2000>;
1455
1456 clocks {
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1459
1460 icssg2_coreclk_mux: coreclk-mux@3c {
1461 reg = <0x3c>;
1462 #clock-cells = <0>;
1463 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
1464 <&k3_clks 64 3>; /* icssg1_iclk */
1465 assigned-clocks = <&icssg2_coreclk_mux>;
1466 assigned-clock-parents = <&k3_clks 64 3>;
1467 };
1468
1469 icssg2_iepclk_mux: iepclk-mux@30 {
1470 reg = <0x30>;
1471 #clock-cells = <0>;
1472 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
1473 <&icssg2_coreclk_mux>; /* core_clk */
1474 assigned-clocks = <&icssg2_iepclk_mux>;
1475 assigned-clock-parents = <&icssg2_coreclk_mux>;
1476 };
1477 };
1478 };
1479
1480 icssg2_iep0: iep@2e000 {
1481 compatible = "ti,am654-icss-iep";
1482 reg = <0x2e000 0x1000>;
1483 clocks = <&icssg2_iepclk_mux>;
1484 };
1485
1486 icssg2_iep1: iep@2f000 {
1487 compatible = "ti,am654-icss-iep";
1488 reg = <0x2f000 0x1000>;
1489 clocks = <&icssg2_iepclk_mux>;
1490 };
1491
1492 icssg2_mii_rt: mii-rt@32000 {
1493 compatible = "ti,pruss-mii", "syscon";
1494 reg = <0x32000 0x100>;
1495 };
1496
1497 icssg2_mii_g_rt: mii-g-rt@33000 {
1498 compatible = "ti,pruss-mii-g", "syscon";
1499 reg = <0x33000 0x1000>;
1500 };
1501
1502 icssg2_intc: interrupt-controller@20000 {
1503 compatible = "ti,icssg-intc";
1504 reg = <0x20000 0x2000>;
1505 interrupt-controller;
1506 #interrupt-cells = <3>;
1507 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
1508 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
1509 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
1515 interrupt-names = "host_intr0", "host_intr1",
1516 "host_intr2", "host_intr3",
1517 "host_intr4", "host_intr5",
1518 "host_intr6", "host_intr7";
1519 };
1520
1521 pru2_0: pru@34000 {
1522 compatible = "ti,am654-pru";
1523 reg = <0x34000 0x4000>,
1524 <0x22000 0x100>,
1525 <0x22400 0x100>;
1526 reg-names = "iram", "control", "debug";
1527 firmware-name = "am65x-pru2_0-fw";
1528 interrupt-parent = <&icssg2_intc>;
1529 interrupts = <16 2 2>;
1530 interrupt-names = "vring";
1531 };
1532
1533 rtu2_0: rtu@4000 {
1534 compatible = "ti,am654-rtu";
1535 reg = <0x4000 0x2000>,
1536 <0x23000 0x100>,
1537 <0x23400 0x100>;
1538 reg-names = "iram", "control", "debug";
1539 firmware-name = "am65x-rtu2_0-fw";
1540 interrupt-parent = <&icssg2_intc>;
1541 interrupts = <20 4 4>;
1542 interrupt-names = "vring";
1543 };
1544
1545 tx_pru2_0: txpru@a000 {
1546 compatible = "ti,am654-tx-pru";
1547 reg = <0xa000 0x1800>,
1548 <0x25000 0x100>,
1549 <0x25400 0x100>;
1550 reg-names = "iram", "control", "debug";
1551 firmware-name = "am65x-txpru2_0-fw";
1552 };
1553
1554 pru2_1: pru@38000 {
1555 compatible = "ti,am654-pru";
1556 reg = <0x38000 0x4000>,
1557 <0x24000 0x100>,
1558 <0x24400 0x100>;
1559 reg-names = "iram", "control", "debug";
1560 firmware-name = "am65x-pru2_1-fw";
1561 interrupt-parent = <&icssg2_intc>;
1562 interrupts = <18 3 3>;
1563 interrupt-names = "vring";
1564 };
1565
1566 rtu2_1: rtu@6000 {
1567 compatible = "ti,am654-rtu";
1568 reg = <0x6000 0x2000>,
1569 <0x23800 0x100>,
1570 <0x23c00 0x100>;
1571 reg-names = "iram", "control", "debug";
1572 firmware-name = "am65x-rtu2_1-fw";
1573 interrupt-parent = <&icssg2_intc>;
1574 interrupts = <22 5 5>;
1575 interrupt-names = "vring";
1576 };
1577
1578 tx_pru2_1: txpru@c000 {
1579 compatible = "ti,am654-tx-pru";
1580 reg = <0xc000 0x1800>,
1581 <0x25800 0x100>,
1582 <0x25c00 0x100>;
1583 reg-names = "iram", "control", "debug";
1584 firmware-name = "am65x-txpru2_1-fw";
1585 };
1586
1587 icssg2_mdio: mdio@32400 {
1588 compatible = "ti,davinci_mdio";
1589 reg = <0x32400 0x100>;
1590 clocks = <&k3_clks 64 3>;
1591 clock-names = "fck";
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1594 bus_freq = <1000000>;
1595 status = "disabled";
1596 };
1597 };
1598 };
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