1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Base Board: https://www.ti.com/lit/zip/SPRR463
6 */
7
8 /dts-v1/;
9
10 #include "k3-am68-sk-som.dtsi"
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-cadence.h>
13 #include <dt-bindings/phy/phy.h>
14
15 #include "k3-serdes.h"
16
17 / {
18 compatible = "ti,am68-sk", "ti,j721s2";
19 model = "Texas Instruments AM68 SK";
20
21 chosen {
22 stdout-path = "serial2:115200n8";
23 };
24
25 aliases {
26 serial0 = &wkup_uart0;
27 serial1 = &mcu_uart0;
28 serial2 = &main_uart8;
29 mmc1 = &main_sdhci1;
30 can0 = &mcu_mcan0;
31 can1 = &mcu_mcan1;
32 can2 = &main_mcan6;
33 can3 = &main_mcan7;
34 ethernet0 = &cpsw_port1;
35 };
36
37 vusb_main: regulator-vusb-main5v0 {
38 /* USB MAIN INPUT 5V DC */
39 compatible = "regulator-fixed";
40 regulator-name = "vusb-main5v0";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 regulator-always-on;
44 regulator-boot-on;
45 };
46
47 vsys_3v3: regulator-vsys3v3 {
48 /* Output of LM5141 */
49 compatible = "regulator-fixed";
50 regulator-name = "vsys_3v3";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 vin-supply = <&vusb_main>;
54 regulator-always-on;
55 regulator-boot-on;
56 };
57
58 vdd_mmc1: regulator-sd {
59 /* Output of TPS22918 */
60 compatible = "regulator-fixed";
61 regulator-name = "vdd_mmc1";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 regulator-boot-on;
65 enable-active-high;
66 vin-supply = <&vsys_3v3>;
67 gpio = <&exp1 8 GPIO_ACTIVE_HIGH>;
68 };
69
70 vdd_sd_dv: regulator-tlv71033 {
71 /* Output of TLV71033 */
72 compatible = "regulator-gpio";
73 regulator-name = "tlv71033";
74 pinctrl-names = "default";
75 pinctrl-0 = <&vdd_sd_dv_pins_default>;
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-boot-on;
79 vin-supply = <&vsys_3v3>;
80 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
81 states = <1800000 0x0>,
82 <3300000 0x1>;
83 };
84
85 vsys_io_1v8: regulator-vsys-io-1v8 {
86 compatible = "regulator-fixed";
87 regulator-name = "vsys_io_1v8";
88 regulator-min-microvolt = <1800000>;
89 regulator-max-microvolt = <1800000>;
90 regulator-always-on;
91 regulator-boot-on;
92 };
93
94 vsys_io_1v2: regulator-vsys-io-1v2 {
95 compatible = "regulator-fixed";
96 regulator-name = "vsys_io_1v2";
97 regulator-min-microvolt = <1200000>;
98 regulator-max-microvolt = <1200000>;
99 regulator-always-on;
100 regulator-boot-on;
101 };
102
103 transceiver1: can-phy0 {
104 compatible = "ti,tcan1042";
105 #phy-cells = <0>;
106 max-bitrate = <5000000>;
107 };
108
109 transceiver2: can-phy1 {
110 compatible = "ti,tcan1042";
111 #phy-cells = <0>;
112 max-bitrate = <5000000>;
113 };
114
115 transceiver3: can-phy2 {
116 compatible = "ti,tcan1042";
117 #phy-cells = <0>;
118 max-bitrate = <5000000>;
119 };
120
121 transceiver4: can-phy3 {
122 compatible = "ti,tcan1042";
123 #phy-cells = <0>;
124 max-bitrate = <5000000>;
125 };
126
127 connector-hdmi {
128 compatible = "hdmi-connector";
129 label = "hdmi";
130 type = "a";
131 pinctrl-names = "default";
132 pinctrl-0 = <&hdmi_hpd_pins_default>;
133 ddc-i2c-bus = <&mcu_i2c1>;
134 /* HDMI_HPD */
135 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
136
137 port {
138 hdmi_connector_in: endpoint {
139 remote-endpoint = <&tfp410_out>;
140 };
141 };
142 };
143
144 bridge-dvi {
145 compatible = "ti,tfp410";
146 /* HDMI_PDn */
147 powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
148 ti,deskew = <0>;
149
150 ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 port@0 {
155 reg = <0>;
156
157 tfp410_in: endpoint {
158 remote-endpoint = <&dpi_out0>;
159 pclk-sample = <1>;
160 };
161 };
162
163 port@1 {
164 reg = <1>;
165
166 tfp410_out: endpoint {
167 remote-endpoint = <&hdmi_connector_in>;
168 };
169 };
170 };
171 };
172
173 csi_mux: mux-controller {
174 compatible = "gpio-mux";
175 #mux-state-cells = <1>;
176 mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>;
177 idle-state = <0>;
178 };
179 };
180
181 &main_pmx0 {
182 main_uart8_pins_default: main-uart8-default-pins {
183 pinctrl-single,pins = <
184 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
185 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
186 >;
187 };
188
189 main_i2c0_pins_default: main-i2c0-default-pins {
190 pinctrl-single,pins = <
191 J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
192 J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
193 >;
194 };
195
196 main_i2c1_pins_default: main-i2c1-default-pins {
197 pinctrl-single,pins = <
198 J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */
199 J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */
200 >;
201 };
202
203 main_mmc1_pins_default: main-mmc1-default-pins {
204 pinctrl-single,pins = <
205 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
206 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
207 J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
208 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
209 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
210 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
211 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
212 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
213 >;
214 };
215
216 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
217 pinctrl-single,pins = <
218 J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
219 >;
220 };
221
222 main_usbss0_pins_default: main-usbss0-default-pins {
223 pinctrl-single,pins = <
224 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
225 >;
226 };
227
228 main_mcan6_pins_default: main-mcan6-default-pins {
229 pinctrl-single,pins = <
230 J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
231 J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
232 >;
233 };
234
235 main_mcan7_pins_default: main-mcan7-default-pins {
236 pinctrl-single,pins = <
237 J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
238 J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
239 >;
240 };
241
242 main_i2c4_pins_default: main-i2c4-default-pins {
243 pinctrl-single,pins = <
244 J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
245 J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
246 >;
247 };
248
249 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
250 pinctrl-single,pins = <
251 J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
252 J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
253 J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
254 J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
255 J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
256 J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
257 J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
258 J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
259 J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
260 J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
261 J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
262 J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
263 J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
264 J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
265 >;
266 };
267
268 dss_vout0_pins_default: dss-vout0-default-pins {
269 pinctrl-single,pins = <
270 J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */
271 J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */
272 J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */
273 J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */
274 J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */
275 J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */
276 J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */
277 J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */
278 J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */
279 J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */
280 J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */
281 J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */
282 J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */
283 J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */
284 J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */
285 J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */
286 J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */
287 J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */
288 J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */
289 J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */
290 J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */
291 J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */
292 J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */
293 J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */
294 J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */
295 J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */
296 J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */
297 J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */
298 >;
299 };
300
301 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
302 pinctrl-single,pins = <
303 J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */
304 >;
305 };
306 };
307
308 &wkup_pmx2 {
309 wkup_uart0_pins_default: wkup-uart0-default-pins {
310 pinctrl-single,pins = <
311 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
312 J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
313 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
314 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
315 >;
316 };
317
318 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
319 pinctrl-single,pins = <
320 J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
321 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
322 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
323 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
324 J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
325 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
326 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
327 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
328 J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
329 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
330 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
331 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
332 >;
333 };
334
335 mcu_mdio_pins_default: mcu-mdio-default-pins {
336 pinctrl-single,pins = <
337 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
338 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
339 >;
340 };
341
342 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
343 pinctrl-single,pins = <
344 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
345 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
346 >;
347 };
348
349 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
350 pinctrl-single,pins = <
351 J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
352 J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
353 >;
354 };
355
356 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
357 pinctrl-single,pins = <
358 J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
359 J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
360 >;
361 };
362
363 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
364 pinctrl-single,pins = <
365 J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
366 J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
367 >;
368 };
369
370 mcu_uart0_pins_default: mcu-uart0-default-pins {
371 pinctrl-single,pins = <
372 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
373 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
374 >;
375 };
376
377 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
378 pinctrl-single,pins = <
379 J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
380 J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
381 J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
382 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
383 J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
384 J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
385 J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
386 J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
387 J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
388 >;
389 };
390 };
391
392 &wkup_pmx3 {
393 mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 {
394 pinctrl-single,pins = <
395 J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
396 >;
397 };
398 };
399
400 &main_gpio0 {
401 status = "okay";
402 pinctrl-names = "default";
403 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
404 };
405
406 &wkup_gpio0 {
407 status = "okay";
408 pinctrl-names = "default";
409 pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
410 };
411
412 &wkup_uart0 {
413 status = "reserved";
414 pinctrl-names = "default";
415 pinctrl-0 = <&wkup_uart0_pins_default>;
416 };
417
418 &wkup_i2c0 {
419 bootph-all;
420 clock-frequency = <400000>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&wkup_i2c0_pins_default>;
423 status = "okay";
424
425 lp8733: pmic@60 {
426 compatible = "ti,lp8733";
427 reg = <0x60>;
428 buck0-in-supply = <&vsys_3v3>;
429 buck1-in-supply = <&vsys_3v3>;
430 ldo0-in-supply = <&vsys_3v3>;
431 ldo1-in-supply = <&vsys_3v3>;
432
433 lp8733_regulators: regulators {
434 lp8733_buck0_reg: buck0 {
435 /* FB_B0 -> LP8733-BUCK1 - VDD_MCU_0V85 */
436 regulator-name = "lp8733-buck0";
437 regulator-min-microvolt = <850000>;
438 regulator-max-microvolt = <850000>;
439 regulator-always-on;
440 regulator-boot-on;
441 };
442
443 lp8733_buck1_reg: buck1 {
444 /* FB_B1 -> LP8733-BUCK2 - VDD_DDR_1V1 */
445 regulator-name = "lp8733-buck1";
446 regulator-min-microvolt = <1100000>;
447 regulator-max-microvolt = <1100000>;
448 regulator-always-on;
449 regulator-boot-on;
450 };
451
452 lp8733_ldo0_reg: ldo0 {
453 /* LDO0 -> LP8733-LDO1 - VDA_DLL_0V8 */
454 regulator-name = "lp8733-ldo0";
455 regulator-min-microvolt = <800000>;
456 regulator-max-microvolt = <800000>;
457 regulator-boot-on;
458 regulator-always-on;
459 };
460
461 lp8733_ldo1_reg: ldo1 {
462 /* LDO1 -> LP8733-LDO2 - VDA_LN_1V8 */
463 regulator-name = "lp8733-ldo1";
464 regulator-min-microvolt = <1800000>;
465 regulator-max-microvolt = <1800000>;
466 regulator-always-on;
467 regulator-boot-on;
468 };
469 };
470 };
471
472 tps62873a: regulator@40 {
473 compatible = "ti,tps62873";
474 reg = <0x40>;
475 bootph-pre-ram;
476 regulator-name = "VDD_CPU_AVS";
477 regulator-min-microvolt = <600000>;
478 regulator-max-microvolt = <900000>;
479 regulator-boot-on;
480 regulator-always-on;
481 };
482
483 tps62873b: regulator@43 {
484 compatible = "ti,tps62873";
485 reg = <0x43>;
486 regulator-name = "VDD_CORE_0V8";
487 regulator-min-microvolt = <800000>;
488 regulator-max-microvolt = <800000>;
489 regulator-boot-on;
490 regulator-always-on;
491 };
492 };
493
494 &mcu_uart0 {
495 status = "okay";
496 pinctrl-names = "default";
497 pinctrl-0 = <&mcu_uart0_pins_default>;
498 };
499
500 &main_uart8 {
501 status = "okay";
502 pinctrl-names = "default";
503 pinctrl-0 = <&main_uart8_pins_default>;
504 /* Shared with TFA on this platform */
505 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
506 };
507
508 &main_i2c0 {
509 pinctrl-names = "default";
510 pinctrl-0 = <&main_i2c0_pins_default>;
511 clock-frequency = <400000>;
512
513 exp1: gpio@21 {
514 compatible = "ti,tca6416";
515 reg = <0x21>;
516 gpio-controller;
517 #gpio-cells = <2>;
518 gpio-line-names = " ", " ", " ", " ", " ",
519 "BOARDID_EEPROM_WP", "CAN_STB", " ",
520 "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz",
521 "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " ";
522 };
523 };
524
525 &main_i2c1 {
526 pinctrl-names = "default";
527 pinctrl-0 = <&main_i2c1_pins_default>;
528 status = "okay";
529
530 exp3: gpio@20 {
531 compatible = "ti,tca6408";
532 reg = <0x20>;
533 gpio-controller;
534 #gpio-cells = <2>;
535 gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn",
536 "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1",
537 "CSI1_B_GPIO1";
538 };
539
540 i2c-mux@70 {
541 compatible = "nxp,pca9543";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 reg = <0x70>;
545
546 cam0_i2c: i2c@0 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 reg = <0>;
550 };
551
552 cam1_i2c: i2c@1 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <1>;
556 };
557
558 };
559 };
560
561 &main_i2c4 {
562 status = "okay";
563 pinctrl-names = "default";
564 pinctrl-0 = <&main_i2c4_pins_default>;
565 clock-frequency = <400000>;
566 };
567
568 &mcu_i2c0 {
569 status = "okay";
570 pinctrl-names = "default";
571 pinctrl-0 = <&mcu_i2c0_pins_default>;
572 clock-frequency = <400000>;
573 };
574
575 &mcu_i2c1 {
576 status = "okay";
577 pinctrl-names = "default";
578 pinctrl-0 = <&mcu_i2c1_pins_default>;
579 /* i2c1 is used for DVI DDC, so we need to use 100kHz */
580 clock-frequency = <100000>;
581
582 exp2: gpio@20 {
583 compatible = "ti,tca6408";
584 reg = <0x20>;
585 gpio-controller;
586 #gpio-cells = <2>;
587 gpio-line-names = "HDMI_PDn","HDMI_LS_OE",
588 "DP0_3V3_EN","eDP_ENABLE";
589 };
590 };
591
592 &main_sdhci1 {
593 /* SD card */
594 status = "okay";
595 pinctrl-0 = <&main_mmc1_pins_default>;
596 pinctrl-names = "default";
597 disable-wp;
598 vmmc-supply = <&vdd_mmc1>;
599 vqmmc-supply = <&vdd_sd_dv>;
600 };
601
602 &mcu_cpsw {
603 pinctrl-names = "default";
604 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
605 };
606
607 &davinci_mdio {
608 phy0: ethernet-phy@0 {
609 reg = <0>;
610 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
611 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
612 ti,min-output-impedance;
613 };
614 };
615
616 &cpsw_port1 {
617 phy-mode = "rgmii-rxid";
618 phy-handle = <&phy0>;
619 };
620
621 &mcu_mcan0 {
622 status = "okay";
623 pinctrl-names = "default";
624 pinctrl-0 = <&mcu_mcan0_pins_default>;
625 phys = <&transceiver1>;
626 };
627
628 &mcu_mcan1 {
629 status = "okay";
630 pinctrl-names = "default";
631 pinctrl-0 = <&mcu_mcan1_pins_default>;
632 phys = <&transceiver2>;
633 };
634
635 &main_mcan6 {
636 status = "okay";
637 pinctrl-names = "default";
638 pinctrl-0 = <&main_mcan6_pins_default>;
639 phys = <&transceiver3>;
640 };
641
642 &main_mcan7 {
643 status = "okay";
644 pinctrl-names = "default";
645 pinctrl-0 = <&main_mcan7_pins_default>;
646 phys = <&transceiver4>;
647 };
648
649 &dss {
650 status = "okay";
651 pinctrl-names = "default";
652 pinctrl-0 = <&dss_vout0_pins_default>;
653 /*
654 * These clock assignments are chosen to enable the following outputs:
655 *
656 * VP0 - DisplayPort SST
657 * VP1 - DPI0
658 * VP2 - DSI
659 * VP3 - DPI1
660 */
661 assigned-clocks = <&k3_clks 158 2>,
662 <&k3_clks 158 5>,
663 <&k3_clks 158 14>,
664 <&k3_clks 158 18>;
665 assigned-clock-parents = <&k3_clks 158 3>,
666 <&k3_clks 158 7>,
667 <&k3_clks 158 16>,
668 <&k3_clks 158 22>;
669 };
670
671 &dss_ports {
672 #address-cells = <1>;
673 #size-cells = <0>;
674
675 /* HDMI */
676 port@1 {
677 reg = <1>;
678
679 dpi_out0: endpoint {
680 remote-endpoint = <&tfp410_in>;
681 };
682 };
683 };
684
685 &serdes_ln_ctrl {
686 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
687 <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
688 };
689
690 &serdes_refclk {
691 clock-frequency = <100000000>;
692 };
693
694 &serdes0 {
695 status = "okay";
696
697 serdes0_pcie_link: phy@0 {
698 reg = <0>;
699 cdns,num-lanes = <2>;
700 #phy-cells = <0>;
701 cdns,phy-type = <PHY_TYPE_PCIE>;
702 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
703 };
704
705 serdes0_usb_link: phy@2 {
706 status = "okay";
707 reg = <2>;
708 cdns,num-lanes = <1>;
709 #phy-cells = <0>;
710 cdns,phy-type = <PHY_TYPE_USB3>;
711 resets = <&serdes_wiz0 3>;
712 };
713 };
714
715 &pcie1_rc {
716 status = "okay";
717 reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
718 phys = <&serdes0_pcie_link>;
719 phy-names = "pcie-phy";
720 num-lanes = <2>;
721 };
722
723 &usb_serdes_mux {
724 idle-states = <0>; /* USB0 to SERDES lane 2 */
725 };
726
727 &usbss0 {
728 status = "okay";
729 pinctrl-0 = <&main_usbss0_pins_default>;
730 pinctrl-names = "default";
731 ti,vbus-divider;
732 };
733
734 &usb0 {
735 dr_mode = "host";
736 maximum-speed = "super-speed";
737 phys = <&serdes0_usb_link>;
738 phy-names = "cdns3,usb3-phy";
739 };
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