1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
10
11 #include "k3-serdes.h"
12
13 / {
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
18 };
19
20 cmn_refclk1: clock-cmnrefclk1 {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
24 };
25 };
26
27 &cbass_main {
28 msmc_ram: sram@70000000 {
29 compatible = "mmio-sram";
30 reg = <0x0 0x70000000 0x0 0x800000>;
31 #address-cells = <1>;
32 #size-cells = <1>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
34
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
37 };
38 };
39
40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
46
47 serdes_ln_ctrl: mux-controller@4080 {
48 compatible = "reg-mux";
49 reg = <0x4080 0x50>;
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
52 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
53 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
54 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
55 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
56 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
58 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
59 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
60 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
61 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
62 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
63 };
64
65 cpsw0_phy_gmii_sel: phy@4044 {
66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
67 ti,qsgmii-main-ports = <2>, <2>;
68 reg = <0x4044 0x20>;
69 #phy-cells = <1>;
70 };
71
72 usb_serdes_mux: mux-controller@4000 {
73 compatible = "reg-mux";
74 reg = <0x4000 0x20>;
75 #mux-control-cells = <1>;
76 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
77 <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
78 };
79
80 ehrpwm_tbclk: clock-controller@4140 {
81 compatible = "ti,am654-ehrpwm-tbclk";
82 reg = <0x4140 0x18>;
83 #clock-cells = <1>;
84 };
85 };
86
87 main_ehrpwm0: pwm@3000000 {
88 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
89 #pwm-cells = <3>;
90 reg = <0x00 0x3000000 0x00 0x100>;
91 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
92 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
93 clock-names = "tbclk", "fck";
94 status = "disabled";
95 };
96
97 main_ehrpwm1: pwm@3010000 {
98 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
99 #pwm-cells = <3>;
100 reg = <0x00 0x3010000 0x00 0x100>;
101 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
102 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
103 clock-names = "tbclk", "fck";
104 status = "disabled";
105 };
106
107 main_ehrpwm2: pwm@3020000 {
108 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
109 #pwm-cells = <3>;
110 reg = <0x00 0x3020000 0x00 0x100>;
111 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
112 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
113 clock-names = "tbclk", "fck";
114 status = "disabled";
115 };
116
117 main_ehrpwm3: pwm@3030000 {
118 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
119 #pwm-cells = <3>;
120 reg = <0x00 0x3030000 0x00 0x100>;
121 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
122 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
123 clock-names = "tbclk", "fck";
124 status = "disabled";
125 };
126
127 main_ehrpwm4: pwm@3040000 {
128 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
129 #pwm-cells = <3>;
130 reg = <0x00 0x3040000 0x00 0x100>;
131 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
132 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
133 clock-names = "tbclk", "fck";
134 status = "disabled";
135 };
136
137 main_ehrpwm5: pwm@3050000 {
138 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
139 #pwm-cells = <3>;
140 reg = <0x00 0x3050000 0x00 0x100>;
141 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
142 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
143 clock-names = "tbclk", "fck";
144 status = "disabled";
145 };
146
147 gic500: interrupt-controller@1800000 {
148 compatible = "arm,gic-v3";
149 #address-cells = <2>;
150 #size-cells = <2>;
151 ranges;
152 #interrupt-cells = <3>;
153 interrupt-controller;
154 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
155 <0x00 0x01900000 0x00 0x100000>, /* GICR */
156 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
157 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
158 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
159
160 /* vcpumntirq: virtual CPU interface maintenance interrupt */
161 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
162
163 gic_its: msi-controller@1820000 {
164 compatible = "arm,gic-v3-its";
165 reg = <0x00 0x01820000 0x00 0x10000>;
166 socionext,synquacer-pre-its = <0x1000000 0x400000>;
167 msi-controller;
168 #msi-cells = <1>;
169 };
170 };
171
172 main_gpio_intr: interrupt-controller@a00000 {
173 compatible = "ti,sci-intr";
174 reg = <0x00 0x00a00000 0x00 0x800>;
175 ti,intr-trigger-type = <1>;
176 interrupt-controller;
177 interrupt-parent = <&gic500>;
178 #interrupt-cells = <1>;
179 ti,sci = <&dmsc>;
180 ti,sci-dev-id = <131>;
181 ti,interrupt-ranges = <8 392 56>;
182 };
183
184 main_navss: bus@30000000 {
185 compatible = "simple-bus";
186 #address-cells = <2>;
187 #size-cells = <2>;
188 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
189 dma-coherent;
190 dma-ranges;
191
192 ti,sci-dev-id = <199>;
193
194 main_navss_intr: interrupt-controller@310e0000 {
195 compatible = "ti,sci-intr";
196 reg = <0x0 0x310e0000 0x0 0x4000>;
197 ti,intr-trigger-type = <4>;
198 interrupt-controller;
199 interrupt-parent = <&gic500>;
200 #interrupt-cells = <1>;
201 ti,sci = <&dmsc>;
202 ti,sci-dev-id = <213>;
203 ti,interrupt-ranges = <0 64 64>,
204 <64 448 64>,
205 <128 672 64>;
206 };
207
208 main_udmass_inta: interrupt-controller@33d00000 {
209 compatible = "ti,sci-inta";
210 reg = <0x0 0x33d00000 0x0 0x100000>;
211 interrupt-controller;
212 interrupt-parent = <&main_navss_intr>;
213 msi-controller;
214 #interrupt-cells = <0>;
215 ti,sci = <&dmsc>;
216 ti,sci-dev-id = <209>;
217 ti,interrupt-ranges = <0 0 256>;
218 };
219
220 secure_proxy_main: mailbox@32c00000 {
221 compatible = "ti,am654-secure-proxy";
222 #mbox-cells = <1>;
223 reg-names = "target_data", "rt", "scfg";
224 reg = <0x00 0x32c00000 0x00 0x100000>,
225 <0x00 0x32400000 0x00 0x100000>,
226 <0x00 0x32800000 0x00 0x100000>;
227 interrupt-names = "rx_011";
228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
229 };
230
231 smmu0: iommu@36600000 {
232 compatible = "arm,smmu-v3";
233 reg = <0x0 0x36600000 0x0 0x100000>;
234 interrupt-parent = <&gic500>;
235 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
236 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
237 interrupt-names = "eventq", "gerror";
238 #iommu-cells = <1>;
239 };
240
241 hwspinlock: spinlock@30e00000 {
242 compatible = "ti,am654-hwspinlock";
243 reg = <0x00 0x30e00000 0x00 0x1000>;
244 #hwlock-cells = <1>;
245 };
246
247 mailbox0_cluster0: mailbox@31f80000 {
248 compatible = "ti,am654-mailbox";
249 reg = <0x00 0x31f80000 0x00 0x200>;
250 #mbox-cells = <1>;
251 ti,mbox-num-users = <4>;
252 ti,mbox-num-fifos = <16>;
253 interrupt-parent = <&main_navss_intr>;
254 status = "disabled";
255 };
256
257 mailbox0_cluster1: mailbox@31f81000 {
258 compatible = "ti,am654-mailbox";
259 reg = <0x00 0x31f81000 0x00 0x200>;
260 #mbox-cells = <1>;
261 ti,mbox-num-users = <4>;
262 ti,mbox-num-fifos = <16>;
263 interrupt-parent = <&main_navss_intr>;
264 status = "disabled";
265 };
266
267 mailbox0_cluster2: mailbox@31f82000 {
268 compatible = "ti,am654-mailbox";
269 reg = <0x00 0x31f82000 0x00 0x200>;
270 #mbox-cells = <1>;
271 ti,mbox-num-users = <4>;
272 ti,mbox-num-fifos = <16>;
273 interrupt-parent = <&main_navss_intr>;
274 status = "disabled";
275 };
276
277 mailbox0_cluster3: mailbox@31f83000 {
278 compatible = "ti,am654-mailbox";
279 reg = <0x00 0x31f83000 0x00 0x200>;
280 #mbox-cells = <1>;
281 ti,mbox-num-users = <4>;
282 ti,mbox-num-fifos = <16>;
283 interrupt-parent = <&main_navss_intr>;
284 status = "disabled";
285 };
286
287 mailbox0_cluster4: mailbox@31f84000 {
288 compatible = "ti,am654-mailbox";
289 reg = <0x00 0x31f84000 0x00 0x200>;
290 #mbox-cells = <1>;
291 ti,mbox-num-users = <4>;
292 ti,mbox-num-fifos = <16>;
293 interrupt-parent = <&main_navss_intr>;
294 status = "disabled";
295 };
296
297 mailbox0_cluster5: mailbox@31f85000 {
298 compatible = "ti,am654-mailbox";
299 reg = <0x00 0x31f85000 0x00 0x200>;
300 #mbox-cells = <1>;
301 ti,mbox-num-users = <4>;
302 ti,mbox-num-fifos = <16>;
303 interrupt-parent = <&main_navss_intr>;
304 status = "disabled";
305 };
306
307 mailbox0_cluster6: mailbox@31f86000 {
308 compatible = "ti,am654-mailbox";
309 reg = <0x00 0x31f86000 0x00 0x200>;
310 #mbox-cells = <1>;
311 ti,mbox-num-users = <4>;
312 ti,mbox-num-fifos = <16>;
313 interrupt-parent = <&main_navss_intr>;
314 status = "disabled";
315 };
316
317 mailbox0_cluster7: mailbox@31f87000 {
318 compatible = "ti,am654-mailbox";
319 reg = <0x00 0x31f87000 0x00 0x200>;
320 #mbox-cells = <1>;
321 ti,mbox-num-users = <4>;
322 ti,mbox-num-fifos = <16>;
323 interrupt-parent = <&main_navss_intr>;
324 status = "disabled";
325 };
326
327 mailbox0_cluster8: mailbox@31f88000 {
328 compatible = "ti,am654-mailbox";
329 reg = <0x00 0x31f88000 0x00 0x200>;
330 #mbox-cells = <1>;
331 ti,mbox-num-users = <4>;
332 ti,mbox-num-fifos = <16>;
333 interrupt-parent = <&main_navss_intr>;
334 status = "disabled";
335 };
336
337 mailbox0_cluster9: mailbox@31f89000 {
338 compatible = "ti,am654-mailbox";
339 reg = <0x00 0x31f89000 0x00 0x200>;
340 #mbox-cells = <1>;
341 ti,mbox-num-users = <4>;
342 ti,mbox-num-fifos = <16>;
343 interrupt-parent = <&main_navss_intr>;
344 status = "disabled";
345 };
346
347 mailbox0_cluster10: mailbox@31f8a000 {
348 compatible = "ti,am654-mailbox";
349 reg = <0x00 0x31f8a000 0x00 0x200>;
350 #mbox-cells = <1>;
351 ti,mbox-num-users = <4>;
352 ti,mbox-num-fifos = <16>;
353 interrupt-parent = <&main_navss_intr>;
354 status = "disabled";
355 };
356
357 mailbox0_cluster11: mailbox@31f8b000 {
358 compatible = "ti,am654-mailbox";
359 reg = <0x00 0x31f8b000 0x00 0x200>;
360 #mbox-cells = <1>;
361 ti,mbox-num-users = <4>;
362 ti,mbox-num-fifos = <16>;
363 interrupt-parent = <&main_navss_intr>;
364 status = "disabled";
365 };
366
367 main_ringacc: ringacc@3c000000 {
368 compatible = "ti,am654-navss-ringacc";
369 reg = <0x0 0x3c000000 0x0 0x400000>,
370 <0x0 0x38000000 0x0 0x400000>,
371 <0x0 0x31120000 0x0 0x100>,
372 <0x0 0x33000000 0x0 0x40000>,
373 <0x0 0x31080000 0x0 0x40000>;
374 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
375 ti,num-rings = <1024>;
376 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
377 ti,sci = <&dmsc>;
378 ti,sci-dev-id = <211>;
379 msi-parent = <&main_udmass_inta>;
380 };
381
382 main_udmap: dma-controller@31150000 {
383 compatible = "ti,j721e-navss-main-udmap";
384 reg = <0x0 0x31150000 0x0 0x100>,
385 <0x0 0x34000000 0x0 0x100000>,
386 <0x0 0x35000000 0x0 0x100000>,
387 <0x0 0x30b00000 0x0 0x20000>,
388 <0x0 0x30c00000 0x0 0x10000>,
389 <0x0 0x30d00000 0x0 0x8000>;
390 reg-names = "gcfg", "rchanrt", "tchanrt",
391 "tchan", "rchan", "rflow";
392 msi-parent = <&main_udmass_inta>;
393 #dma-cells = <1>;
394
395 ti,sci = <&dmsc>;
396 ti,sci-dev-id = <212>;
397 ti,ringacc = <&main_ringacc>;
398
399 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
400 <0x0f>, /* TX_HCHAN */
401 <0x10>; /* TX_UHCHAN */
402 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
403 <0x0b>, /* RX_HCHAN */
404 <0x0c>; /* RX_UHCHAN */
405 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
406 };
407
408 cpts@310d0000 {
409 compatible = "ti,j721e-cpts";
410 reg = <0x0 0x310d0000 0x0 0x400>;
411 reg-names = "cpts";
412 clocks = <&k3_clks 201 1>;
413 clock-names = "cpts";
414 interrupts-extended = <&main_navss_intr 391>;
415 interrupt-names = "cpts";
416 ti,cpts-periodic-outputs = <6>;
417 ti,cpts-ext-ts-inputs = <8>;
418 };
419 };
420
421 cpsw0: ethernet@c000000 {
422 compatible = "ti,j721e-cpswxg-nuss";
423 #address-cells = <2>;
424 #size-cells = <2>;
425 reg = <0x0 0xc000000 0x0 0x200000>;
426 reg-names = "cpsw_nuss";
427 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
428 clocks = <&k3_clks 19 89>;
429 clock-names = "fck";
430 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
431
432 dmas = <&main_udmap 0xca00>,
433 <&main_udmap 0xca01>,
434 <&main_udmap 0xca02>,
435 <&main_udmap 0xca03>,
436 <&main_udmap 0xca04>,
437 <&main_udmap 0xca05>,
438 <&main_udmap 0xca06>,
439 <&main_udmap 0xca07>,
440 <&main_udmap 0x4a00>;
441 dma-names = "tx0", "tx1", "tx2", "tx3",
442 "tx4", "tx5", "tx6", "tx7",
443 "rx";
444
445 status = "disabled";
446
447 ethernet-ports {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 cpsw0_port1: port@1 {
451 reg = <1>;
452 ti,mac-only;
453 label = "port1";
454 status = "disabled";
455 };
456
457 cpsw0_port2: port@2 {
458 reg = <2>;
459 ti,mac-only;
460 label = "port2";
461 status = "disabled";
462 };
463
464 cpsw0_port3: port@3 {
465 reg = <3>;
466 ti,mac-only;
467 label = "port3";
468 status = "disabled";
469 };
470
471 cpsw0_port4: port@4 {
472 reg = <4>;
473 ti,mac-only;
474 label = "port4";
475 status = "disabled";
476 };
477
478 cpsw0_port5: port@5 {
479 reg = <5>;
480 ti,mac-only;
481 label = "port5";
482 status = "disabled";
483 };
484
485 cpsw0_port6: port@6 {
486 reg = <6>;
487 ti,mac-only;
488 label = "port6";
489 status = "disabled";
490 };
491
492 cpsw0_port7: port@7 {
493 reg = <7>;
494 ti,mac-only;
495 label = "port7";
496 status = "disabled";
497 };
498
499 cpsw0_port8: port@8 {
500 reg = <8>;
501 ti,mac-only;
502 label = "port8";
503 status = "disabled";
504 };
505 };
506
507 cpsw9g_mdio: mdio@f00 {
508 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
509 reg = <0x0 0xf00 0x0 0x100>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 clocks = <&k3_clks 19 89>;
513 clock-names = "fck";
514 bus_freq = <1000000>;
515 status = "disabled";
516 };
517
518 cpts@3d000 {
519 compatible = "ti,j721e-cpts";
520 reg = <0x0 0x3d000 0x0 0x400>;
521 clocks = <&k3_clks 19 16>;
522 clock-names = "cpts";
523 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
524 interrupt-names = "cpts";
525 ti,cpts-ext-ts-inputs = <4>;
526 ti,cpts-periodic-outputs = <2>;
527 };
528 };
529
530 main_crypto: crypto@4e00000 {
531 compatible = "ti,j721e-sa2ul";
532 reg = <0x0 0x4e00000 0x0 0x1200>;
533 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
534 #address-cells = <2>;
535 #size-cells = <2>;
536 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
537
538 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
539 <&main_udmap 0x4001>;
540 dma-names = "tx", "rx1", "rx2";
541
542 rng: rng@4e10000 {
543 compatible = "inside-secure,safexcel-eip76";
544 reg = <0x0 0x4e10000 0x0 0x7d>;
545 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
546 };
547 };
548
549 main_pmx0: pinctrl@11c000 {
550 compatible = "pinctrl-single";
551 /* Proxy 0 addressing */
552 reg = <0x0 0x11c000 0x0 0x2b4>;
553 #pinctrl-cells = <1>;
554 pinctrl-single,register-width = <32>;
555 pinctrl-single,function-mask = <0xffffffff>;
556 };
557
558 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
559 main_timerio_input: pinctrl@104200 {
560 compatible = "pinctrl-single";
561 reg = <0x00 0x104200 0x00 0x50>;
562 #pinctrl-cells = <1>;
563 pinctrl-single,register-width = <32>;
564 pinctrl-single,function-mask = <0x00000007>;
565 };
566
567 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
568 main_timerio_output: pinctrl@104280 {
569 compatible = "pinctrl-single";
570 reg = <0x00 0x104280 0x00 0x20>;
571 #pinctrl-cells = <1>;
572 pinctrl-single,register-width = <32>;
573 pinctrl-single,function-mask = <0x0000001f>;
574 };
575
576 ti_csi2rx0: ticsi2rx@4500000 {
577 compatible = "ti,j721e-csi2rx-shim";
578 reg = <0x0 0x4500000 0x0 0x1000>;
579 ranges;
580 #address-cells = <2>;
581 #size-cells = <2>;
582 dmas = <&main_udmap 0x4940>;
583 dma-names = "rx0";
584 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
585 status = "disabled";
586
587 cdns_csi2rx0: csi-bridge@4504000 {
588 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
589 reg = <0x0 0x4504000 0x0 0x1000>;
590 clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
591 <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
592 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
593 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
594 phys = <&dphy0>;
595 phy-names = "dphy";
596
597 ports {
598 #address-cells = <1>;
599 #size-cells = <0>;
600
601 csi0_port0: port@0 {
602 reg = <0>;
603 status = "disabled";
604 };
605
606 csi0_port1: port@1 {
607 reg = <1>;
608 status = "disabled";
609 };
610
611 csi0_port2: port@2 {
612 reg = <2>;
613 status = "disabled";
614 };
615
616 csi0_port3: port@3 {
617 reg = <3>;
618 status = "disabled";
619 };
620
621 csi0_port4: port@4 {
622 reg = <4>;
623 status = "disabled";
624 };
625 };
626 };
627 };
628
629 ti_csi2rx1: ticsi2rx@4510000 {
630 compatible = "ti,j721e-csi2rx-shim";
631 reg = <0x0 0x4510000 0x0 0x1000>;
632 ranges;
633 #address-cells = <2>;
634 #size-cells = <2>;
635 dmas = <&main_udmap 0x4960>;
636 dma-names = "rx0";
637 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
638 status = "disabled";
639
640 cdns_csi2rx1: csi-bridge@4514000 {
641 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
642 reg = <0x0 0x4514000 0x0 0x1000>;
643 clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
644 <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
645 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
646 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
647 phys = <&dphy1>;
648 phy-names = "dphy";
649
650 ports {
651 #address-cells = <1>;
652 #size-cells = <0>;
653
654 csi1_port0: port@0 {
655 reg = <0>;
656 status = "disabled";
657 };
658
659 csi1_port1: port@1 {
660 reg = <1>;
661 status = "disabled";
662 };
663
664 csi1_port2: port@2 {
665 reg = <2>;
666 status = "disabled";
667 };
668
669 csi1_port3: port@3 {
670 reg = <3>;
671 status = "disabled";
672 };
673
674 csi1_port4: port@4 {
675 reg = <4>;
676 status = "disabled";
677 };
678 };
679 };
680 };
681
682 dphy0: phy@4580000 {
683 compatible = "cdns,dphy-rx";
684 reg = <0x0 0x4580000 0x0 0x1100>;
685 #phy-cells = <0>;
686 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
687 status = "disabled";
688 };
689
690 dphy1: phy@4590000 {
691 compatible = "cdns,dphy-rx";
692 reg = <0x0 0x4590000 0x0 0x1100>;
693 #phy-cells = <0>;
694 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
695 status = "disabled";
696 };
697
698 serdes_wiz0: wiz@5000000 {
699 compatible = "ti,j721e-wiz-16g";
700 #address-cells = <1>;
701 #size-cells = <1>;
702 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
703 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
704 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
705 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
706 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
707 num-lanes = <2>;
708 #reset-cells = <1>;
709 ranges = <0x5000000 0x0 0x5000000 0x10000>;
710
711 wiz0_pll0_refclk: pll0-refclk {
712 clocks = <&k3_clks 292 11>, <&cmn_refclk>;
713 #clock-cells = <0>;
714 assigned-clocks = <&wiz0_pll0_refclk>;
715 assigned-clock-parents = <&k3_clks 292 11>;
716 };
717
718 wiz0_pll1_refclk: pll1-refclk {
719 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
720 #clock-cells = <0>;
721 assigned-clocks = <&wiz0_pll1_refclk>;
722 assigned-clock-parents = <&k3_clks 292 0>;
723 };
724
725 wiz0_refclk_dig: refclk-dig {
726 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
727 #clock-cells = <0>;
728 assigned-clocks = <&wiz0_refclk_dig>;
729 assigned-clock-parents = <&k3_clks 292 11>;
730 };
731
732 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
733 clocks = <&wiz0_refclk_dig>;
734 #clock-cells = <0>;
735 };
736
737 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
738 clocks = <&wiz0_pll1_refclk>;
739 #clock-cells = <0>;
740 };
741
742 serdes0: serdes@5000000 {
743 compatible = "ti,sierra-phy-t0";
744 reg-names = "serdes";
745 reg = <0x5000000 0x10000>;
746 #address-cells = <1>;
747 #size-cells = <0>;
748 #clock-cells = <1>;
749 resets = <&serdes_wiz0 0>;
750 reset-names = "sierra_reset";
751 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
752 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
753 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
754 "pll0_refclk", "pll1_refclk";
755 };
756 };
757
758 serdes_wiz1: wiz@5010000 {
759 compatible = "ti,j721e-wiz-16g";
760 #address-cells = <1>;
761 #size-cells = <1>;
762 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
763 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
764 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
765 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
766 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
767 num-lanes = <2>;
768 #reset-cells = <1>;
769 ranges = <0x5010000 0x0 0x5010000 0x10000>;
770
771 wiz1_pll0_refclk: pll0-refclk {
772 clocks = <&k3_clks 293 13>, <&cmn_refclk>;
773 #clock-cells = <0>;
774 assigned-clocks = <&wiz1_pll0_refclk>;
775 assigned-clock-parents = <&k3_clks 293 13>;
776 };
777
778 wiz1_pll1_refclk: pll1-refclk {
779 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
780 #clock-cells = <0>;
781 assigned-clocks = <&wiz1_pll1_refclk>;
782 assigned-clock-parents = <&k3_clks 293 0>;
783 };
784
785 wiz1_refclk_dig: refclk-dig {
786 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
787 #clock-cells = <0>;
788 assigned-clocks = <&wiz1_refclk_dig>;
789 assigned-clock-parents = <&k3_clks 293 13>;
790 };
791
792 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
793 clocks = <&wiz1_refclk_dig>;
794 #clock-cells = <0>;
795 };
796
797 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
798 clocks = <&wiz1_pll1_refclk>;
799 #clock-cells = <0>;
800 };
801
802 serdes1: serdes@5010000 {
803 compatible = "ti,sierra-phy-t0";
804 reg-names = "serdes";
805 reg = <0x5010000 0x10000>;
806 #address-cells = <1>;
807 #size-cells = <0>;
808 #clock-cells = <1>;
809 resets = <&serdes_wiz1 0>;
810 reset-names = "sierra_reset";
811 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
812 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
813 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
814 "pll0_refclk", "pll1_refclk";
815 };
816 };
817
818 serdes_wiz2: wiz@5020000 {
819 compatible = "ti,j721e-wiz-16g";
820 #address-cells = <1>;
821 #size-cells = <1>;
822 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
823 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
824 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
825 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
826 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
827 num-lanes = <2>;
828 #reset-cells = <1>;
829 ranges = <0x5020000 0x0 0x5020000 0x10000>;
830
831 wiz2_pll0_refclk: pll0-refclk {
832 clocks = <&k3_clks 294 11>, <&cmn_refclk>;
833 #clock-cells = <0>;
834 assigned-clocks = <&wiz2_pll0_refclk>;
835 assigned-clock-parents = <&k3_clks 294 11>;
836 };
837
838 wiz2_pll1_refclk: pll1-refclk {
839 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
840 #clock-cells = <0>;
841 assigned-clocks = <&wiz2_pll1_refclk>;
842 assigned-clock-parents = <&k3_clks 294 0>;
843 };
844
845 wiz2_refclk_dig: refclk-dig {
846 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
847 #clock-cells = <0>;
848 assigned-clocks = <&wiz2_refclk_dig>;
849 assigned-clock-parents = <&k3_clks 294 11>;
850 };
851
852 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
853 clocks = <&wiz2_refclk_dig>;
854 #clock-cells = <0>;
855 };
856
857 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
858 clocks = <&wiz2_pll1_refclk>;
859 #clock-cells = <0>;
860 };
861
862 serdes2: serdes@5020000 {
863 compatible = "ti,sierra-phy-t0";
864 reg-names = "serdes";
865 reg = <0x5020000 0x10000>;
866 #address-cells = <1>;
867 #size-cells = <0>;
868 #clock-cells = <1>;
869 resets = <&serdes_wiz2 0>;
870 reset-names = "sierra_reset";
871 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
872 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
873 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
874 "pll0_refclk", "pll1_refclk";
875 };
876 };
877
878 serdes_wiz3: wiz@5030000 {
879 compatible = "ti,j721e-wiz-16g";
880 #address-cells = <1>;
881 #size-cells = <1>;
882 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
883 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
884 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
885 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
886 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
887 num-lanes = <2>;
888 #reset-cells = <1>;
889 ranges = <0x5030000 0x0 0x5030000 0x10000>;
890
891 wiz3_pll0_refclk: pll0-refclk {
892 clocks = <&k3_clks 295 9>, <&cmn_refclk>;
893 #clock-cells = <0>;
894 assigned-clocks = <&wiz3_pll0_refclk>;
895 assigned-clock-parents = <&k3_clks 295 9>;
896 };
897
898 wiz3_pll1_refclk: pll1-refclk {
899 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
900 #clock-cells = <0>;
901 assigned-clocks = <&wiz3_pll1_refclk>;
902 assigned-clock-parents = <&k3_clks 295 0>;
903 };
904
905 wiz3_refclk_dig: refclk-dig {
906 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
907 #clock-cells = <0>;
908 assigned-clocks = <&wiz3_refclk_dig>;
909 assigned-clock-parents = <&k3_clks 295 9>;
910 };
911
912 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
913 clocks = <&wiz3_refclk_dig>;
914 #clock-cells = <0>;
915 };
916
917 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
918 clocks = <&wiz3_pll1_refclk>;
919 #clock-cells = <0>;
920 };
921
922 serdes3: serdes@5030000 {
923 compatible = "ti,sierra-phy-t0";
924 reg-names = "serdes";
925 reg = <0x5030000 0x10000>;
926 #address-cells = <1>;
927 #size-cells = <0>;
928 #clock-cells = <1>;
929 resets = <&serdes_wiz3 0>;
930 reset-names = "sierra_reset";
931 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
932 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
933 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
934 "pll0_refclk", "pll1_refclk";
935 };
936 };
937
938 pcie0_rc: pcie@2900000 {
939 compatible = "ti,j721e-pcie-host";
940 reg = <0x00 0x02900000 0x00 0x1000>,
941 <0x00 0x02907000 0x00 0x400>,
942 <0x00 0x0d000000 0x00 0x00800000>,
943 <0x00 0x10000000 0x00 0x00001000>;
944 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
945 interrupt-names = "link_state";
946 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
947 device_type = "pci";
948 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
949 max-link-speed = <3>;
950 num-lanes = <2>;
951 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
952 clocks = <&k3_clks 239 1>;
953 clock-names = "fck";
954 #address-cells = <3>;
955 #size-cells = <2>;
956 bus-range = <0x0 0xff>;
957 vendor-id = <0x104c>;
958 device-id = <0xb00d>;
959 msi-map = <0x0 &gic_its 0x0 0x10000>;
960 dma-coherent;
961 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
962 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
963 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
964 status = "disabled";
965 };
966
967 pcie1_rc: pcie@2910000 {
968 compatible = "ti,j721e-pcie-host";
969 reg = <0x00 0x02910000 0x00 0x1000>,
970 <0x00 0x02917000 0x00 0x400>,
971 <0x00 0x0d800000 0x00 0x00800000>,
972 <0x00 0x18000000 0x00 0x00001000>;
973 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
974 interrupt-names = "link_state";
975 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
976 device_type = "pci";
977 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
978 max-link-speed = <3>;
979 num-lanes = <2>;
980 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
981 clocks = <&k3_clks 240 1>;
982 clock-names = "fck";
983 #address-cells = <3>;
984 #size-cells = <2>;
985 bus-range = <0x0 0xff>;
986 vendor-id = <0x104c>;
987 device-id = <0xb00d>;
988 msi-map = <0x0 &gic_its 0x10000 0x10000>;
989 dma-coherent;
990 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
991 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
992 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
993 status = "disabled";
994 };
995
996 pcie2_rc: pcie@2920000 {
997 compatible = "ti,j721e-pcie-host";
998 reg = <0x00 0x02920000 0x00 0x1000>,
999 <0x00 0x02927000 0x00 0x400>,
1000 <0x00 0x0e000000 0x00 0x00800000>,
1001 <0x44 0x00000000 0x00 0x00001000>;
1002 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1003 interrupt-names = "link_state";
1004 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
1005 device_type = "pci";
1006 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
1007 max-link-speed = <3>;
1008 num-lanes = <2>;
1009 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
1010 clocks = <&k3_clks 241 1>;
1011 clock-names = "fck";
1012 #address-cells = <3>;
1013 #size-cells = <2>;
1014 bus-range = <0x0 0xff>;
1015 vendor-id = <0x104c>;
1016 device-id = <0xb00d>;
1017 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1018 dma-coherent;
1019 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
1020 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
1021 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1022 status = "disabled";
1023 };
1024
1025 pcie3_rc: pcie@2930000 {
1026 compatible = "ti,j721e-pcie-host";
1027 reg = <0x00 0x02930000 0x00 0x1000>,
1028 <0x00 0x02937000 0x00 0x400>,
1029 <0x00 0x0e800000 0x00 0x00800000>,
1030 <0x44 0x10000000 0x00 0x00001000>;
1031 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1032 interrupt-names = "link_state";
1033 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
1034 device_type = "pci";
1035 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
1036 max-link-speed = <3>;
1037 num-lanes = <2>;
1038 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
1039 clocks = <&k3_clks 242 1>;
1040 clock-names = "fck";
1041 #address-cells = <3>;
1042 #size-cells = <2>;
1043 bus-range = <0x0 0xff>;
1044 vendor-id = <0x104c>;
1045 device-id = <0xb00d>;
1046 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1047 dma-coherent;
1048 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
1049 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
1050 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1051 status = "disabled";
1052 };
1053
1054 serdes_wiz4: wiz@5050000 {
1055 compatible = "ti,am64-wiz-10g";
1056 #address-cells = <1>;
1057 #size-cells = <1>;
1058 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
1059 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
1060 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1061 assigned-clocks = <&k3_clks 297 9>;
1062 assigned-clock-parents = <&k3_clks 297 10>;
1063 assigned-clock-rates = <19200000>;
1064 num-lanes = <4>;
1065 #reset-cells = <1>;
1066 #clock-cells = <1>;
1067 ranges = <0x05050000 0x00 0x05050000 0x010000>,
1068 <0x0a030a00 0x00 0x0a030a00 0x40>;
1069
1070 serdes4: serdes@5050000 {
1071 /*
1072 * Note: we also map DPTX PHY registers as the Torrent
1073 * needs to manage those.
1074 */
1075 compatible = "ti,j721e-serdes-10g";
1076 reg = <0x05050000 0x010000>,
1077 <0x0a030a00 0x40>; /* DPTX PHY */
1078 reg-names = "torrent_phy", "dptx_phy";
1079
1080 resets = <&serdes_wiz4 0>;
1081 reset-names = "torrent_reset";
1082 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
1083 clock-names = "refclk";
1084 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
1085 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
1086 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
1087 assigned-clock-parents = <&k3_clks 297 9>,
1088 <&k3_clks 297 9>,
1089 <&k3_clks 297 9>;
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 };
1093 };
1094
1095 main_timer0: timer@2400000 {
1096 compatible = "ti,am654-timer";
1097 reg = <0x00 0x2400000 0x00 0x400>;
1098 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&k3_clks 49 1>;
1100 clock-names = "fck";
1101 assigned-clocks = <&k3_clks 49 1>;
1102 assigned-clock-parents = <&k3_clks 49 2>;
1103 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1104 ti,timer-pwm;
1105 };
1106
1107 main_timer1: timer@2410000 {
1108 compatible = "ti,am654-timer";
1109 reg = <0x00 0x2410000 0x00 0x400>;
1110 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&k3_clks 50 1>;
1112 clock-names = "fck";
1113 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
1114 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
1115 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1116 ti,timer-pwm;
1117 };
1118
1119 main_timer2: timer@2420000 {
1120 compatible = "ti,am654-timer";
1121 reg = <0x00 0x2420000 0x00 0x400>;
1122 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1123 clocks = <&k3_clks 51 1>;
1124 clock-names = "fck";
1125 assigned-clocks = <&k3_clks 51 1>;
1126 assigned-clock-parents = <&k3_clks 51 2>;
1127 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1128 ti,timer-pwm;
1129 };
1130
1131 main_timer3: timer@2430000 {
1132 compatible = "ti,am654-timer";
1133 reg = <0x00 0x2430000 0x00 0x400>;
1134 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1135 clocks = <&k3_clks 52 1>;
1136 clock-names = "fck";
1137 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1138 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1139 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1140 ti,timer-pwm;
1141 };
1142
1143 main_timer4: timer@2440000 {
1144 compatible = "ti,am654-timer";
1145 reg = <0x00 0x2440000 0x00 0x400>;
1146 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&k3_clks 53 1>;
1148 clock-names = "fck";
1149 assigned-clocks = <&k3_clks 53 1>;
1150 assigned-clock-parents = <&k3_clks 53 2>;
1151 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1152 ti,timer-pwm;
1153 };
1154
1155 main_timer5: timer@2450000 {
1156 compatible = "ti,am654-timer";
1157 reg = <0x00 0x2450000 0x00 0x400>;
1158 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1159 clocks = <&k3_clks 54 1>;
1160 clock-names = "fck";
1161 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1162 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1163 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1164 ti,timer-pwm;
1165 };
1166
1167 main_timer6: timer@2460000 {
1168 compatible = "ti,am654-timer";
1169 reg = <0x00 0x2460000 0x00 0x400>;
1170 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&k3_clks 55 1>;
1172 clock-names = "fck";
1173 assigned-clocks = <&k3_clks 55 1>;
1174 assigned-clock-parents = <&k3_clks 55 2>;
1175 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1176 ti,timer-pwm;
1177 };
1178
1179 main_timer7: timer@2470000 {
1180 compatible = "ti,am654-timer";
1181 reg = <0x00 0x2470000 0x00 0x400>;
1182 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&k3_clks 57 1>;
1184 clock-names = "fck";
1185 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1186 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1187 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1188 ti,timer-pwm;
1189 };
1190
1191 main_timer8: timer@2480000 {
1192 compatible = "ti,am654-timer";
1193 reg = <0x00 0x2480000 0x00 0x400>;
1194 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1195 clocks = <&k3_clks 58 1>;
1196 clock-names = "fck";
1197 assigned-clocks = <&k3_clks 58 1>;
1198 assigned-clock-parents = <&k3_clks 58 2>;
1199 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1200 ti,timer-pwm;
1201 };
1202
1203 main_timer9: timer@2490000 {
1204 compatible = "ti,am654-timer";
1205 reg = <0x00 0x2490000 0x00 0x400>;
1206 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&k3_clks 59 1>;
1208 clock-names = "fck";
1209 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1210 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1211 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1212 ti,timer-pwm;
1213 };
1214
1215 main_timer10: timer@24a0000 {
1216 compatible = "ti,am654-timer";
1217 reg = <0x00 0x24a0000 0x00 0x400>;
1218 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&k3_clks 60 1>;
1220 clock-names = "fck";
1221 assigned-clocks = <&k3_clks 60 1>;
1222 assigned-clock-parents = <&k3_clks 60 2>;
1223 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1224 ti,timer-pwm;
1225 };
1226
1227 main_timer11: timer@24b0000 {
1228 compatible = "ti,am654-timer";
1229 reg = <0x00 0x24b0000 0x00 0x400>;
1230 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&k3_clks 62 1>;
1232 clock-names = "fck";
1233 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1234 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1235 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1236 ti,timer-pwm;
1237 };
1238
1239 main_timer12: timer@24c0000 {
1240 compatible = "ti,am654-timer";
1241 reg = <0x00 0x24c0000 0x00 0x400>;
1242 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&k3_clks 63 1>;
1244 clock-names = "fck";
1245 assigned-clocks = <&k3_clks 63 1>;
1246 assigned-clock-parents = <&k3_clks 63 2>;
1247 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1248 ti,timer-pwm;
1249 };
1250
1251 main_timer13: timer@24d0000 {
1252 compatible = "ti,am654-timer";
1253 reg = <0x00 0x24d0000 0x00 0x400>;
1254 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1255 clocks = <&k3_clks 64 1>;
1256 clock-names = "fck";
1257 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1258 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1259 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1260 ti,timer-pwm;
1261 };
1262
1263 main_timer14: timer@24e0000 {
1264 compatible = "ti,am654-timer";
1265 reg = <0x00 0x24e0000 0x00 0x400>;
1266 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&k3_clks 65 1>;
1268 clock-names = "fck";
1269 assigned-clocks = <&k3_clks 65 1>;
1270 assigned-clock-parents = <&k3_clks 65 2>;
1271 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1272 ti,timer-pwm;
1273 };
1274
1275 main_timer15: timer@24f0000 {
1276 compatible = "ti,am654-timer";
1277 reg = <0x00 0x24f0000 0x00 0x400>;
1278 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&k3_clks 66 1>;
1280 clock-names = "fck";
1281 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1282 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1283 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1284 ti,timer-pwm;
1285 };
1286
1287 main_timer16: timer@2500000 {
1288 compatible = "ti,am654-timer";
1289 reg = <0x00 0x2500000 0x00 0x400>;
1290 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1291 clocks = <&k3_clks 67 1>;
1292 clock-names = "fck";
1293 assigned-clocks = <&k3_clks 67 1>;
1294 assigned-clock-parents = <&k3_clks 67 2>;
1295 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1296 ti,timer-pwm;
1297 };
1298
1299 main_timer17: timer@2510000 {
1300 compatible = "ti,am654-timer";
1301 reg = <0x00 0x2510000 0x00 0x400>;
1302 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&k3_clks 68 1>;
1304 clock-names = "fck";
1305 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1306 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1307 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1308 ti,timer-pwm;
1309 };
1310
1311 main_timer18: timer@2520000 {
1312 compatible = "ti,am654-timer";
1313 reg = <0x00 0x2520000 0x00 0x400>;
1314 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1315 clocks = <&k3_clks 69 1>;
1316 clock-names = "fck";
1317 assigned-clocks = <&k3_clks 69 1>;
1318 assigned-clock-parents = <&k3_clks 69 2>;
1319 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1320 ti,timer-pwm;
1321 };
1322
1323 main_timer19: timer@2530000 {
1324 compatible = "ti,am654-timer";
1325 reg = <0x00 0x2530000 0x00 0x400>;
1326 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1327 clocks = <&k3_clks 70 1>;
1328 clock-names = "fck";
1329 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1330 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1331 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1332 ti,timer-pwm;
1333 };
1334
1335 main_uart0: serial@2800000 {
1336 compatible = "ti,j721e-uart", "ti,am654-uart";
1337 reg = <0x00 0x02800000 0x00 0x100>;
1338 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1339 clock-frequency = <48000000>;
1340 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1341 clocks = <&k3_clks 146 0>;
1342 clock-names = "fclk";
1343 status = "disabled";
1344 };
1345
1346 main_uart1: serial@2810000 {
1347 compatible = "ti,j721e-uart", "ti,am654-uart";
1348 reg = <0x00 0x02810000 0x00 0x100>;
1349 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
1350 clock-frequency = <48000000>;
1351 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1352 clocks = <&k3_clks 278 0>;
1353 clock-names = "fclk";
1354 status = "disabled";
1355 };
1356
1357 main_uart2: serial@2820000 {
1358 compatible = "ti,j721e-uart", "ti,am654-uart";
1359 reg = <0x00 0x02820000 0x00 0x100>;
1360 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1361 clock-frequency = <48000000>;
1362 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1363 clocks = <&k3_clks 279 0>;
1364 clock-names = "fclk";
1365 status = "disabled";
1366 };
1367
1368 main_uart3: serial@2830000 {
1369 compatible = "ti,j721e-uart", "ti,am654-uart";
1370 reg = <0x00 0x02830000 0x00 0x100>;
1371 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
1372 clock-frequency = <48000000>;
1373 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1374 clocks = <&k3_clks 280 0>;
1375 clock-names = "fclk";
1376 status = "disabled";
1377 };
1378
1379 main_uart4: serial@2840000 {
1380 compatible = "ti,j721e-uart", "ti,am654-uart";
1381 reg = <0x00 0x02840000 0x00 0x100>;
1382 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
1383 clock-frequency = <48000000>;
1384 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1385 clocks = <&k3_clks 281 0>;
1386 clock-names = "fclk";
1387 status = "disabled";
1388 };
1389
1390 main_uart5: serial@2850000 {
1391 compatible = "ti,j721e-uart", "ti,am654-uart";
1392 reg = <0x00 0x02850000 0x00 0x100>;
1393 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1394 clock-frequency = <48000000>;
1395 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1396 clocks = <&k3_clks 282 0>;
1397 clock-names = "fclk";
1398 status = "disabled";
1399 };
1400
1401 main_uart6: serial@2860000 {
1402 compatible = "ti,j721e-uart", "ti,am654-uart";
1403 reg = <0x00 0x02860000 0x00 0x100>;
1404 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
1405 clock-frequency = <48000000>;
1406 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1407 clocks = <&k3_clks 283 0>;
1408 clock-names = "fclk";
1409 status = "disabled";
1410 };
1411
1412 main_uart7: serial@2870000 {
1413 compatible = "ti,j721e-uart", "ti,am654-uart";
1414 reg = <0x00 0x02870000 0x00 0x100>;
1415 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1416 clock-frequency = <48000000>;
1417 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1418 clocks = <&k3_clks 284 0>;
1419 clock-names = "fclk";
1420 status = "disabled";
1421 };
1422
1423 main_uart8: serial@2880000 {
1424 compatible = "ti,j721e-uart", "ti,am654-uart";
1425 reg = <0x00 0x02880000 0x00 0x100>;
1426 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
1427 clock-frequency = <48000000>;
1428 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1429 clocks = <&k3_clks 285 0>;
1430 clock-names = "fclk";
1431 status = "disabled";
1432 };
1433
1434 main_uart9: serial@2890000 {
1435 compatible = "ti,j721e-uart", "ti,am654-uart";
1436 reg = <0x00 0x02890000 0x00 0x100>;
1437 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
1438 clock-frequency = <48000000>;
1439 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1440 clocks = <&k3_clks 286 0>;
1441 clock-names = "fclk";
1442 status = "disabled";
1443 };
1444
1445 main_gpio0: gpio@600000 {
1446 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1447 reg = <0x0 0x00600000 0x0 0x100>;
1448 gpio-controller;
1449 #gpio-cells = <2>;
1450 interrupt-parent = <&main_gpio_intr>;
1451 interrupts = <256>, <257>, <258>, <259>,
1452 <260>, <261>, <262>, <263>;
1453 interrupt-controller;
1454 #interrupt-cells = <2>;
1455 ti,ngpio = <128>;
1456 ti,davinci-gpio-unbanked = <0>;
1457 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1458 clocks = <&k3_clks 105 0>;
1459 clock-names = "gpio";
1460 status = "disabled";
1461 };
1462
1463 main_gpio1: gpio@601000 {
1464 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1465 reg = <0x0 0x00601000 0x0 0x100>;
1466 gpio-controller;
1467 #gpio-cells = <2>;
1468 interrupt-parent = <&main_gpio_intr>;
1469 interrupts = <288>, <289>, <290>;
1470 interrupt-controller;
1471 #interrupt-cells = <2>;
1472 ti,ngpio = <36>;
1473 ti,davinci-gpio-unbanked = <0>;
1474 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1475 clocks = <&k3_clks 106 0>;
1476 clock-names = "gpio";
1477 status = "disabled";
1478 };
1479
1480 main_gpio2: gpio@610000 {
1481 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1482 reg = <0x0 0x00610000 0x0 0x100>;
1483 gpio-controller;
1484 #gpio-cells = <2>;
1485 interrupt-parent = <&main_gpio_intr>;
1486 interrupts = <264>, <265>, <266>, <267>,
1487 <268>, <269>, <270>, <271>;
1488 interrupt-controller;
1489 #interrupt-cells = <2>;
1490 ti,ngpio = <128>;
1491 ti,davinci-gpio-unbanked = <0>;
1492 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1493 clocks = <&k3_clks 107 0>;
1494 clock-names = "gpio";
1495 status = "disabled";
1496 };
1497
1498 main_gpio3: gpio@611000 {
1499 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1500 reg = <0x0 0x00611000 0x0 0x100>;
1501 gpio-controller;
1502 #gpio-cells = <2>;
1503 interrupt-parent = <&main_gpio_intr>;
1504 interrupts = <292>, <293>, <294>;
1505 interrupt-controller;
1506 #interrupt-cells = <2>;
1507 ti,ngpio = <36>;
1508 ti,davinci-gpio-unbanked = <0>;
1509 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1510 clocks = <&k3_clks 108 0>;
1511 clock-names = "gpio";
1512 status = "disabled";
1513 };
1514
1515 main_gpio4: gpio@620000 {
1516 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1517 reg = <0x0 0x00620000 0x0 0x100>;
1518 gpio-controller;
1519 #gpio-cells = <2>;
1520 interrupt-parent = <&main_gpio_intr>;
1521 interrupts = <272>, <273>, <274>, <275>,
1522 <276>, <277>, <278>, <279>;
1523 interrupt-controller;
1524 #interrupt-cells = <2>;
1525 ti,ngpio = <128>;
1526 ti,davinci-gpio-unbanked = <0>;
1527 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1528 clocks = <&k3_clks 109 0>;
1529 clock-names = "gpio";
1530 status = "disabled";
1531 };
1532
1533 main_gpio5: gpio@621000 {
1534 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1535 reg = <0x0 0x00621000 0x0 0x100>;
1536 gpio-controller;
1537 #gpio-cells = <2>;
1538 interrupt-parent = <&main_gpio_intr>;
1539 interrupts = <296>, <297>, <298>;
1540 interrupt-controller;
1541 #interrupt-cells = <2>;
1542 ti,ngpio = <36>;
1543 ti,davinci-gpio-unbanked = <0>;
1544 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1545 clocks = <&k3_clks 110 0>;
1546 clock-names = "gpio";
1547 status = "disabled";
1548 };
1549
1550 main_gpio6: gpio@630000 {
1551 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1552 reg = <0x0 0x00630000 0x0 0x100>;
1553 gpio-controller;
1554 #gpio-cells = <2>;
1555 interrupt-parent = <&main_gpio_intr>;
1556 interrupts = <280>, <281>, <282>, <283>,
1557 <284>, <285>, <286>, <287>;
1558 interrupt-controller;
1559 #interrupt-cells = <2>;
1560 ti,ngpio = <128>;
1561 ti,davinci-gpio-unbanked = <0>;
1562 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1563 clocks = <&k3_clks 111 0>;
1564 clock-names = "gpio";
1565 status = "disabled";
1566 };
1567
1568 main_gpio7: gpio@631000 {
1569 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1570 reg = <0x0 0x00631000 0x0 0x100>;
1571 gpio-controller;
1572 #gpio-cells = <2>;
1573 interrupt-parent = <&main_gpio_intr>;
1574 interrupts = <300>, <301>, <302>;
1575 interrupt-controller;
1576 #interrupt-cells = <2>;
1577 ti,ngpio = <36>;
1578 ti,davinci-gpio-unbanked = <0>;
1579 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1580 clocks = <&k3_clks 112 0>;
1581 clock-names = "gpio";
1582 status = "disabled";
1583 };
1584
1585 main_sdhci0: mmc@4f80000 {
1586 compatible = "ti,j721e-sdhci-8bit";
1587 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1588 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1589 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1590 clock-names = "clk_ahb", "clk_xin";
1591 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1592 assigned-clocks = <&k3_clks 91 1>;
1593 assigned-clock-parents = <&k3_clks 91 2>;
1594 bus-width = <8>;
1595 mmc-hs200-1_8v;
1596 mmc-ddr-1_8v;
1597 ti,otap-del-sel-legacy = <0x0>;
1598 ti,otap-del-sel-mmc-hs = <0x0>;
1599 ti,otap-del-sel-ddr52 = <0x5>;
1600 ti,otap-del-sel-hs200 = <0x6>;
1601 ti,otap-del-sel-hs400 = <0x0>;
1602 ti,itap-del-sel-legacy = <0x10>;
1603 ti,itap-del-sel-mmc-hs = <0xa>;
1604 ti,itap-del-sel-ddr52 = <0x3>;
1605 ti,trm-icp = <0x8>;
1606 dma-coherent;
1607 status = "disabled";
1608 };
1609
1610 main_sdhci1: mmc@4fb0000 {
1611 compatible = "ti,j721e-sdhci-4bit";
1612 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1613 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1614 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1615 clock-names = "clk_ahb", "clk_xin";
1616 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1617 assigned-clocks = <&k3_clks 92 0>;
1618 assigned-clock-parents = <&k3_clks 92 1>;
1619 ti,otap-del-sel-legacy = <0x0>;
1620 ti,otap-del-sel-sd-hs = <0x0>;
1621 ti,otap-del-sel-sdr12 = <0xf>;
1622 ti,otap-del-sel-sdr25 = <0xf>;
1623 ti,otap-del-sel-sdr50 = <0xc>;
1624 ti,otap-del-sel-ddr50 = <0xc>;
1625 ti,otap-del-sel-sdr104 = <0x5>;
1626 ti,itap-del-sel-legacy = <0x0>;
1627 ti,itap-del-sel-sd-hs = <0x0>;
1628 ti,itap-del-sel-sdr12 = <0x0>;
1629 ti,itap-del-sel-sdr25 = <0x0>;
1630 ti,itap-del-sel-ddr50 = <0x2>;
1631 ti,trm-icp = <0x8>;
1632 ti,clkbuf-sel = <0x7>;
1633 dma-coherent;
1634 sdhci-caps-mask = <0x2 0x0>;
1635 status = "disabled";
1636 };
1637
1638 main_sdhci2: mmc@4f98000 {
1639 compatible = "ti,j721e-sdhci-4bit";
1640 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1641 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1642 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1643 clock-names = "clk_ahb", "clk_xin";
1644 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1645 assigned-clocks = <&k3_clks 93 0>;
1646 assigned-clock-parents = <&k3_clks 93 1>;
1647 ti,otap-del-sel-legacy = <0x0>;
1648 ti,otap-del-sel-sd-hs = <0x0>;
1649 ti,otap-del-sel-sdr12 = <0xf>;
1650 ti,otap-del-sel-sdr25 = <0xf>;
1651 ti,otap-del-sel-sdr50 = <0xc>;
1652 ti,otap-del-sel-ddr50 = <0xc>;
1653 ti,otap-del-sel-sdr104 = <0x5>;
1654 ti,itap-del-sel-legacy = <0x0>;
1655 ti,itap-del-sel-sd-hs = <0x0>;
1656 ti,itap-del-sel-sdr12 = <0x0>;
1657 ti,itap-del-sel-sdr25 = <0x0>;
1658 ti,itap-del-sel-ddr50 = <0x2>;
1659 ti,trm-icp = <0x8>;
1660 ti,clkbuf-sel = <0x7>;
1661 dma-coherent;
1662 sdhci-caps-mask = <0x2 0x0>;
1663 status = "disabled";
1664 };
1665
1666 usbss0: cdns-usb@4104000 {
1667 compatible = "ti,j721e-usb";
1668 reg = <0x00 0x4104000 0x00 0x100>;
1669 dma-coherent;
1670 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1671 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1672 clock-names = "ref", "lpm";
1673 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1674 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1675 #address-cells = <2>;
1676 #size-cells = <2>;
1677 ranges;
1678
1679 usb0: usb@6000000 {
1680 compatible = "cdns,usb3";
1681 reg = <0x00 0x6000000 0x00 0x10000>,
1682 <0x00 0x6010000 0x00 0x10000>,
1683 <0x00 0x6020000 0x00 0x10000>;
1684 reg-names = "otg", "xhci", "dev";
1685 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1686 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1687 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1688 interrupt-names = "host",
1689 "peripheral",
1690 "otg";
1691 maximum-speed = "super-speed";
1692 dr_mode = "otg";
1693 };
1694 };
1695
1696 usbss1: cdns-usb@4114000 {
1697 compatible = "ti,j721e-usb";
1698 reg = <0x00 0x4114000 0x00 0x100>;
1699 dma-coherent;
1700 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1701 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1702 clock-names = "ref", "lpm";
1703 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1704 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1705 #address-cells = <2>;
1706 #size-cells = <2>;
1707 ranges;
1708
1709 usb1: usb@6400000 {
1710 compatible = "cdns,usb3";
1711 reg = <0x00 0x6400000 0x00 0x10000>,
1712 <0x00 0x6410000 0x00 0x10000>,
1713 <0x00 0x6420000 0x00 0x10000>;
1714 reg-names = "otg", "xhci", "dev";
1715 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1716 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1717 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1718 interrupt-names = "host",
1719 "peripheral",
1720 "otg";
1721 maximum-speed = "super-speed";
1722 dr_mode = "otg";
1723 };
1724 };
1725
1726 main_i2c0: i2c@2000000 {
1727 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1728 reg = <0x0 0x2000000 0x0 0x100>;
1729 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 clock-names = "fck";
1733 clocks = <&k3_clks 187 0>;
1734 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1735 status = "disabled";
1736 };
1737
1738 main_i2c1: i2c@2010000 {
1739 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1740 reg = <0x0 0x2010000 0x0 0x100>;
1741 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1742 #address-cells = <1>;
1743 #size-cells = <0>;
1744 clock-names = "fck";
1745 clocks = <&k3_clks 188 0>;
1746 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1747 status = "disabled";
1748 };
1749
1750 main_i2c2: i2c@2020000 {
1751 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1752 reg = <0x0 0x2020000 0x0 0x100>;
1753 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1756 clock-names = "fck";
1757 clocks = <&k3_clks 189 0>;
1758 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1759 status = "disabled";
1760 };
1761
1762 main_i2c3: i2c@2030000 {
1763 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1764 reg = <0x0 0x2030000 0x0 0x100>;
1765 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1768 clock-names = "fck";
1769 clocks = <&k3_clks 190 0>;
1770 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1771 status = "disabled";
1772 };
1773
1774 main_i2c4: i2c@2040000 {
1775 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1776 reg = <0x0 0x2040000 0x0 0x100>;
1777 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1778 #address-cells = <1>;
1779 #size-cells = <0>;
1780 clock-names = "fck";
1781 clocks = <&k3_clks 191 0>;
1782 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1783 status = "disabled";
1784 };
1785
1786 main_i2c5: i2c@2050000 {
1787 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1788 reg = <0x0 0x2050000 0x0 0x100>;
1789 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1790 #address-cells = <1>;
1791 #size-cells = <0>;
1792 clock-names = "fck";
1793 clocks = <&k3_clks 192 0>;
1794 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1795 status = "disabled";
1796 };
1797
1798 main_i2c6: i2c@2060000 {
1799 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1800 reg = <0x0 0x2060000 0x0 0x100>;
1801 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1802 #address-cells = <1>;
1803 #size-cells = <0>;
1804 clock-names = "fck";
1805 clocks = <&k3_clks 193 0>;
1806 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1807 status = "disabled";
1808 };
1809
1810 ufs_wrapper: ufs-wrapper@4e80000 {
1811 compatible = "ti,j721e-ufs";
1812 reg = <0x0 0x4e80000 0x0 0x100>;
1813 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1814 clocks = <&k3_clks 277 1>;
1815 assigned-clocks = <&k3_clks 277 1>;
1816 assigned-clock-parents = <&k3_clks 277 4>;
1817 ranges;
1818 #address-cells = <2>;
1819 #size-cells = <2>;
1820
1821 ufs@4e84000 {
1822 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1823 reg = <0x0 0x4e84000 0x0 0x10000>;
1824 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1825 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1826 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1827 clock-names = "core_clk", "phy_clk", "ref_clk";
1828 dma-coherent;
1829 };
1830 };
1831
1832 mhdp: dp-bridge@a000000 {
1833 compatible = "ti,j721e-mhdp8546";
1834 /*
1835 * Note: we do not map DPTX PHY area, as that is handled by
1836 * the PHY driver.
1837 */
1838 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1839 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1840 reg-names = "mhdptx", "j721e-intg";
1841
1842 clocks = <&k3_clks 151 36>;
1843
1844 interrupt-parent = <&gic500>;
1845 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
1846
1847 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1848
1849 dp0_ports: ports {
1850 #address-cells = <1>;
1851 #size-cells = <0>;
1852
1853 port@0 {
1854 reg = <0>;
1855 };
1856
1857 port@4 {
1858 reg = <4>;
1859 };
1860 };
1861 };
1862
1863 dss: dss@4a00000 {
1864 compatible = "ti,j721e-dss";
1865 reg =
1866 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1867 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1868 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1869 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1870
1871 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1872 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1873 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1874 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1875
1876 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1877 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1878 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1879 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1880
1881 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1882 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1883 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1884 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1885 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1886
1887 reg-names = "common_m", "common_s0",
1888 "common_s1", "common_s2",
1889 "vidl1", "vidl2","vid1","vid2",
1890 "ovr1", "ovr2", "ovr3", "ovr4",
1891 "vp1", "vp2", "vp3", "vp4",
1892 "wb";
1893
1894 clocks = <&k3_clks 152 0>,
1895 <&k3_clks 152 1>,
1896 <&k3_clks 152 4>,
1897 <&k3_clks 152 9>,
1898 <&k3_clks 152 13>;
1899 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1900
1901 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1902
1903 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1907 interrupt-names = "common_m",
1908 "common_s0",
1909 "common_s1",
1910 "common_s2";
1911
1912 dss_ports: ports {
1913 };
1914 };
1915
1916 mcasp0: mcasp@2b00000 {
1917 compatible = "ti,am33xx-mcasp-audio";
1918 reg = <0x0 0x02b00000 0x0 0x2000>,
1919 <0x0 0x02b08000 0x0 0x1000>;
1920 reg-names = "mpu","dat";
1921 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1923 interrupt-names = "tx", "rx";
1924
1925 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1926 dma-names = "tx", "rx";
1927
1928 clocks = <&k3_clks 174 1>;
1929 clock-names = "fck";
1930 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1931 status = "disabled";
1932 };
1933
1934 mcasp1: mcasp@2b10000 {
1935 compatible = "ti,am33xx-mcasp-audio";
1936 reg = <0x0 0x02b10000 0x0 0x2000>,
1937 <0x0 0x02b18000 0x0 0x1000>;
1938 reg-names = "mpu","dat";
1939 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1941 interrupt-names = "tx", "rx";
1942
1943 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1944 dma-names = "tx", "rx";
1945
1946 clocks = <&k3_clks 175 1>;
1947 clock-names = "fck";
1948 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1949 status = "disabled";
1950 };
1951
1952 mcasp2: mcasp@2b20000 {
1953 compatible = "ti,am33xx-mcasp-audio";
1954 reg = <0x0 0x02b20000 0x0 0x2000>,
1955 <0x0 0x02b28000 0x0 0x1000>;
1956 reg-names = "mpu","dat";
1957 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1959 interrupt-names = "tx", "rx";
1960
1961 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1962 dma-names = "tx", "rx";
1963
1964 clocks = <&k3_clks 176 1>;
1965 clock-names = "fck";
1966 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1967 status = "disabled";
1968 };
1969
1970 mcasp3: mcasp@2b30000 {
1971 compatible = "ti,am33xx-mcasp-audio";
1972 reg = <0x0 0x02b30000 0x0 0x2000>,
1973 <0x0 0x02b38000 0x0 0x1000>;
1974 reg-names = "mpu","dat";
1975 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1976 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1977 interrupt-names = "tx", "rx";
1978
1979 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1980 dma-names = "tx", "rx";
1981
1982 clocks = <&k3_clks 177 1>;
1983 clock-names = "fck";
1984 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1985 status = "disabled";
1986 };
1987
1988 mcasp4: mcasp@2b40000 {
1989 compatible = "ti,am33xx-mcasp-audio";
1990 reg = <0x0 0x02b40000 0x0 0x2000>,
1991 <0x0 0x02b48000 0x0 0x1000>;
1992 reg-names = "mpu","dat";
1993 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1994 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1995 interrupt-names = "tx", "rx";
1996
1997 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1998 dma-names = "tx", "rx";
1999
2000 clocks = <&k3_clks 178 1>;
2001 clock-names = "fck";
2002 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
2003 status = "disabled";
2004 };
2005
2006 mcasp5: mcasp@2b50000 {
2007 compatible = "ti,am33xx-mcasp-audio";
2008 reg = <0x0 0x02b50000 0x0 0x2000>,
2009 <0x0 0x02b58000 0x0 0x1000>;
2010 reg-names = "mpu","dat";
2011 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
2013 interrupt-names = "tx", "rx";
2014
2015 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
2016 dma-names = "tx", "rx";
2017
2018 clocks = <&k3_clks 179 1>;
2019 clock-names = "fck";
2020 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
2021 status = "disabled";
2022 };
2023
2024 mcasp6: mcasp@2b60000 {
2025 compatible = "ti,am33xx-mcasp-audio";
2026 reg = <0x0 0x02b60000 0x0 0x2000>,
2027 <0x0 0x02b68000 0x0 0x1000>;
2028 reg-names = "mpu","dat";
2029 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
2031 interrupt-names = "tx", "rx";
2032
2033 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
2034 dma-names = "tx", "rx";
2035
2036 clocks = <&k3_clks 180 1>;
2037 clock-names = "fck";
2038 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
2039 status = "disabled";
2040 };
2041
2042 mcasp7: mcasp@2b70000 {
2043 compatible = "ti,am33xx-mcasp-audio";
2044 reg = <0x0 0x02b70000 0x0 0x2000>,
2045 <0x0 0x02b78000 0x0 0x1000>;
2046 reg-names = "mpu","dat";
2047 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
2048 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
2049 interrupt-names = "tx", "rx";
2050
2051 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
2052 dma-names = "tx", "rx";
2053
2054 clocks = <&k3_clks 181 1>;
2055 clock-names = "fck";
2056 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
2057 status = "disabled";
2058 };
2059
2060 mcasp8: mcasp@2b80000 {
2061 compatible = "ti,am33xx-mcasp-audio";
2062 reg = <0x0 0x02b80000 0x0 0x2000>,
2063 <0x0 0x02b88000 0x0 0x1000>;
2064 reg-names = "mpu","dat";
2065 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
2066 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
2067 interrupt-names = "tx", "rx";
2068
2069 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
2070 dma-names = "tx", "rx";
2071
2072 clocks = <&k3_clks 182 1>;
2073 clock-names = "fck";
2074 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
2075 status = "disabled";
2076 };
2077
2078 mcasp9: mcasp@2b90000 {
2079 compatible = "ti,am33xx-mcasp-audio";
2080 reg = <0x0 0x02b90000 0x0 0x2000>,
2081 <0x0 0x02b98000 0x0 0x1000>;
2082 reg-names = "mpu","dat";
2083 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
2085 interrupt-names = "tx", "rx";
2086
2087 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
2088 dma-names = "tx", "rx";
2089
2090 clocks = <&k3_clks 183 1>;
2091 clock-names = "fck";
2092 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
2093 status = "disabled";
2094 };
2095
2096 mcasp10: mcasp@2ba0000 {
2097 compatible = "ti,am33xx-mcasp-audio";
2098 reg = <0x0 0x02ba0000 0x0 0x2000>,
2099 <0x0 0x02ba8000 0x0 0x1000>;
2100 reg-names = "mpu","dat";
2101 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
2102 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
2103 interrupt-names = "tx", "rx";
2104
2105 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
2106 dma-names = "tx", "rx";
2107
2108 clocks = <&k3_clks 184 1>;
2109 clock-names = "fck";
2110 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
2111 status = "disabled";
2112 };
2113
2114 mcasp11: mcasp@2bb0000 {
2115 compatible = "ti,am33xx-mcasp-audio";
2116 reg = <0x0 0x02bb0000 0x0 0x2000>,
2117 <0x0 0x02bb8000 0x0 0x1000>;
2118 reg-names = "mpu","dat";
2119 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
2120 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
2121 interrupt-names = "tx", "rx";
2122
2123 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2124 dma-names = "tx", "rx";
2125
2126 clocks = <&k3_clks 185 1>;
2127 clock-names = "fck";
2128 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
2129 status = "disabled";
2130 };
2131
2132 watchdog0: watchdog@2200000 {
2133 compatible = "ti,j7-rti-wdt";
2134 reg = <0x0 0x2200000 0x0 0x100>;
2135 clocks = <&k3_clks 252 1>;
2136 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2137 assigned-clocks = <&k3_clks 252 1>;
2138 assigned-clock-parents = <&k3_clks 252 5>;
2139 };
2140
2141 watchdog1: watchdog@2210000 {
2142 compatible = "ti,j7-rti-wdt";
2143 reg = <0x0 0x2210000 0x0 0x100>;
2144 clocks = <&k3_clks 253 1>;
2145 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2146 assigned-clocks = <&k3_clks 253 1>;
2147 assigned-clock-parents = <&k3_clks 253 5>;
2148 };
2149
2150 main_r5fss0: r5fss@5c00000 {
2151 compatible = "ti,j721e-r5fss";
2152 ti,cluster-mode = <1>;
2153 #address-cells = <1>;
2154 #size-cells = <1>;
2155 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2156 <0x5d00000 0x00 0x5d00000 0x20000>;
2157 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2158
2159 main_r5fss0_core0: r5f@5c00000 {
2160 compatible = "ti,j721e-r5f";
2161 reg = <0x5c00000 0x00008000>,
2162 <0x5c10000 0x00008000>;
2163 reg-names = "atcm", "btcm";
2164 ti,sci = <&dmsc>;
2165 ti,sci-dev-id = <245>;
2166 ti,sci-proc-ids = <0x06 0xff>;
2167 resets = <&k3_reset 245 1>;
2168 firmware-name = "j7-main-r5f0_0-fw";
2169 ti,atcm-enable = <1>;
2170 ti,btcm-enable = <1>;
2171 ti,loczrama = <1>;
2172 };
2173
2174 main_r5fss0_core1: r5f@5d00000 {
2175 compatible = "ti,j721e-r5f";
2176 reg = <0x5d00000 0x00008000>,
2177 <0x5d10000 0x00008000>;
2178 reg-names = "atcm", "btcm";
2179 ti,sci = <&dmsc>;
2180 ti,sci-dev-id = <246>;
2181 ti,sci-proc-ids = <0x07 0xff>;
2182 resets = <&k3_reset 246 1>;
2183 firmware-name = "j7-main-r5f0_1-fw";
2184 ti,atcm-enable = <1>;
2185 ti,btcm-enable = <1>;
2186 ti,loczrama = <1>;
2187 };
2188 };
2189
2190 main_r5fss1: r5fss@5e00000 {
2191 compatible = "ti,j721e-r5fss";
2192 ti,cluster-mode = <1>;
2193 #address-cells = <1>;
2194 #size-cells = <1>;
2195 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2196 <0x5f00000 0x00 0x5f00000 0x20000>;
2197 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2198
2199 main_r5fss1_core0: r5f@5e00000 {
2200 compatible = "ti,j721e-r5f";
2201 reg = <0x5e00000 0x00008000>,
2202 <0x5e10000 0x00008000>;
2203 reg-names = "atcm", "btcm";
2204 ti,sci = <&dmsc>;
2205 ti,sci-dev-id = <247>;
2206 ti,sci-proc-ids = <0x08 0xff>;
2207 resets = <&k3_reset 247 1>;
2208 firmware-name = "j7-main-r5f1_0-fw";
2209 ti,atcm-enable = <1>;
2210 ti,btcm-enable = <1>;
2211 ti,loczrama = <1>;
2212 };
2213
2214 main_r5fss1_core1: r5f@5f00000 {
2215 compatible = "ti,j721e-r5f";
2216 reg = <0x5f00000 0x00008000>,
2217 <0x5f10000 0x00008000>;
2218 reg-names = "atcm", "btcm";
2219 ti,sci = <&dmsc>;
2220 ti,sci-dev-id = <248>;
2221 ti,sci-proc-ids = <0x09 0xff>;
2222 resets = <&k3_reset 248 1>;
2223 firmware-name = "j7-main-r5f1_1-fw";
2224 ti,atcm-enable = <1>;
2225 ti,btcm-enable = <1>;
2226 ti,loczrama = <1>;
2227 };
2228 };
2229
2230 c66_0: dsp@4d80800000 {
2231 compatible = "ti,j721e-c66-dsp";
2232 reg = <0x4d 0x80800000 0x00 0x00048000>,
2233 <0x4d 0x80e00000 0x00 0x00008000>,
2234 <0x4d 0x80f00000 0x00 0x00008000>;
2235 reg-names = "l2sram", "l1pram", "l1dram";
2236 ti,sci = <&dmsc>;
2237 ti,sci-dev-id = <142>;
2238 ti,sci-proc-ids = <0x03 0xff>;
2239 resets = <&k3_reset 142 1>;
2240 firmware-name = "j7-c66_0-fw";
2241 status = "disabled";
2242 };
2243
2244 c66_1: dsp@4d81800000 {
2245 compatible = "ti,j721e-c66-dsp";
2246 reg = <0x4d 0x81800000 0x00 0x00048000>,
2247 <0x4d 0x81e00000 0x00 0x00008000>,
2248 <0x4d 0x81f00000 0x00 0x00008000>;
2249 reg-names = "l2sram", "l1pram", "l1dram";
2250 ti,sci = <&dmsc>;
2251 ti,sci-dev-id = <143>;
2252 ti,sci-proc-ids = <0x04 0xff>;
2253 resets = <&k3_reset 143 1>;
2254 firmware-name = "j7-c66_1-fw";
2255 status = "disabled";
2256 };
2257
2258 c71_0: dsp@64800000 {
2259 compatible = "ti,j721e-c71-dsp";
2260 reg = <0x00 0x64800000 0x00 0x00080000>,
2261 <0x00 0x64e00000 0x00 0x0000c000>;
2262 reg-names = "l2sram", "l1dram";
2263 ti,sci = <&dmsc>;
2264 ti,sci-dev-id = <15>;
2265 ti,sci-proc-ids = <0x30 0xff>;
2266 resets = <&k3_reset 15 1>;
2267 firmware-name = "j7-c71_0-fw";
2268 status = "disabled";
2269 };
2270
2271 icssg0: icssg@b000000 {
2272 compatible = "ti,j721e-icssg";
2273 reg = <0x00 0xb000000 0x00 0x80000>;
2274 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2275 #address-cells = <1>;
2276 #size-cells = <1>;
2277 ranges = <0x0 0x00 0x0b000000 0x100000>;
2278
2279 icssg0_mem: memories@0 {
2280 reg = <0x0 0x2000>,
2281 <0x2000 0x2000>,
2282 <0x10000 0x10000>;
2283 reg-names = "dram0", "dram1",
2284 "shrdram2";
2285 };
2286
2287 icssg0_cfg: cfg@26000 {
2288 compatible = "ti,pruss-cfg", "syscon";
2289 reg = <0x26000 0x200>;
2290 #address-cells = <1>;
2291 #size-cells = <1>;
2292 ranges = <0x0 0x26000 0x2000>;
2293
2294 clocks {
2295 #address-cells = <1>;
2296 #size-cells = <0>;
2297
2298 icssg0_coreclk_mux: coreclk-mux@3c {
2299 reg = <0x3c>;
2300 #clock-cells = <0>;
2301 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
2302 <&k3_clks 119 1>; /* icssg0_iclk */
2303 assigned-clocks = <&icssg0_coreclk_mux>;
2304 assigned-clock-parents = <&k3_clks 119 1>;
2305 };
2306
2307 icssg0_iepclk_mux: iepclk-mux@30 {
2308 reg = <0x30>;
2309 #clock-cells = <0>;
2310 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
2311 <&icssg0_coreclk_mux>; /* core_clk */
2312 assigned-clocks = <&icssg0_iepclk_mux>;
2313 assigned-clock-parents = <&icssg0_coreclk_mux>;
2314 };
2315 };
2316 };
2317
2318 icssg0_mii_rt: mii-rt@32000 {
2319 compatible = "ti,pruss-mii", "syscon";
2320 reg = <0x32000 0x100>;
2321 };
2322
2323 icssg0_mii_g_rt: mii-g-rt@33000 {
2324 compatible = "ti,pruss-mii-g", "syscon";
2325 reg = <0x33000 0x1000>;
2326 };
2327
2328 icssg0_intc: interrupt-controller@20000 {
2329 compatible = "ti,icssg-intc";
2330 reg = <0x20000 0x2000>;
2331 interrupt-controller;
2332 #interrupt-cells = <3>;
2333 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2334 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2335 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2336 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
2337 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
2338 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
2339 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
2341 interrupt-names = "host_intr0", "host_intr1",
2342 "host_intr2", "host_intr3",
2343 "host_intr4", "host_intr5",
2344 "host_intr6", "host_intr7";
2345 };
2346
2347 pru0_0: pru@34000 {
2348 compatible = "ti,j721e-pru";
2349 reg = <0x34000 0x3000>,
2350 <0x22000 0x100>,
2351 <0x22400 0x100>;
2352 reg-names = "iram", "control", "debug";
2353 firmware-name = "j7-pru0_0-fw";
2354 };
2355
2356 rtu0_0: rtu@4000 {
2357 compatible = "ti,j721e-rtu";
2358 reg = <0x4000 0x2000>,
2359 <0x23000 0x100>,
2360 <0x23400 0x100>;
2361 reg-names = "iram", "control", "debug";
2362 firmware-name = "j7-rtu0_0-fw";
2363 };
2364
2365 tx_pru0_0: txpru@a000 {
2366 compatible = "ti,j721e-tx-pru";
2367 reg = <0xa000 0x1800>,
2368 <0x25000 0x100>,
2369 <0x25400 0x100>;
2370 reg-names = "iram", "control", "debug";
2371 firmware-name = "j7-txpru0_0-fw";
2372 };
2373
2374 pru0_1: pru@38000 {
2375 compatible = "ti,j721e-pru";
2376 reg = <0x38000 0x3000>,
2377 <0x24000 0x100>,
2378 <0x24400 0x100>;
2379 reg-names = "iram", "control", "debug";
2380 firmware-name = "j7-pru0_1-fw";
2381 };
2382
2383 rtu0_1: rtu@6000 {
2384 compatible = "ti,j721e-rtu";
2385 reg = <0x6000 0x2000>,
2386 <0x23800 0x100>,
2387 <0x23c00 0x100>;
2388 reg-names = "iram", "control", "debug";
2389 firmware-name = "j7-rtu0_1-fw";
2390 };
2391
2392 tx_pru0_1: txpru@c000 {
2393 compatible = "ti,j721e-tx-pru";
2394 reg = <0xc000 0x1800>,
2395 <0x25800 0x100>,
2396 <0x25c00 0x100>;
2397 reg-names = "iram", "control", "debug";
2398 firmware-name = "j7-txpru0_1-fw";
2399 };
2400
2401 icssg0_mdio: mdio@32400 {
2402 compatible = "ti,davinci_mdio";
2403 reg = <0x32400 0x100>;
2404 clocks = <&k3_clks 119 1>;
2405 clock-names = "fck";
2406 #address-cells = <1>;
2407 #size-cells = <0>;
2408 bus_freq = <1000000>;
2409 status = "disabled";
2410 };
2411 };
2412
2413 icssg1: icssg@b100000 {
2414 compatible = "ti,j721e-icssg";
2415 reg = <0x00 0xb100000 0x00 0x80000>;
2416 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2417 #address-cells = <1>;
2418 #size-cells = <1>;
2419 ranges = <0x0 0x00 0x0b100000 0x100000>;
2420
2421 icssg1_mem: memories@b100000 {
2422 reg = <0x0 0x2000>,
2423 <0x2000 0x2000>,
2424 <0x10000 0x10000>;
2425 reg-names = "dram0", "dram1",
2426 "shrdram2";
2427 };
2428
2429 icssg1_cfg: cfg@26000 {
2430 compatible = "ti,pruss-cfg", "syscon";
2431 reg = <0x26000 0x200>;
2432 #address-cells = <1>;
2433 #size-cells = <1>;
2434 ranges = <0x0 0x26000 0x2000>;
2435
2436 clocks {
2437 #address-cells = <1>;
2438 #size-cells = <0>;
2439
2440 icssg1_coreclk_mux: coreclk-mux@3c {
2441 reg = <0x3c>;
2442 #clock-cells = <0>;
2443 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
2444 <&k3_clks 120 4>; /* icssg1_iclk */
2445 assigned-clocks = <&icssg1_coreclk_mux>;
2446 assigned-clock-parents = <&k3_clks 120 4>;
2447 };
2448
2449 icssg1_iepclk_mux: iepclk-mux@30 {
2450 reg = <0x30>;
2451 #clock-cells = <0>;
2452 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
2453 <&icssg1_coreclk_mux>; /* core_clk */
2454 assigned-clocks = <&icssg1_iepclk_mux>;
2455 assigned-clock-parents = <&icssg1_coreclk_mux>;
2456 };
2457 };
2458 };
2459
2460 icssg1_mii_rt: mii-rt@32000 {
2461 compatible = "ti,pruss-mii", "syscon";
2462 reg = <0x32000 0x100>;
2463 };
2464
2465 icssg1_mii_g_rt: mii-g-rt@33000 {
2466 compatible = "ti,pruss-mii-g", "syscon";
2467 reg = <0x33000 0x1000>;
2468 };
2469
2470 icssg1_intc: interrupt-controller@20000 {
2471 compatible = "ti,icssg-intc";
2472 reg = <0x20000 0x2000>;
2473 interrupt-controller;
2474 #interrupt-cells = <3>;
2475 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2476 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2477 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2478 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
2479 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2480 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2481 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2482 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2483 interrupt-names = "host_intr0", "host_intr1",
2484 "host_intr2", "host_intr3",
2485 "host_intr4", "host_intr5",
2486 "host_intr6", "host_intr7";
2487 };
2488
2489 pru1_0: pru@34000 {
2490 compatible = "ti,j721e-pru";
2491 reg = <0x34000 0x4000>,
2492 <0x22000 0x100>,
2493 <0x22400 0x100>;
2494 reg-names = "iram", "control", "debug";
2495 firmware-name = "j7-pru1_0-fw";
2496 };
2497
2498 rtu1_0: rtu@4000 {
2499 compatible = "ti,j721e-rtu";
2500 reg = <0x4000 0x2000>,
2501 <0x23000 0x100>,
2502 <0x23400 0x100>;
2503 reg-names = "iram", "control", "debug";
2504 firmware-name = "j7-rtu1_0-fw";
2505 };
2506
2507 tx_pru1_0: txpru@a000 {
2508 compatible = "ti,j721e-tx-pru";
2509 reg = <0xa000 0x1800>,
2510 <0x25000 0x100>,
2511 <0x25400 0x100>;
2512 reg-names = "iram", "control", "debug";
2513 firmware-name = "j7-txpru1_0-fw";
2514 };
2515
2516 pru1_1: pru@38000 {
2517 compatible = "ti,j721e-pru";
2518 reg = <0x38000 0x4000>,
2519 <0x24000 0x100>,
2520 <0x24400 0x100>;
2521 reg-names = "iram", "control", "debug";
2522 firmware-name = "j7-pru1_1-fw";
2523 };
2524
2525 rtu1_1: rtu@6000 {
2526 compatible = "ti,j721e-rtu";
2527 reg = <0x6000 0x2000>,
2528 <0x23800 0x100>,
2529 <0x23c00 0x100>;
2530 reg-names = "iram", "control", "debug";
2531 firmware-name = "j7-rtu1_1-fw";
2532 };
2533
2534 tx_pru1_1: txpru@c000 {
2535 compatible = "ti,j721e-tx-pru";
2536 reg = <0xc000 0x1800>,
2537 <0x25800 0x100>,
2538 <0x25c00 0x100>;
2539 reg-names = "iram", "control", "debug";
2540 firmware-name = "j7-txpru1_1-fw";
2541 };
2542
2543 icssg1_mdio: mdio@32400 {
2544 compatible = "ti,davinci_mdio";
2545 reg = <0x32400 0x100>;
2546 clocks = <&k3_clks 120 4>;
2547 clock-names = "fck";
2548 #address-cells = <1>;
2549 #size-cells = <0>;
2550 bus_freq = <1000000>;
2551 status = "disabled";
2552 };
2553 };
2554
2555 main_mcan0: can@2701000 {
2556 compatible = "bosch,m_can";
2557 reg = <0x00 0x02701000 0x00 0x200>,
2558 <0x00 0x02708000 0x00 0x8000>;
2559 reg-names = "m_can", "message_ram";
2560 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2561 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2562 clock-names = "hclk", "cclk";
2563 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2564 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2565 interrupt-names = "int0", "int1";
2566 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2567 status = "disabled";
2568 };
2569
2570 main_mcan1: can@2711000 {
2571 compatible = "bosch,m_can";
2572 reg = <0x00 0x02711000 0x00 0x200>,
2573 <0x00 0x02718000 0x00 0x8000>;
2574 reg-names = "m_can", "message_ram";
2575 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2576 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2577 clock-names = "hclk", "cclk";
2578 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2579 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
2580 interrupt-names = "int0", "int1";
2581 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2582 status = "disabled";
2583 };
2584
2585 main_mcan2: can@2721000 {
2586 compatible = "bosch,m_can";
2587 reg = <0x00 0x02721000 0x00 0x200>,
2588 <0x00 0x02728000 0x00 0x8000>;
2589 reg-names = "m_can", "message_ram";
2590 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2591 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2592 clock-names = "hclk", "cclk";
2593 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2594 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2595 interrupt-names = "int0", "int1";
2596 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2597 status = "disabled";
2598 };
2599
2600 main_mcan3: can@2731000 {
2601 compatible = "bosch,m_can";
2602 reg = <0x00 0x02731000 0x00 0x200>,
2603 <0x00 0x02738000 0x00 0x8000>;
2604 reg-names = "m_can", "message_ram";
2605 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2606 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2607 clock-names = "hclk", "cclk";
2608 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2609 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2610 interrupt-names = "int0", "int1";
2611 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2612 status = "disabled";
2613 };
2614
2615 main_mcan4: can@2741000 {
2616 compatible = "bosch,m_can";
2617 reg = <0x00 0x02741000 0x00 0x200>,
2618 <0x00 0x02748000 0x00 0x8000>;
2619 reg-names = "m_can", "message_ram";
2620 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2621 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2622 clock-names = "hclk", "cclk";
2623 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2624 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2625 interrupt-names = "int0", "int1";
2626 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2627 status = "disabled";
2628 };
2629
2630 main_mcan5: can@2751000 {
2631 compatible = "bosch,m_can";
2632 reg = <0x00 0x02751000 0x00 0x200>,
2633 <0x00 0x02758000 0x00 0x8000>;
2634 reg-names = "m_can", "message_ram";
2635 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2636 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2637 clock-names = "hclk", "cclk";
2638 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2639 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2640 interrupt-names = "int0", "int1";
2641 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2642 status = "disabled";
2643 };
2644
2645 main_mcan6: can@2761000 {
2646 compatible = "bosch,m_can";
2647 reg = <0x00 0x02761000 0x00 0x200>,
2648 <0x00 0x02768000 0x00 0x8000>;
2649 reg-names = "m_can", "message_ram";
2650 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2651 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2652 clock-names = "hclk", "cclk";
2653 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2654 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
2655 interrupt-names = "int0", "int1";
2656 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2657 status = "disabled";
2658 };
2659
2660 main_mcan7: can@2771000 {
2661 compatible = "bosch,m_can";
2662 reg = <0x00 0x02771000 0x00 0x200>,
2663 <0x00 0x02778000 0x00 0x8000>;
2664 reg-names = "m_can", "message_ram";
2665 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2666 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2667 clock-names = "hclk", "cclk";
2668 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2669 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2670 interrupt-names = "int0", "int1";
2671 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2672 status = "disabled";
2673 };
2674
2675 main_mcan8: can@2781000 {
2676 compatible = "bosch,m_can";
2677 reg = <0x00 0x02781000 0x00 0x200>,
2678 <0x00 0x02788000 0x00 0x8000>;
2679 reg-names = "m_can", "message_ram";
2680 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2681 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2682 clock-names = "hclk", "cclk";
2683 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2684 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
2685 interrupt-names = "int0", "int1";
2686 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2687 status = "disabled";
2688 };
2689
2690 main_mcan9: can@2791000 {
2691 compatible = "bosch,m_can";
2692 reg = <0x00 0x02791000 0x00 0x200>,
2693 <0x00 0x02798000 0x00 0x8000>;
2694 reg-names = "m_can", "message_ram";
2695 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2696 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2697 clock-names = "hclk", "cclk";
2698 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
2699 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2700 interrupt-names = "int0", "int1";
2701 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2702 status = "disabled";
2703 };
2704
2705 main_mcan10: can@27a1000 {
2706 compatible = "bosch,m_can";
2707 reg = <0x00 0x027a1000 0x00 0x200>,
2708 <0x00 0x027a8000 0x00 0x8000>;
2709 reg-names = "m_can", "message_ram";
2710 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2711 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2712 clock-names = "hclk", "cclk";
2713 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
2714 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2715 interrupt-names = "int0", "int1";
2716 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2717 status = "disabled";
2718 };
2719
2720 main_mcan11: can@27b1000 {
2721 compatible = "bosch,m_can";
2722 reg = <0x00 0x027b1000 0x00 0x200>,
2723 <0x00 0x027b8000 0x00 0x8000>;
2724 reg-names = "m_can", "message_ram";
2725 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2726 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2727 clock-names = "hclk", "cclk";
2728 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
2729 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2730 interrupt-names = "int0", "int1";
2731 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2732 status = "disabled";
2733 };
2734
2735 main_mcan12: can@27c1000 {
2736 compatible = "bosch,m_can";
2737 reg = <0x00 0x027c1000 0x00 0x200>,
2738 <0x00 0x027c8000 0x00 0x8000>;
2739 reg-names = "m_can", "message_ram";
2740 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2741 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2742 clock-names = "hclk", "cclk";
2743 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
2744 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
2745 interrupt-names = "int0", "int1";
2746 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2747 status = "disabled";
2748 };
2749
2750 main_mcan13: can@27d1000 {
2751 compatible = "bosch,m_can";
2752 reg = <0x00 0x027d1000 0x00 0x200>,
2753 <0x00 0x027d8000 0x00 0x8000>;
2754 reg-names = "m_can", "message_ram";
2755 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2756 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2757 clock-names = "hclk", "cclk";
2758 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
2759 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
2760 interrupt-names = "int0", "int1";
2761 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2762 status = "disabled";
2763 };
2764
2765 main_spi0: spi@2100000 {
2766 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2767 reg = <0x00 0x02100000 0x00 0x400>;
2768 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2769 #address-cells = <1>;
2770 #size-cells = <0>;
2771 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2772 clocks = <&k3_clks 266 1>;
2773 status = "disabled";
2774 };
2775
2776 main_spi1: spi@2110000 {
2777 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2778 reg = <0x00 0x02110000 0x00 0x400>;
2779 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
2780 #address-cells = <1>;
2781 #size-cells = <0>;
2782 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2783 clocks = <&k3_clks 267 1>;
2784 status = "disabled";
2785 };
2786
2787 main_spi2: spi@2120000 {
2788 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2789 reg = <0x00 0x02120000 0x00 0x400>;
2790 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
2791 #address-cells = <1>;
2792 #size-cells = <0>;
2793 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2794 clocks = <&k3_clks 268 1>;
2795 status = "disabled";
2796 };
2797
2798 main_spi3: spi@2130000 {
2799 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2800 reg = <0x00 0x02130000 0x00 0x400>;
2801 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
2802 #address-cells = <1>;
2803 #size-cells = <0>;
2804 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2805 clocks = <&k3_clks 269 1>;
2806 status = "disabled";
2807 };
2808
2809 main_spi4: spi@2140000 {
2810 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2811 reg = <0x00 0x02140000 0x00 0x400>;
2812 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
2813 #address-cells = <1>;
2814 #size-cells = <0>;
2815 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2816 clocks = <&k3_clks 270 1>;
2817 status = "disabled";
2818 };
2819
2820 main_spi5: spi@2150000 {
2821 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2822 reg = <0x00 0x02150000 0x00 0x400>;
2823 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2824 #address-cells = <1>;
2825 #size-cells = <0>;
2826 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2827 clocks = <&k3_clks 271 1>;
2828 status = "disabled";
2829 };
2830
2831 main_spi6: spi@2160000 {
2832 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2833 reg = <0x00 0x02160000 0x00 0x400>;
2834 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
2835 #address-cells = <1>;
2836 #size-cells = <0>;
2837 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2838 clocks = <&k3_clks 272 1>;
2839 status = "disabled";
2840 };
2841
2842 main_spi7: spi@2170000 {
2843 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2844 reg = <0x00 0x02170000 0x00 0x400>;
2845 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
2846 #address-cells = <1>;
2847 #size-cells = <0>;
2848 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2849 clocks = <&k3_clks 273 1>;
2850 status = "disabled";
2851 };
2852
2853 main_esm: esm@700000 {
2854 compatible = "ti,j721e-esm";
2855 reg = <0x0 0x700000 0x0 0x1000>;
2856 ti,esm-pins = <344>, <345>;
2857 };
2858 };
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