1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /**
3 * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
4 *
5 * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
6 *
7 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 */
9
10 /dts-v1/;
11 /plugin/;
12
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/net/ti-dp83867.h>
15
16 #include "k3-pinctrl.h"
17
18 &{/} {
19 aliases {
20 ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
21 };
22 };
23
24 &main_pmx0 {
25 main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins {
26 pinctrl-single,pins = <
27 J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
28 J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
29 >;
30 };
31
32 rgmii1_default_pins: rgmii1-default-pins {
33 pinctrl-single,pins = <
34 J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
35 J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
36 J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
37 J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
38 J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
39 J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
40 J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
41 J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
42 J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
43 J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
44 J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
45 J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
46 >;
47 };
48 };
49
50 &exp1 {
51 p15-hog {
52 /* P15 - EXP_MUX2 */
53 gpio-hog;
54 gpios = <13 GPIO_ACTIVE_HIGH>;
55 output-high;
56 line-name = "EXP_MUX2";
57 };
58 };
59
60 &main_cpsw {
61 status = "okay";
62 pinctrl-names = "default";
63 pinctrl-0 = <&rgmii1_default_pins>;
64 };
65
66 &main_cpsw_mdio {
67 status = "okay";
68 pinctrl-names = "default";
69 pinctrl-0 = <&main_cpsw_mdio_default_pins>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 main_cpsw_phy0: ethernet-phy@0 {
74 reg = <0>;
75 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
76 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
77 ti,min-output-impedance;
78 };
79 };
80
81 &main_cpsw_port1 {
82 status = "okay";
83 phy-mode = "rgmii-rxid";
84 phy-handle = <&main_cpsw_phy0>;
85 };
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