1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
10
11 / {
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
16 };
17 };
18
19 &cbass_main {
20 msmc_ram: sram@70000000 {
21 compatible = "mmio-sram";
22 reg = <0x0 0x70000000 0x0 0x400000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
26
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
29 };
30
31 tifs-sram@1f0000 {
32 reg = <0x1f0000 0x10000>;
33 };
34
35 l3cache-sram@200000 {
36 reg = <0x200000 0x200000>;
37 };
38 };
39
40 scm_conf: syscon@104000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 reg = <0x00 0x00104000 0x00 0x18000>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
46
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "reg-mux";
49 reg = <0x0 0x4>;
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
52 };
53
54 phy_gmii_sel_cpsw: phy@34 {
55 compatible = "ti,am654-phy-gmii-sel";
56 reg = <0x34 0x4>;
57 #phy-cells = <1>;
58 };
59
60 serdes_ln_ctrl: mux-controller@80 {
61 compatible = "reg-mux";
62 reg = <0x80 0x10>;
63 #mux-control-cells = <1>;
64 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
65 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
66 };
67
68 ehrpwm_tbclk: clock-controller@140 {
69 compatible = "ti,am654-ehrpwm-tbclk";
70 reg = <0x140 0x18>;
71 #clock-cells = <1>;
72 };
73 };
74
75 main_ehrpwm0: pwm@3000000 {
76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
77 #pwm-cells = <3>;
78 reg = <0x00 0x3000000 0x00 0x100>;
79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
80 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
81 clock-names = "tbclk", "fck";
82 status = "disabled";
83 };
84
85 main_ehrpwm1: pwm@3010000 {
86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
87 #pwm-cells = <3>;
88 reg = <0x00 0x3010000 0x00 0x100>;
89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
90 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
91 clock-names = "tbclk", "fck";
92 status = "disabled";
93 };
94
95 main_ehrpwm2: pwm@3020000 {
96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
97 #pwm-cells = <3>;
98 reg = <0x00 0x3020000 0x00 0x100>;
99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
101 clock-names = "tbclk", "fck";
102 status = "disabled";
103 };
104
105 main_ehrpwm3: pwm@3030000 {
106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
107 #pwm-cells = <3>;
108 reg = <0x00 0x3030000 0x00 0x100>;
109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
110 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
111 clock-names = "tbclk", "fck";
112 status = "disabled";
113 };
114
115 main_ehrpwm4: pwm@3040000 {
116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
117 #pwm-cells = <3>;
118 reg = <0x00 0x3040000 0x00 0x100>;
119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
120 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
121 clock-names = "tbclk", "fck";
122 status = "disabled";
123 };
124
125 main_ehrpwm5: pwm@3050000 {
126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
127 #pwm-cells = <3>;
128 reg = <0x00 0x3050000 0x00 0x100>;
129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
130 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
131 clock-names = "tbclk", "fck";
132 status = "disabled";
133 };
134
135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
139 ranges;
140 #interrupt-cells = <3>;
141 interrupt-controller;
142 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
143 <0x00 0x01900000 0x00 0x100000>, /* GICR */
144 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
145 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
146 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
147
148 /* vcpumntirq: virtual CPU interface maintenance interrupt */
149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
150
151 gic_its: msi-controller@1820000 {
152 compatible = "arm,gic-v3-its";
153 reg = <0x00 0x01820000 0x00 0x10000>;
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
155 msi-controller;
156 #msi-cells = <1>;
157 };
158 };
159
160 main_gpio_intr: interrupt-controller@a00000 {
161 compatible = "ti,sci-intr";
162 reg = <0x00 0x00a00000 0x00 0x800>;
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
167 ti,sci = <&sms>;
168 ti,sci-dev-id = <148>;
169 ti,interrupt-ranges = <8 392 56>;
170 };
171
172 main_pmx0: pinctrl@11c000 {
173 compatible = "pinctrl-single";
174 /* Proxy 0 addressing */
175 reg = <0x0 0x11c000 0x0 0x120>;
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <0xffffffff>;
179 };
180
181 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
182 main_timerio_input: pinctrl@104200 {
183 compatible = "pinctrl-single";
184 reg = <0x00 0x104200 0x00 0x50>;
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width = <32>;
187 pinctrl-single,function-mask = <0x00000007>;
188 };
189
190 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
191 main_timerio_output: pinctrl@104280 {
192 compatible = "pinctrl-single";
193 reg = <0x00 0x104280 0x00 0x20>;
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0x0000001f>;
197 };
198
199 main_crypto: crypto@4e00000 {
200 compatible = "ti,j721e-sa2ul";
201 reg = <0x00 0x04e00000 0x00 0x1200>;
202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
203 #address-cells = <2>;
204 #size-cells = <2>;
205 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
206
207 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
208 <&main_udmap 0x4a41>;
209 dma-names = "tx", "rx1", "rx2";
210
211 rng: rng@4e10000 {
212 compatible = "inside-secure,safexcel-eip76";
213 reg = <0x00 0x04e10000 0x00 0x7d>;
214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
215 };
216 };
217
218 main_timer0: timer@2400000 {
219 compatible = "ti,am654-timer";
220 reg = <0x00 0x2400000 0x00 0x400>;
221 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&k3_clks 63 1>;
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63 1>;
225 assigned-clock-parents = <&k3_clks 63 2>;
226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
227 ti,timer-pwm;
228 };
229
230 main_timer1: timer@2410000 {
231 compatible = "ti,am654-timer";
232 reg = <0x00 0x2410000 0x00 0x400>;
233 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&k3_clks 64 1>;
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64 1>;
237 assigned-clock-parents = <&k3_clks 64 2>;
238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
239 ti,timer-pwm;
240 };
241
242 main_timer2: timer@2420000 {
243 compatible = "ti,am654-timer";
244 reg = <0x00 0x2420000 0x00 0x400>;
245 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&k3_clks 65 1>;
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65 1>;
249 assigned-clock-parents = <&k3_clks 65 2>;
250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
251 ti,timer-pwm;
252 };
253
254 main_timer3: timer@2430000 {
255 compatible = "ti,am654-timer";
256 reg = <0x00 0x2430000 0x00 0x400>;
257 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&k3_clks 66 1>;
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66 1>;
261 assigned-clock-parents = <&k3_clks 66 2>;
262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
263 ti,timer-pwm;
264 };
265
266 main_timer4: timer@2440000 {
267 compatible = "ti,am654-timer";
268 reg = <0x00 0x2440000 0x00 0x400>;
269 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&k3_clks 67 1>;
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67 1>;
273 assigned-clock-parents = <&k3_clks 67 2>;
274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
276 };
277
278 main_timer5: timer@2450000 {
279 compatible = "ti,am654-timer";
280 reg = <0x00 0x2450000 0x00 0x400>;
281 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&k3_clks 68 1>;
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68 1>;
285 assigned-clock-parents = <&k3_clks 68 2>;
286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
287 ti,timer-pwm;
288 };
289
290 main_timer6: timer@2460000 {
291 compatible = "ti,am654-timer";
292 reg = <0x00 0x2460000 0x00 0x400>;
293 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&k3_clks 69 1>;
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69 1>;
297 assigned-clock-parents = <&k3_clks 69 2>;
298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
299 ti,timer-pwm;
300 };
301
302 main_timer7: timer@2470000 {
303 compatible = "ti,am654-timer";
304 reg = <0x00 0x2470000 0x00 0x400>;
305 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&k3_clks 70 1>;
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70 1>;
309 assigned-clock-parents = <&k3_clks 70 2>;
310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
311 ti,timer-pwm;
312 };
313
314 main_timer8: timer@2480000 {
315 compatible = "ti,am654-timer";
316 reg = <0x00 0x2480000 0x00 0x400>;
317 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&k3_clks 71 1>;
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71 1>;
321 assigned-clock-parents = <&k3_clks 71 2>;
322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
323 ti,timer-pwm;
324 };
325
326 main_timer9: timer@2490000 {
327 compatible = "ti,am654-timer";
328 reg = <0x00 0x2490000 0x00 0x400>;
329 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&k3_clks 72 1>;
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72 1>;
333 assigned-clock-parents = <&k3_clks 72 2>;
334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
335 ti,timer-pwm;
336 };
337
338 main_timer10: timer@24a0000 {
339 compatible = "ti,am654-timer";
340 reg = <0x00 0x24a0000 0x00 0x400>;
341 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&k3_clks 73 1>;
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73 1>;
345 assigned-clock-parents = <&k3_clks 73 2>;
346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
347 ti,timer-pwm;
348 };
349
350 main_timer11: timer@24b0000 {
351 compatible = "ti,am654-timer";
352 reg = <0x00 0x24b0000 0x00 0x400>;
353 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&k3_clks 74 1>;
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74 1>;
357 assigned-clock-parents = <&k3_clks 74 2>;
358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
359 ti,timer-pwm;
360 };
361
362 main_timer12: timer@24c0000 {
363 compatible = "ti,am654-timer";
364 reg = <0x00 0x24c0000 0x00 0x400>;
365 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&k3_clks 75 1>;
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75 1>;
369 assigned-clock-parents = <&k3_clks 75 2>;
370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
371 ti,timer-pwm;
372 };
373
374 main_timer13: timer@24d0000 {
375 compatible = "ti,am654-timer";
376 reg = <0x00 0x24d0000 0x00 0x400>;
377 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&k3_clks 76 1>;
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76 1>;
381 assigned-clock-parents = <&k3_clks 76 2>;
382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
383 ti,timer-pwm;
384 };
385
386 main_timer14: timer@24e0000 {
387 compatible = "ti,am654-timer";
388 reg = <0x00 0x24e0000 0x00 0x400>;
389 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&k3_clks 77 1>;
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77 1>;
393 assigned-clock-parents = <&k3_clks 77 2>;
394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
395 ti,timer-pwm;
396 };
397
398 main_timer15: timer@24f0000 {
399 compatible = "ti,am654-timer";
400 reg = <0x00 0x24f0000 0x00 0x400>;
401 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&k3_clks 78 1>;
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78 1>;
405 assigned-clock-parents = <&k3_clks 78 2>;
406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
407 ti,timer-pwm;
408 };
409
410 main_timer16: timer@2500000 {
411 compatible = "ti,am654-timer";
412 reg = <0x00 0x2500000 0x00 0x400>;
413 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&k3_clks 79 1>;
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79 1>;
417 assigned-clock-parents = <&k3_clks 79 2>;
418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
419 ti,timer-pwm;
420 };
421
422 main_timer17: timer@2510000 {
423 compatible = "ti,am654-timer";
424 reg = <0x00 0x2510000 0x00 0x400>;
425 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&k3_clks 80 1>;
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80 1>;
429 assigned-clock-parents = <&k3_clks 80 2>;
430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
431 ti,timer-pwm;
432 };
433
434 main_timer18: timer@2520000 {
435 compatible = "ti,am654-timer";
436 reg = <0x00 0x2520000 0x00 0x400>;
437 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&k3_clks 81 1>;
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81 1>;
441 assigned-clock-parents = <&k3_clks 81 2>;
442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
443 ti,timer-pwm;
444 };
445
446 main_timer19: timer@2530000 {
447 compatible = "ti,am654-timer";
448 reg = <0x00 0x2530000 0x00 0x400>;
449 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&k3_clks 82 1>;
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82 1>;
453 assigned-clock-parents = <&k3_clks 82 2>;
454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
455 ti,timer-pwm;
456 };
457
458 main_uart0: serial@2800000 {
459 compatible = "ti,j721e-uart", "ti,am654-uart";
460 reg = <0x00 0x02800000 0x00 0x200>;
461 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&k3_clks 146 3>;
463 clock-names = "fclk";
464 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
465 status = "disabled";
466 };
467
468 main_uart1: serial@2810000 {
469 compatible = "ti,j721e-uart", "ti,am654-uart";
470 reg = <0x00 0x02810000 0x00 0x200>;
471 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&k3_clks 350 3>;
473 clock-names = "fclk";
474 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
475 status = "disabled";
476 };
477
478 main_uart2: serial@2820000 {
479 compatible = "ti,j721e-uart", "ti,am654-uart";
480 reg = <0x00 0x02820000 0x00 0x200>;
481 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&k3_clks 351 3>;
483 clock-names = "fclk";
484 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
485 status = "disabled";
486 };
487
488 main_uart3: serial@2830000 {
489 compatible = "ti,j721e-uart", "ti,am654-uart";
490 reg = <0x00 0x02830000 0x00 0x200>;
491 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&k3_clks 352 3>;
493 clock-names = "fclk";
494 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
495 status = "disabled";
496 };
497
498 main_uart4: serial@2840000 {
499 compatible = "ti,j721e-uart", "ti,am654-uart";
500 reg = <0x00 0x02840000 0x00 0x200>;
501 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&k3_clks 353 3>;
503 clock-names = "fclk";
504 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
505 status = "disabled";
506 };
507
508 main_uart5: serial@2850000 {
509 compatible = "ti,j721e-uart", "ti,am654-uart";
510 reg = <0x00 0x02850000 0x00 0x200>;
511 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&k3_clks 354 3>;
513 clock-names = "fclk";
514 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
515 status = "disabled";
516 };
517
518 main_uart6: serial@2860000 {
519 compatible = "ti,j721e-uart", "ti,am654-uart";
520 reg = <0x00 0x02860000 0x00 0x200>;
521 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&k3_clks 355 3>;
523 clock-names = "fclk";
524 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
525 status = "disabled";
526 };
527
528 main_uart7: serial@2870000 {
529 compatible = "ti,j721e-uart", "ti,am654-uart";
530 reg = <0x00 0x02870000 0x00 0x200>;
531 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&k3_clks 356 3>;
533 clock-names = "fclk";
534 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
535 status = "disabled";
536 };
537
538 main_uart8: serial@2880000 {
539 compatible = "ti,j721e-uart", "ti,am654-uart";
540 reg = <0x00 0x02880000 0x00 0x200>;
541 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&k3_clks 357 3>;
543 clock-names = "fclk";
544 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
545 status = "disabled";
546 };
547
548 main_uart9: serial@2890000 {
549 compatible = "ti,j721e-uart", "ti,am654-uart";
550 reg = <0x00 0x02890000 0x00 0x200>;
551 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&k3_clks 358 3>;
553 clock-names = "fclk";
554 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
555 status = "disabled";
556 };
557
558 main_gpio0: gpio@600000 {
559 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
560 reg = <0x00 0x00600000 0x00 0x100>;
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-parent = <&main_gpio_intr>;
564 interrupts = <145>, <146>, <147>, <148>, <149>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
567 ti,ngpio = <66>;
568 ti,davinci-gpio-unbanked = <0>;
569 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
570 clocks = <&k3_clks 111 0>;
571 clock-names = "gpio";
572 status = "disabled";
573 };
574
575 main_gpio2: gpio@610000 {
576 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
577 reg = <0x00 0x00610000 0x00 0x100>;
578 gpio-controller;
579 #gpio-cells = <2>;
580 interrupt-parent = <&main_gpio_intr>;
581 interrupts = <154>, <155>, <156>, <157>, <158>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
584 ti,ngpio = <66>;
585 ti,davinci-gpio-unbanked = <0>;
586 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
587 clocks = <&k3_clks 112 0>;
588 clock-names = "gpio";
589 status = "disabled";
590 };
591
592 main_gpio4: gpio@620000 {
593 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
594 reg = <0x00 0x00620000 0x00 0x100>;
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-parent = <&main_gpio_intr>;
598 interrupts = <163>, <164>, <165>, <166>, <167>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
601 ti,ngpio = <66>;
602 ti,davinci-gpio-unbanked = <0>;
603 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
604 clocks = <&k3_clks 113 0>;
605 clock-names = "gpio";
606 status = "disabled";
607 };
608
609 main_gpio6: gpio@630000 {
610 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
611 reg = <0x00 0x00630000 0x00 0x100>;
612 gpio-controller;
613 #gpio-cells = <2>;
614 interrupt-parent = <&main_gpio_intr>;
615 interrupts = <172>, <173>, <174>, <175>, <176>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
618 ti,ngpio = <66>;
619 ti,davinci-gpio-unbanked = <0>;
620 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
621 clocks = <&k3_clks 114 0>;
622 clock-names = "gpio";
623 status = "disabled";
624 };
625
626 main_i2c0: i2c@2000000 {
627 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
628 reg = <0x00 0x02000000 0x00 0x100>;
629 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
630 #address-cells = <1>;
631 #size-cells = <0>;
632 clocks = <&k3_clks 214 1>;
633 clock-names = "fck";
634 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
635 };
636
637 main_i2c1: i2c@2010000 {
638 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
639 reg = <0x00 0x02010000 0x00 0x100>;
640 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 clocks = <&k3_clks 215 1>;
644 clock-names = "fck";
645 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
646 status = "disabled";
647 };
648
649 main_i2c2: i2c@2020000 {
650 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
651 reg = <0x00 0x02020000 0x00 0x100>;
652 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
653 #address-cells = <1>;
654 #size-cells = <0>;
655 clocks = <&k3_clks 216 1>;
656 clock-names = "fck";
657 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
658 status = "disabled";
659 };
660
661 main_i2c3: i2c@2030000 {
662 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
663 reg = <0x00 0x02030000 0x00 0x100>;
664 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
665 #address-cells = <1>;
666 #size-cells = <0>;
667 clocks = <&k3_clks 217 1>;
668 clock-names = "fck";
669 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
670 status = "disabled";
671 };
672
673 main_i2c4: i2c@2040000 {
674 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
675 reg = <0x00 0x02040000 0x00 0x100>;
676 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>;
678 #size-cells = <0>;
679 clocks = <&k3_clks 218 1>;
680 clock-names = "fck";
681 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
682 status = "disabled";
683 };
684
685 main_i2c5: i2c@2050000 {
686 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
687 reg = <0x00 0x02050000 0x00 0x100>;
688 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
689 #address-cells = <1>;
690 #size-cells = <0>;
691 clocks = <&k3_clks 219 1>;
692 clock-names = "fck";
693 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
694 status = "disabled";
695 };
696
697 main_i2c6: i2c@2060000 {
698 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
699 reg = <0x00 0x02060000 0x00 0x100>;
700 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
701 #address-cells = <1>;
702 #size-cells = <0>;
703 clocks = <&k3_clks 220 1>;
704 clock-names = "fck";
705 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
706 status = "disabled";
707 };
708
709 vpu: video-codec@4210000 {
710 compatible = "ti,j721s2-wave521c", "cnm,wave521c";
711 reg = <0x00 0x4210000 0x00 0x10000>;
712 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&k3_clks 179 2>;
714 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
715 };
716
717 main_sdhci0: mmc@4f80000 {
718 compatible = "ti,j721e-sdhci-8bit";
719 reg = <0x00 0x04f80000 0x00 0x1000>,
720 <0x00 0x04f88000 0x00 0x400>;
721 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
722 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
723 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
724 clock-names = "clk_ahb", "clk_xin";
725 assigned-clocks = <&k3_clks 98 1>;
726 assigned-clock-parents = <&k3_clks 98 2>;
727 bus-width = <8>;
728 ti,otap-del-sel-legacy = <0x0>;
729 ti,otap-del-sel-mmc-hs = <0x0>;
730 ti,otap-del-sel-ddr52 = <0x6>;
731 ti,otap-del-sel-hs200 = <0x8>;
732 ti,otap-del-sel-hs400 = <0x5>;
733 ti,itap-del-sel-legacy = <0x10>;
734 ti,itap-del-sel-mmc-hs = <0xa>;
735 ti,strobe-sel = <0x77>;
736 ti,clkbuf-sel = <0x7>;
737 ti,trm-icp = <0x8>;
738 mmc-ddr-1_8v;
739 mmc-hs200-1_8v;
740 mmc-hs400-1_8v;
741 dma-coherent;
742 status = "disabled";
743 };
744
745 main_sdhci1: mmc@4fb0000 {
746 compatible = "ti,j721e-sdhci-4bit";
747 reg = <0x00 0x04fb0000 0x00 0x1000>,
748 <0x00 0x04fb8000 0x00 0x400>;
749 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
750 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
751 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
752 clock-names = "clk_ahb", "clk_xin";
753 assigned-clocks = <&k3_clks 99 1>;
754 assigned-clock-parents = <&k3_clks 99 2>;
755 bus-width = <4>;
756 ti,otap-del-sel-legacy = <0x0>;
757 ti,otap-del-sel-sd-hs = <0x0>;
758 ti,otap-del-sel-sdr12 = <0xf>;
759 ti,otap-del-sel-sdr25 = <0xf>;
760 ti,otap-del-sel-sdr50 = <0xc>;
761 ti,otap-del-sel-sdr104 = <0x5>;
762 ti,otap-del-sel-ddr50 = <0xc>;
763 ti,itap-del-sel-legacy = <0x0>;
764 ti,itap-del-sel-sd-hs = <0x0>;
765 ti,itap-del-sel-sdr12 = <0x0>;
766 ti,itap-del-sel-sdr25 = <0x0>;
767 ti,itap-del-sel-ddr50 = <0x2>;
768 ti,clkbuf-sel = <0x7>;
769 ti,trm-icp = <0x8>;
770 dma-coherent;
771 status = "disabled";
772 };
773
774 main_navss: bus@30000000 {
775 compatible = "simple-bus";
776 #address-cells = <2>;
777 #size-cells = <2>;
778 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
779 ti,sci-dev-id = <224>;
780 dma-coherent;
781 dma-ranges;
782
783 main_navss_intr: interrupt-controller@310e0000 {
784 compatible = "ti,sci-intr";
785 reg = <0x00 0x310e0000 0x00 0x4000>;
786 ti,intr-trigger-type = <4>;
787 interrupt-controller;
788 interrupt-parent = <&gic500>;
789 #interrupt-cells = <1>;
790 ti,sci = <&sms>;
791 ti,sci-dev-id = <227>;
792 ti,interrupt-ranges = <0 64 64>,
793 <64 448 64>,
794 <128 672 64>;
795 };
796
797 main_udmass_inta: msi-controller@33d00000 {
798 compatible = "ti,sci-inta";
799 reg = <0x00 0x33d00000 0x00 0x100000>;
800 interrupt-controller;
801 #interrupt-cells = <0>;
802 interrupt-parent = <&main_navss_intr>;
803 msi-controller;
804 ti,sci = <&sms>;
805 ti,sci-dev-id = <265>;
806 ti,interrupt-ranges = <0 0 256>;
807 ti,unmapped-event-sources = <&main_bcdma_csi>;
808 };
809
810 secure_proxy_main: mailbox@32c00000 {
811 compatible = "ti,am654-secure-proxy";
812 #mbox-cells = <1>;
813 reg-names = "target_data", "rt", "scfg";
814 reg = <0x00 0x32c00000 0x00 0x100000>,
815 <0x00 0x32400000 0x00 0x100000>,
816 <0x00 0x32800000 0x00 0x100000>;
817 interrupt-names = "rx_011";
818 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
819 };
820
821 hwspinlock: spinlock@30e00000 {
822 compatible = "ti,am654-hwspinlock";
823 reg = <0x00 0x30e00000 0x00 0x1000>;
824 #hwlock-cells = <1>;
825 };
826
827 mailbox0_cluster0: mailbox@31f80000 {
828 compatible = "ti,am654-mailbox";
829 reg = <0x00 0x31f80000 0x00 0x200>;
830 #mbox-cells = <1>;
831 ti,mbox-num-users = <4>;
832 ti,mbox-num-fifos = <16>;
833 interrupt-parent = <&main_navss_intr>;
834 status = "disabled";
835 };
836
837 mailbox0_cluster1: mailbox@31f81000 {
838 compatible = "ti,am654-mailbox";
839 reg = <0x00 0x31f81000 0x00 0x200>;
840 #mbox-cells = <1>;
841 ti,mbox-num-users = <4>;
842 ti,mbox-num-fifos = <16>;
843 interrupt-parent = <&main_navss_intr>;
844 status = "disabled";
845 };
846
847 mailbox0_cluster2: mailbox@31f82000 {
848 compatible = "ti,am654-mailbox";
849 reg = <0x00 0x31f82000 0x00 0x200>;
850 #mbox-cells = <1>;
851 ti,mbox-num-users = <4>;
852 ti,mbox-num-fifos = <16>;
853 interrupt-parent = <&main_navss_intr>;
854 status = "disabled";
855 };
856
857 mailbox0_cluster3: mailbox@31f83000 {
858 compatible = "ti,am654-mailbox";
859 reg = <0x00 0x31f83000 0x00 0x200>;
860 #mbox-cells = <1>;
861 ti,mbox-num-users = <4>;
862 ti,mbox-num-fifos = <16>;
863 interrupt-parent = <&main_navss_intr>;
864 status = "disabled";
865 };
866
867 mailbox0_cluster4: mailbox@31f84000 {
868 compatible = "ti,am654-mailbox";
869 reg = <0x00 0x31f84000 0x00 0x200>;
870 #mbox-cells = <1>;
871 ti,mbox-num-users = <4>;
872 ti,mbox-num-fifos = <16>;
873 interrupt-parent = <&main_navss_intr>;
874 status = "disabled";
875 };
876
877 mailbox0_cluster5: mailbox@31f85000 {
878 compatible = "ti,am654-mailbox";
879 reg = <0x00 0x31f85000 0x00 0x200>;
880 #mbox-cells = <1>;
881 ti,mbox-num-users = <4>;
882 ti,mbox-num-fifos = <16>;
883 interrupt-parent = <&main_navss_intr>;
884 status = "disabled";
885 };
886
887 mailbox0_cluster6: mailbox@31f86000 {
888 compatible = "ti,am654-mailbox";
889 reg = <0x00 0x31f86000 0x00 0x200>;
890 #mbox-cells = <1>;
891 ti,mbox-num-users = <4>;
892 ti,mbox-num-fifos = <16>;
893 interrupt-parent = <&main_navss_intr>;
894 status = "disabled";
895 };
896
897 mailbox0_cluster7: mailbox@31f87000 {
898 compatible = "ti,am654-mailbox";
899 reg = <0x00 0x31f87000 0x00 0x200>;
900 #mbox-cells = <1>;
901 ti,mbox-num-users = <4>;
902 ti,mbox-num-fifos = <16>;
903 interrupt-parent = <&main_navss_intr>;
904 status = "disabled";
905 };
906
907 mailbox0_cluster8: mailbox@31f88000 {
908 compatible = "ti,am654-mailbox";
909 reg = <0x00 0x31f88000 0x00 0x200>;
910 #mbox-cells = <1>;
911 ti,mbox-num-users = <4>;
912 ti,mbox-num-fifos = <16>;
913 interrupt-parent = <&main_navss_intr>;
914 status = "disabled";
915 };
916
917 mailbox0_cluster9: mailbox@31f89000 {
918 compatible = "ti,am654-mailbox";
919 reg = <0x00 0x31f89000 0x00 0x200>;
920 #mbox-cells = <1>;
921 ti,mbox-num-users = <4>;
922 ti,mbox-num-fifos = <16>;
923 interrupt-parent = <&main_navss_intr>;
924 status = "disabled";
925 };
926
927 mailbox0_cluster10: mailbox@31f8a000 {
928 compatible = "ti,am654-mailbox";
929 reg = <0x00 0x31f8a000 0x00 0x200>;
930 #mbox-cells = <1>;
931 ti,mbox-num-users = <4>;
932 ti,mbox-num-fifos = <16>;
933 interrupt-parent = <&main_navss_intr>;
934 status = "disabled";
935 };
936
937 mailbox0_cluster11: mailbox@31f8b000 {
938 compatible = "ti,am654-mailbox";
939 reg = <0x00 0x31f8b000 0x00 0x200>;
940 #mbox-cells = <1>;
941 ti,mbox-num-users = <4>;
942 ti,mbox-num-fifos = <16>;
943 interrupt-parent = <&main_navss_intr>;
944 status = "disabled";
945 };
946
947 mailbox1_cluster0: mailbox@31f90000 {
948 compatible = "ti,am654-mailbox";
949 reg = <0x00 0x31f90000 0x00 0x200>;
950 #mbox-cells = <1>;
951 ti,mbox-num-users = <4>;
952 ti,mbox-num-fifos = <16>;
953 interrupt-parent = <&main_navss_intr>;
954 status = "disabled";
955 };
956
957 mailbox1_cluster1: mailbox@31f91000 {
958 compatible = "ti,am654-mailbox";
959 reg = <0x00 0x31f91000 0x00 0x200>;
960 #mbox-cells = <1>;
961 ti,mbox-num-users = <4>;
962 ti,mbox-num-fifos = <16>;
963 interrupt-parent = <&main_navss_intr>;
964 status = "disabled";
965 };
966
967 mailbox1_cluster2: mailbox@31f92000 {
968 compatible = "ti,am654-mailbox";
969 reg = <0x00 0x31f92000 0x00 0x200>;
970 #mbox-cells = <1>;
971 ti,mbox-num-users = <4>;
972 ti,mbox-num-fifos = <16>;
973 interrupt-parent = <&main_navss_intr>;
974 status = "disabled";
975 };
976
977 mailbox1_cluster3: mailbox@31f93000 {
978 compatible = "ti,am654-mailbox";
979 reg = <0x00 0x31f93000 0x00 0x200>;
980 #mbox-cells = <1>;
981 ti,mbox-num-users = <4>;
982 ti,mbox-num-fifos = <16>;
983 interrupt-parent = <&main_navss_intr>;
984 status = "disabled";
985 };
986
987 mailbox1_cluster4: mailbox@31f94000 {
988 compatible = "ti,am654-mailbox";
989 reg = <0x00 0x31f94000 0x00 0x200>;
990 #mbox-cells = <1>;
991 ti,mbox-num-users = <4>;
992 ti,mbox-num-fifos = <16>;
993 interrupt-parent = <&main_navss_intr>;
994 status = "disabled";
995 };
996
997 mailbox1_cluster5: mailbox@31f95000 {
998 compatible = "ti,am654-mailbox";
999 reg = <0x00 0x31f95000 0x00 0x200>;
1000 #mbox-cells = <1>;
1001 ti,mbox-num-users = <4>;
1002 ti,mbox-num-fifos = <16>;
1003 interrupt-parent = <&main_navss_intr>;
1004 status = "disabled";
1005 };
1006
1007 mailbox1_cluster6: mailbox@31f96000 {
1008 compatible = "ti,am654-mailbox";
1009 reg = <0x00 0x31f96000 0x00 0x200>;
1010 #mbox-cells = <1>;
1011 ti,mbox-num-users = <4>;
1012 ti,mbox-num-fifos = <16>;
1013 interrupt-parent = <&main_navss_intr>;
1014 status = "disabled";
1015 };
1016
1017 mailbox1_cluster7: mailbox@31f97000 {
1018 compatible = "ti,am654-mailbox";
1019 reg = <0x00 0x31f97000 0x00 0x200>;
1020 #mbox-cells = <1>;
1021 ti,mbox-num-users = <4>;
1022 ti,mbox-num-fifos = <16>;
1023 interrupt-parent = <&main_navss_intr>;
1024 status = "disabled";
1025 };
1026
1027 mailbox1_cluster8: mailbox@31f98000 {
1028 compatible = "ti,am654-mailbox";
1029 reg = <0x00 0x31f98000 0x00 0x200>;
1030 #mbox-cells = <1>;
1031 ti,mbox-num-users = <4>;
1032 ti,mbox-num-fifos = <16>;
1033 interrupt-parent = <&main_navss_intr>;
1034 status = "disabled";
1035 };
1036
1037 mailbox1_cluster9: mailbox@31f99000 {
1038 compatible = "ti,am654-mailbox";
1039 reg = <0x00 0x31f99000 0x00 0x200>;
1040 #mbox-cells = <1>;
1041 ti,mbox-num-users = <4>;
1042 ti,mbox-num-fifos = <16>;
1043 interrupt-parent = <&main_navss_intr>;
1044 status = "disabled";
1045 };
1046
1047 mailbox1_cluster10: mailbox@31f9a000 {
1048 compatible = "ti,am654-mailbox";
1049 reg = <0x00 0x31f9a000 0x00 0x200>;
1050 #mbox-cells = <1>;
1051 ti,mbox-num-users = <4>;
1052 ti,mbox-num-fifos = <16>;
1053 interrupt-parent = <&main_navss_intr>;
1054 status = "disabled";
1055 };
1056
1057 mailbox1_cluster11: mailbox@31f9b000 {
1058 compatible = "ti,am654-mailbox";
1059 reg = <0x00 0x31f9b000 0x00 0x200>;
1060 #mbox-cells = <1>;
1061 ti,mbox-num-users = <4>;
1062 ti,mbox-num-fifos = <16>;
1063 interrupt-parent = <&main_navss_intr>;
1064 status = "disabled";
1065 };
1066
1067 main_ringacc: ringacc@3c000000 {
1068 compatible = "ti,am654-navss-ringacc";
1069 reg = <0x0 0x3c000000 0x0 0x400000>,
1070 <0x0 0x38000000 0x0 0x400000>,
1071 <0x0 0x31120000 0x0 0x100>,
1072 <0x0 0x33000000 0x0 0x40000>,
1073 <0x0 0x31080000 0x0 0x40000>;
1074 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1075 ti,num-rings = <1024>;
1076 ti,sci-rm-range-gp-rings = <0x1>;
1077 ti,sci = <&sms>;
1078 ti,sci-dev-id = <259>;
1079 msi-parent = <&main_udmass_inta>;
1080 };
1081
1082 main_udmap: dma-controller@31150000 {
1083 compatible = "ti,j721e-navss-main-udmap";
1084 reg = <0x0 0x31150000 0x0 0x100>,
1085 <0x0 0x34000000 0x0 0x80000>,
1086 <0x0 0x35000000 0x0 0x200000>,
1087 <0x0 0x30b00000 0x0 0x20000>,
1088 <0x0 0x30c00000 0x0 0x8000>,
1089 <0x0 0x30d00000 0x0 0x4000>;
1090 reg-names = "gcfg", "rchanrt", "tchanrt",
1091 "tchan", "rchan", "rflow";
1092 msi-parent = <&main_udmass_inta>;
1093 #dma-cells = <1>;
1094
1095 ti,sci = <&sms>;
1096 ti,sci-dev-id = <263>;
1097 ti,ringacc = <&main_ringacc>;
1098
1099 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1100 <0x0f>, /* TX_HCHAN */
1101 <0x10>; /* TX_UHCHAN */
1102 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1103 <0x0b>, /* RX_HCHAN */
1104 <0x0c>; /* RX_UHCHAN */
1105 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1106 };
1107
1108 main_bcdma_csi: dma-controller@311a0000 {
1109 compatible = "ti,j721s2-dmss-bcdma-csi";
1110 reg = <0x00 0x311a0000 0x00 0x100>,
1111 <0x00 0x35d00000 0x00 0x20000>,
1112 <0x00 0x35c00000 0x00 0x10000>,
1113 <0x00 0x35e00000 0x00 0x80000>;
1114 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1115 msi-parent = <&main_udmass_inta>;
1116 #dma-cells = <3>;
1117 ti,sci = <&sms>;
1118 ti,sci-dev-id = <225>;
1119 ti,sci-rm-range-rchan = <0x21>;
1120 ti,sci-rm-range-tchan = <0x22>;
1121 };
1122
1123 cpts@310d0000 {
1124 compatible = "ti,j721e-cpts";
1125 reg = <0x0 0x310d0000 0x0 0x400>;
1126 reg-names = "cpts";
1127 clocks = <&k3_clks 226 5>;
1128 clock-names = "cpts";
1129 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1130 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1131 interrupts-extended = <&main_navss_intr 391>;
1132 interrupt-names = "cpts";
1133 ti,cpts-periodic-outputs = <6>;
1134 ti,cpts-ext-ts-inputs = <8>;
1135 };
1136 };
1137
1138 main_cpsw: ethernet@c200000 {
1139 compatible = "ti,j721e-cpsw-nuss";
1140 reg = <0x00 0xc200000 0x00 0x200000>;
1141 reg-names = "cpsw_nuss";
1142 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1143 #address-cells = <2>;
1144 #size-cells = <2>;
1145 dma-coherent;
1146 clocks = <&k3_clks 28 28>;
1147 clock-names = "fck";
1148 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1149
1150 dmas = <&main_udmap 0xc640>,
1151 <&main_udmap 0xc641>,
1152 <&main_udmap 0xc642>,
1153 <&main_udmap 0xc643>,
1154 <&main_udmap 0xc644>,
1155 <&main_udmap 0xc645>,
1156 <&main_udmap 0xc646>,
1157 <&main_udmap 0xc647>,
1158 <&main_udmap 0x4640>;
1159 dma-names = "tx0", "tx1", "tx2", "tx3",
1160 "tx4", "tx5", "tx6", "tx7",
1161 "rx";
1162
1163 status = "disabled";
1164
1165 ethernet-ports {
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168
1169 main_cpsw_port1: port@1 {
1170 reg = <1>;
1171 ti,mac-only;
1172 label = "port1";
1173 phys = <&phy_gmii_sel_cpsw 1>;
1174 status = "disabled";
1175 };
1176 };
1177
1178 main_cpsw_mdio: mdio@f00 {
1179 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1180 reg = <0x00 0xf00 0x00 0x100>;
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1183 clocks = <&k3_clks 28 28>;
1184 clock-names = "fck";
1185 bus_freq = <1000000>;
1186 status = "disabled";
1187 };
1188
1189 cpts@3d000 {
1190 compatible = "ti,am65-cpts";
1191 reg = <0x00 0x3d000 0x00 0x400>;
1192 clocks = <&k3_clks 28 3>;
1193 clock-names = "cpts";
1194 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1195 interrupt-names = "cpts";
1196 ti,cpts-ext-ts-inputs = <4>;
1197 ti,cpts-periodic-outputs = <2>;
1198 };
1199 };
1200
1201 usbss0: cdns-usb@4104000 {
1202 compatible = "ti,j721e-usb";
1203 reg = <0x00 0x04104000 0x00 0x100>;
1204 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
1205 clock-names = "ref", "lpm";
1206 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1207 assigned-clock-parents = <&k3_clks 360 17>;
1208 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1209 #address-cells = <2>;
1210 #size-cells = <2>;
1211 ranges;
1212 dma-coherent;
1213
1214 status = "disabled"; /* Needs pinmux */
1215
1216 usb0: usb@6000000 {
1217 compatible = "cdns,usb3";
1218 reg = <0x00 0x06000000 0x00 0x10000>,
1219 <0x00 0x06010000 0x00 0x10000>,
1220 <0x00 0x06020000 0x00 0x10000>;
1221 reg-names = "otg", "xhci", "dev";
1222 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1225 interrupt-names = "host", "peripheral", "otg";
1226 maximum-speed = "super-speed";
1227 dr_mode = "otg";
1228 };
1229 };
1230
1231 ti_csi2rx0: ticsi2rx@4500000 {
1232 compatible = "ti,j721e-csi2rx-shim";
1233 reg = <0x00 0x04500000 0x00 0x1000>;
1234 ranges;
1235 #address-cells = <2>;
1236 #size-cells = <2>;
1237 dmas = <&main_bcdma_csi 0 0x4940 0>;
1238 dma-names = "rx0";
1239 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
1240 status = "disabled";
1241
1242 cdns_csi2rx0: csi-bridge@4504000 {
1243 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1244 reg = <0x00 0x04504000 0x00 0x1000>;
1245 clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
1246 <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
1247 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1248 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1249 phys = <&dphy0>;
1250 phy-names = "dphy";
1251
1252 ports {
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1255
1256 csi0_port0: port@0 {
1257 reg = <0>;
1258 status = "disabled";
1259 };
1260
1261 csi0_port1: port@1 {
1262 reg = <1>;
1263 status = "disabled";
1264 };
1265
1266 csi0_port2: port@2 {
1267 reg = <2>;
1268 status = "disabled";
1269 };
1270
1271 csi0_port3: port@3 {
1272 reg = <3>;
1273 status = "disabled";
1274 };
1275
1276 csi0_port4: port@4 {
1277 reg = <4>;
1278 status = "disabled";
1279 };
1280 };
1281 };
1282 };
1283
1284 ti_csi2rx1: ticsi2rx@4510000 {
1285 compatible = "ti,j721e-csi2rx-shim";
1286 reg = <0x00 0x04510000 0x00 0x1000>;
1287 ranges;
1288 #address-cells = <2>;
1289 #size-cells = <2>;
1290 dmas = <&main_bcdma_csi 0 0x4960 0>;
1291 dma-names = "rx0";
1292 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
1293 status = "disabled";
1294
1295 cdns_csi2rx1: csi-bridge@4514000 {
1296 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1297 reg = <0x00 0x04514000 0x00 0x1000>;
1298 clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
1299 <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
1300 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1301 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1302 phys = <&dphy1>;
1303 phy-names = "dphy";
1304
1305 ports {
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308
1309 csi1_port0: port@0 {
1310 reg = <0>;
1311 status = "disabled";
1312 };
1313
1314 csi1_port1: port@1 {
1315 reg = <1>;
1316 status = "disabled";
1317 };
1318
1319 csi1_port2: port@2 {
1320 reg = <2>;
1321 status = "disabled";
1322 };
1323
1324 csi1_port3: port@3 {
1325 reg = <3>;
1326 status = "disabled";
1327 };
1328
1329 csi1_port4: port@4 {
1330 reg = <4>;
1331 status = "disabled";
1332 };
1333 };
1334 };
1335 };
1336
1337 dphy0: phy@4580000 {
1338 compatible = "cdns,dphy-rx";
1339 reg = <0x00 0x04580000 0x00 0x1100>;
1340 #phy-cells = <0>;
1341 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1342 status = "disabled";
1343 };
1344
1345 dphy1: phy@4590000 {
1346 compatible = "cdns,dphy-rx";
1347 reg = <0x00 0x04590000 0x00 0x1100>;
1348 #phy-cells = <0>;
1349 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1350 status = "disabled";
1351 };
1352
1353 serdes_wiz0: wiz@5060000 {
1354 compatible = "ti,j721s2-wiz-10g";
1355 #address-cells = <1>;
1356 #size-cells = <1>;
1357 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1358 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1359 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1360 num-lanes = <4>;
1361 #reset-cells = <1>;
1362 #clock-cells = <1>;
1363 ranges = <0x5060000 0x0 0x5060000 0x10000>;
1364
1365 assigned-clocks = <&k3_clks 365 3>;
1366 assigned-clock-parents = <&k3_clks 365 7>;
1367
1368 serdes0: serdes@5060000 {
1369 compatible = "ti,j721e-serdes-10g";
1370 reg = <0x05060000 0x00010000>;
1371 reg-names = "torrent_phy";
1372 resets = <&serdes_wiz0 0>;
1373 reset-names = "torrent_reset";
1374 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1375 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
1376 clock-names = "refclk", "phy_en_refclk";
1377 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1378 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
1379 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
1380 assigned-clock-parents = <&k3_clks 365 3>,
1381 <&k3_clks 365 3>,
1382 <&k3_clks 365 3>;
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1385 #clock-cells = <1>;
1386
1387 status = "disabled"; /* Needs lane config */
1388 };
1389 };
1390
1391 pcie1_rc: pcie@2910000 {
1392 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1393 reg = <0x00 0x02910000 0x00 0x1000>,
1394 <0x00 0x02917000 0x00 0x400>,
1395 <0x00 0x0d800000 0x00 0x800000>,
1396 <0x00 0x18000000 0x00 0x1000>;
1397 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1398 interrupt-names = "link_state";
1399 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
1400 device_type = "pci";
1401 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1402 max-link-speed = <3>;
1403 num-lanes = <4>;
1404 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1405 clocks = <&k3_clks 276 41>;
1406 clock-names = "fck";
1407 #address-cells = <3>;
1408 #size-cells = <2>;
1409 bus-range = <0x0 0xff>;
1410 vendor-id = <0x104c>;
1411 device-id = <0xb013>;
1412 msi-map = <0x0 &gic_its 0x0 0x10000>;
1413 dma-coherent;
1414 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
1415 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
1416 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1417 #interrupt-cells = <1>;
1418 interrupt-map-mask = <0 0 0 7>;
1419 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1420 <0 0 0 2 &pcie1_intc 0>, /* INT B */
1421 <0 0 0 3 &pcie1_intc 0>, /* INT C */
1422 <0 0 0 4 &pcie1_intc 0>; /* INT D */
1423
1424 status = "disabled"; /* Needs gpio and serdes info */
1425
1426 pcie1_intc: interrupt-controller {
1427 interrupt-controller;
1428 #interrupt-cells = <1>;
1429 interrupt-parent = <&gic500>;
1430 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
1431 };
1432 };
1433
1434 main_mcan0: can@2701000 {
1435 compatible = "bosch,m_can";
1436 reg = <0x00 0x02701000 0x00 0x200>,
1437 <0x00 0x02708000 0x00 0x8000>;
1438 reg-names = "m_can", "message_ram";
1439 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1440 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1441 clock-names = "hclk", "cclk";
1442 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1444 interrupt-names = "int0", "int1";
1445 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1446 status = "disabled";
1447 };
1448
1449 main_mcan1: can@2711000 {
1450 compatible = "bosch,m_can";
1451 reg = <0x00 0x02711000 0x00 0x200>,
1452 <0x00 0x02718000 0x00 0x8000>;
1453 reg-names = "m_can", "message_ram";
1454 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1455 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1456 clock-names = "hclk", "cclk";
1457 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1459 interrupt-names = "int0", "int1";
1460 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1461 status = "disabled";
1462 };
1463
1464 main_mcan2: can@2721000 {
1465 compatible = "bosch,m_can";
1466 reg = <0x00 0x02721000 0x00 0x200>,
1467 <0x00 0x02728000 0x00 0x8000>;
1468 reg-names = "m_can", "message_ram";
1469 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1470 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1471 clock-names = "hclk", "cclk";
1472 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1474 interrupt-names = "int0", "int1";
1475 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1476 status = "disabled";
1477 };
1478
1479 main_mcan3: can@2731000 {
1480 compatible = "bosch,m_can";
1481 reg = <0x00 0x02731000 0x00 0x200>,
1482 <0x00 0x02738000 0x00 0x8000>;
1483 reg-names = "m_can", "message_ram";
1484 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1485 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1486 clock-names = "hclk", "cclk";
1487 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1489 interrupt-names = "int0", "int1";
1490 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1491 status = "disabled";
1492 };
1493
1494 main_mcan4: can@2741000 {
1495 compatible = "bosch,m_can";
1496 reg = <0x00 0x02741000 0x00 0x200>,
1497 <0x00 0x02748000 0x00 0x8000>;
1498 reg-names = "m_can", "message_ram";
1499 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1500 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1501 clock-names = "hclk", "cclk";
1502 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1504 interrupt-names = "int0", "int1";
1505 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1506 status = "disabled";
1507 };
1508
1509 main_mcan5: can@2751000 {
1510 compatible = "bosch,m_can";
1511 reg = <0x00 0x02751000 0x00 0x200>,
1512 <0x00 0x02758000 0x00 0x8000>;
1513 reg-names = "m_can", "message_ram";
1514 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1515 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1516 clock-names = "hclk", "cclk";
1517 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1519 interrupt-names = "int0", "int1";
1520 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1521 status = "disabled";
1522 };
1523
1524 main_mcan6: can@2761000 {
1525 compatible = "bosch,m_can";
1526 reg = <0x00 0x02761000 0x00 0x200>,
1527 <0x00 0x02768000 0x00 0x8000>;
1528 reg-names = "m_can", "message_ram";
1529 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1530 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1531 clock-names = "hclk", "cclk";
1532 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1534 interrupt-names = "int0", "int1";
1535 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1536 status = "disabled";
1537 };
1538
1539 main_mcan7: can@2771000 {
1540 compatible = "bosch,m_can";
1541 reg = <0x00 0x02771000 0x00 0x200>,
1542 <0x00 0x02778000 0x00 0x8000>;
1543 reg-names = "m_can", "message_ram";
1544 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1545 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1546 clock-names = "hclk", "cclk";
1547 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1549 interrupt-names = "int0", "int1";
1550 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1551 status = "disabled";
1552 };
1553
1554 main_mcan8: can@2781000 {
1555 compatible = "bosch,m_can";
1556 reg = <0x00 0x02781000 0x00 0x200>,
1557 <0x00 0x02788000 0x00 0x8000>;
1558 reg-names = "m_can", "message_ram";
1559 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1560 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1561 clock-names = "hclk", "cclk";
1562 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1564 interrupt-names = "int0", "int1";
1565 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1566 status = "disabled";
1567 };
1568
1569 main_mcan9: can@2791000 {
1570 compatible = "bosch,m_can";
1571 reg = <0x00 0x02791000 0x00 0x200>,
1572 <0x00 0x02798000 0x00 0x8000>;
1573 reg-names = "m_can", "message_ram";
1574 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1575 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1576 clock-names = "hclk", "cclk";
1577 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1579 interrupt-names = "int0", "int1";
1580 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1581 status = "disabled";
1582 };
1583
1584 main_mcan10: can@27a1000 {
1585 compatible = "bosch,m_can";
1586 reg = <0x00 0x027a1000 0x00 0x200>,
1587 <0x00 0x027a8000 0x00 0x8000>;
1588 reg-names = "m_can", "message_ram";
1589 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1590 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1591 clock-names = "hclk", "cclk";
1592 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1593 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1594 interrupt-names = "int0", "int1";
1595 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1596 status = "disabled";
1597 };
1598
1599 main_mcan11: can@27b1000 {
1600 compatible = "bosch,m_can";
1601 reg = <0x00 0x027b1000 0x00 0x200>,
1602 <0x00 0x027b8000 0x00 0x8000>;
1603 reg-names = "m_can", "message_ram";
1604 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1605 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1606 clock-names = "hclk", "cclk";
1607 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1608 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1609 interrupt-names = "int0", "int1";
1610 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1611 status = "disabled";
1612 };
1613
1614 main_mcan12: can@27c1000 {
1615 compatible = "bosch,m_can";
1616 reg = <0x00 0x027c1000 0x00 0x200>,
1617 <0x00 0x027c8000 0x00 0x8000>;
1618 reg-names = "m_can", "message_ram";
1619 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1620 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1621 clock-names = "hclk", "cclk";
1622 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1623 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1624 interrupt-names = "int0", "int1";
1625 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1626 status = "disabled";
1627 };
1628
1629 main_mcan13: can@27d1000 {
1630 compatible = "bosch,m_can";
1631 reg = <0x00 0x027d1000 0x00 0x200>,
1632 <0x00 0x027d8000 0x00 0x8000>;
1633 reg-names = "m_can", "message_ram";
1634 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1635 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1636 clock-names = "hclk", "cclk";
1637 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1638 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1639 interrupt-names = "int0", "int1";
1640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1641 status = "disabled";
1642 };
1643
1644 main_mcan14: can@2681000 {
1645 compatible = "bosch,m_can";
1646 reg = <0x00 0x02681000 0x00 0x200>,
1647 <0x00 0x02688000 0x00 0x8000>;
1648 reg-names = "m_can", "message_ram";
1649 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1650 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1651 clock-names = "hclk", "cclk";
1652 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1654 interrupt-names = "int0", "int1";
1655 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1656 status = "disabled";
1657 };
1658
1659 main_mcan15: can@2691000 {
1660 compatible = "bosch,m_can";
1661 reg = <0x00 0x02691000 0x00 0x200>,
1662 <0x00 0x02698000 0x00 0x8000>;
1663 reg-names = "m_can", "message_ram";
1664 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1665 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1666 clock-names = "hclk", "cclk";
1667 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1668 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1669 interrupt-names = "int0", "int1";
1670 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1671 status = "disabled";
1672 };
1673
1674 main_mcan16: can@26a1000 {
1675 compatible = "bosch,m_can";
1676 reg = <0x00 0x026a1000 0x00 0x200>,
1677 <0x00 0x026a8000 0x00 0x8000>;
1678 reg-names = "m_can", "message_ram";
1679 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1680 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1681 clock-names = "hclk", "cclk";
1682 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1683 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1684 interrupt-names = "int0", "int1";
1685 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1686 status = "disabled";
1687 };
1688
1689 main_mcan17: can@26b1000 {
1690 compatible = "bosch,m_can";
1691 reg = <0x00 0x026b1000 0x00 0x200>,
1692 <0x00 0x026b8000 0x00 0x8000>;
1693 reg-names = "m_can", "message_ram";
1694 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1695 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1696 clock-names = "hclk", "cclk";
1697 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1699 interrupt-names = "int0", "int1";
1700 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1701 status = "disabled";
1702 };
1703
1704 main_spi0: spi@2100000 {
1705 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1706 reg = <0x00 0x02100000 0x00 0x400>;
1707 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1708 #address-cells = <1>;
1709 #size-cells = <0>;
1710 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1711 clocks = <&k3_clks 339 1>;
1712 status = "disabled";
1713 };
1714
1715 main_spi1: spi@2110000 {
1716 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1717 reg = <0x00 0x02110000 0x00 0x400>;
1718 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1719 #address-cells = <1>;
1720 #size-cells = <0>;
1721 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1722 clocks = <&k3_clks 340 1>;
1723 status = "disabled";
1724 };
1725
1726 main_spi2: spi@2120000 {
1727 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1728 reg = <0x00 0x02120000 0x00 0x400>;
1729 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1733 clocks = <&k3_clks 341 1>;
1734 status = "disabled";
1735 };
1736
1737 main_spi3: spi@2130000 {
1738 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1739 reg = <0x00 0x02130000 0x00 0x400>;
1740 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1743 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1744 clocks = <&k3_clks 342 1>;
1745 status = "disabled";
1746 };
1747
1748 main_spi4: spi@2140000 {
1749 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1750 reg = <0x00 0x02140000 0x00 0x400>;
1751 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1754 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1755 clocks = <&k3_clks 343 1>;
1756 status = "disabled";
1757 };
1758
1759 main_spi5: spi@2150000 {
1760 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1761 reg = <0x00 0x02150000 0x00 0x400>;
1762 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1766 clocks = <&k3_clks 344 1>;
1767 status = "disabled";
1768 };
1769
1770 main_spi6: spi@2160000 {
1771 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1772 reg = <0x00 0x02160000 0x00 0x400>;
1773 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1776 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1777 clocks = <&k3_clks 345 1>;
1778 status = "disabled";
1779 };
1780
1781 main_spi7: spi@2170000 {
1782 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1783 reg = <0x00 0x02170000 0x00 0x400>;
1784 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1785 #address-cells = <1>;
1786 #size-cells = <0>;
1787 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1788 clocks = <&k3_clks 346 1>;
1789 status = "disabled";
1790 };
1791
1792 dss: dss@4a00000 {
1793 compatible = "ti,j721e-dss";
1794 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1795 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1796 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1797 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1798 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1799 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1800 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1801 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1802 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1803 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1804 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1805 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1806 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1807 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1808 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1809 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1810 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1811 reg-names = "common_m", "common_s0",
1812 "common_s1", "common_s2",
1813 "vidl1", "vidl2","vid1","vid2",
1814 "ovr1", "ovr2", "ovr3", "ovr4",
1815 "vp1", "vp2", "vp3", "vp4",
1816 "wb";
1817 clocks = <&k3_clks 158 0>,
1818 <&k3_clks 158 2>,
1819 <&k3_clks 158 5>,
1820 <&k3_clks 158 14>,
1821 <&k3_clks 158 18>;
1822 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1823 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1824 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1828 interrupt-names = "common_m",
1829 "common_s0",
1830 "common_s1",
1831 "common_s2";
1832 status = "disabled";
1833
1834 dss_ports: ports {
1835 };
1836 };
1837
1838 main_r5fss0: r5fss@5c00000 {
1839 compatible = "ti,j721s2-r5fss";
1840 ti,cluster-mode = <1>;
1841 #address-cells = <1>;
1842 #size-cells = <1>;
1843 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1844 <0x5d00000 0x00 0x5d00000 0x20000>;
1845 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1846
1847 main_r5fss0_core0: r5f@5c00000 {
1848 compatible = "ti,j721s2-r5f";
1849 reg = <0x5c00000 0x00010000>,
1850 <0x5c10000 0x00010000>;
1851 reg-names = "atcm", "btcm";
1852 ti,sci = <&sms>;
1853 ti,sci-dev-id = <279>;
1854 ti,sci-proc-ids = <0x06 0xff>;
1855 resets = <&k3_reset 279 1>;
1856 firmware-name = "j721s2-main-r5f0_0-fw";
1857 ti,atcm-enable = <1>;
1858 ti,btcm-enable = <1>;
1859 ti,loczrama = <1>;
1860 };
1861
1862 main_r5fss0_core1: r5f@5d00000 {
1863 compatible = "ti,j721s2-r5f";
1864 reg = <0x5d00000 0x00010000>,
1865 <0x5d10000 0x00010000>;
1866 reg-names = "atcm", "btcm";
1867 ti,sci = <&sms>;
1868 ti,sci-dev-id = <280>;
1869 ti,sci-proc-ids = <0x07 0xff>;
1870 resets = <&k3_reset 280 1>;
1871 firmware-name = "j721s2-main-r5f0_1-fw";
1872 ti,atcm-enable = <1>;
1873 ti,btcm-enable = <1>;
1874 ti,loczrama = <1>;
1875 };
1876 };
1877
1878 main_r5fss1: r5fss@5e00000 {
1879 compatible = "ti,j721s2-r5fss";
1880 ti,cluster-mode = <1>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1884 <0x5f00000 0x00 0x5f00000 0x20000>;
1885 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1886
1887 main_r5fss1_core0: r5f@5e00000 {
1888 compatible = "ti,j721s2-r5f";
1889 reg = <0x5e00000 0x00010000>,
1890 <0x5e10000 0x00010000>;
1891 reg-names = "atcm", "btcm";
1892 ti,sci = <&sms>;
1893 ti,sci-dev-id = <281>;
1894 ti,sci-proc-ids = <0x08 0xff>;
1895 resets = <&k3_reset 281 1>;
1896 firmware-name = "j721s2-main-r5f1_0-fw";
1897 ti,atcm-enable = <1>;
1898 ti,btcm-enable = <1>;
1899 ti,loczrama = <1>;
1900 };
1901
1902 main_r5fss1_core1: r5f@5f00000 {
1903 compatible = "ti,j721s2-r5f";
1904 reg = <0x5f00000 0x00010000>,
1905 <0x5f10000 0x00010000>;
1906 reg-names = "atcm", "btcm";
1907 ti,sci = <&sms>;
1908 ti,sci-dev-id = <282>;
1909 ti,sci-proc-ids = <0x09 0xff>;
1910 resets = <&k3_reset 282 1>;
1911 firmware-name = "j721s2-main-r5f1_1-fw";
1912 ti,atcm-enable = <1>;
1913 ti,btcm-enable = <1>;
1914 ti,loczrama = <1>;
1915 };
1916 };
1917
1918 c71_0: dsp@64800000 {
1919 compatible = "ti,j721s2-c71-dsp";
1920 reg = <0x00 0x64800000 0x00 0x00080000>,
1921 <0x00 0x64e00000 0x00 0x0000c000>;
1922 reg-names = "l2sram", "l1dram";
1923 ti,sci = <&sms>;
1924 ti,sci-dev-id = <8>;
1925 ti,sci-proc-ids = <0x30 0xff>;
1926 resets = <&k3_reset 8 1>;
1927 firmware-name = "j721s2-c71_0-fw";
1928 status = "disabled";
1929 };
1930
1931 c71_1: dsp@65800000 {
1932 compatible = "ti,j721s2-c71-dsp";
1933 reg = <0x00 0x65800000 0x00 0x00080000>,
1934 <0x00 0x65e00000 0x00 0x0000c000>;
1935 reg-names = "l2sram", "l1dram";
1936 ti,sci = <&sms>;
1937 ti,sci-dev-id = <11>;
1938 ti,sci-proc-ids = <0x31 0xff>;
1939 resets = <&k3_reset 11 1>;
1940 firmware-name = "j721s2-c71_1-fw";
1941 status = "disabled";
1942 };
1943
1944 main_esm: esm@700000 {
1945 compatible = "ti,j721e-esm";
1946 reg = <0x00 0x700000 0x00 0x1000>;
1947 ti,esm-pins = <688>, <689>;
1948 bootph-pre-ram;
1949 };
1950
1951 watchdog0: watchdog@2200000 {
1952 compatible = "ti,j7-rti-wdt";
1953 reg = <0x00 0x2200000 0x00 0x100>;
1954 clocks = <&k3_clks 286 1>;
1955 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1956 assigned-clocks = <&k3_clks 286 1>;
1957 assigned-clock-parents = <&k3_clks 286 5>;
1958 };
1959
1960 watchdog1: watchdog@2210000 {
1961 compatible = "ti,j7-rti-wdt";
1962 reg = <0x00 0x2210000 0x00 0x100>;
1963 clocks = <&k3_clks 287 1>;
1964 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
1965 assigned-clocks = <&k3_clks 287 1>;
1966 assigned-clock-parents = <&k3_clks 287 5>;
1967 };
1968
1969 /*
1970 * The following RTI instances are coupled with MCU R5Fs, c7x and
1971 * GPU so keeping them reserved as these will be used by their
1972 * respective firmware
1973 */
1974 watchdog2: watchdog@22f0000 {
1975 compatible = "ti,j7-rti-wdt";
1976 reg = <0x00 0x22f0000 0x00 0x100>;
1977 clocks = <&k3_clks 290 1>;
1978 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
1979 assigned-clocks = <&k3_clks 290 1>;
1980 assigned-clock-parents = <&k3_clks 290 5>;
1981 /* reserved for GPU */
1982 status = "reserved";
1983 };
1984
1985 watchdog3: watchdog@2300000 {
1986 compatible = "ti,j7-rti-wdt";
1987 reg = <0x00 0x2300000 0x00 0x100>;
1988 clocks = <&k3_clks 288 1>;
1989 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1990 assigned-clocks = <&k3_clks 288 1>;
1991 assigned-clock-parents = <&k3_clks 288 5>;
1992 /* reserved for C7X_0 */
1993 status = "reserved";
1994 };
1995
1996 watchdog4: watchdog@2310000 {
1997 compatible = "ti,j7-rti-wdt";
1998 reg = <0x00 0x2310000 0x00 0x100>;
1999 clocks = <&k3_clks 289 1>;
2000 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
2001 assigned-clocks = <&k3_clks 289 1>;
2002 assigned-clock-parents = <&k3_clks 289 5>;
2003 /* reserved for C7X_1 */
2004 status = "reserved";
2005 };
2006
2007 watchdog5: watchdog@23c0000 {
2008 compatible = "ti,j7-rti-wdt";
2009 reg = <0x00 0x23c0000 0x00 0x100>;
2010 clocks = <&k3_clks 291 1>;
2011 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
2012 assigned-clocks = <&k3_clks 291 1>;
2013 assigned-clock-parents = <&k3_clks 291 5>;
2014 /* reserved for MAIN_R5F0_0 */
2015 status = "reserved";
2016 };
2017
2018 watchdog6: watchdog@23d0000 {
2019 compatible = "ti,j7-rti-wdt";
2020 reg = <0x00 0x23d0000 0x00 0x100>;
2021 clocks = <&k3_clks 292 1>;
2022 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
2023 assigned-clocks = <&k3_clks 292 1>;
2024 assigned-clock-parents = <&k3_clks 292 5>;
2025 /* reserved for MAIN_R5F0_1 */
2026 status = "reserved";
2027 };
2028
2029 watchdog7: watchdog@23e0000 {
2030 compatible = "ti,j7-rti-wdt";
2031 reg = <0x00 0x23e0000 0x00 0x100>;
2032 clocks = <&k3_clks 293 1>;
2033 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
2034 assigned-clocks = <&k3_clks 293 1>;
2035 assigned-clock-parents = <&k3_clks 293 5>;
2036 /* reserved for MAIN_R5F1_0 */
2037 status = "reserved";
2038 };
2039
2040 watchdog8: watchdog@23f0000 {
2041 compatible = "ti,j7-rti-wdt";
2042 reg = <0x00 0x23f0000 0x00 0x100>;
2043 clocks = <&k3_clks 294 1>;
2044 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
2045 assigned-clocks = <&k3_clks 294 1>;
2046 assigned-clock-parents = <&k3_clks 294 5>;
2047 /* reserved for MAIN_R5F1_1 */
2048 status = "reserved";
2049 };
2050 };
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