1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * SoM: https://www.ti.com/lit/zip/sprr439
4 *
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 /dts-v1/;
9
10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 memory@80000000 {
15 device_type = "memory";
16 bootph-all;
17 /* 16 GB RAM */
18 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
19 <0x00000008 0x80000000 0x00000003 0x80000000>;
20 };
21
22 /* Reserving memory regions still pending */
23 reserved_memory: reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
26 ranges;
27
28 secure_ddr: optee@9e800000 {
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
31 no-map;
32 };
33
34 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
35 compatible = "shared-dma-pool";
36 reg = <0x00 0xa0000000 0x00 0x100000>;
37 no-map;
38 };
39
40 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
41 compatible = "shared-dma-pool";
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 no-map;
44 };
45
46 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
47 compatible = "shared-dma-pool";
48 reg = <0x00 0xa1000000 0x00 0x100000>;
49 no-map;
50 };
51
52 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
53 compatible = "shared-dma-pool";
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 no-map;
56 };
57
58 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
59 compatible = "shared-dma-pool";
60 reg = <0x00 0xa2000000 0x00 0x100000>;
61 no-map;
62 };
63
64 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
65 compatible = "shared-dma-pool";
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
67 no-map;
68 };
69
70 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
71 compatible = "shared-dma-pool";
72 reg = <0x00 0xa3000000 0x00 0x100000>;
73 no-map;
74 };
75
76 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
77 compatible = "shared-dma-pool";
78 reg = <0x00 0xa3100000 0x00 0xf00000>;
79 no-map;
80 };
81
82 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
83 compatible = "shared-dma-pool";
84 reg = <0x00 0xa4000000 0x00 0x100000>;
85 no-map;
86 };
87
88 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
89 compatible = "shared-dma-pool";
90 reg = <0x00 0xa4100000 0x00 0xf00000>;
91 no-map;
92 };
93
94 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
95 compatible = "shared-dma-pool";
96 reg = <0x00 0xa5000000 0x00 0x100000>;
97 no-map;
98 };
99
100 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
101 compatible = "shared-dma-pool";
102 reg = <0x00 0xa5100000 0x00 0xf00000>;
103 no-map;
104 };
105
106 c71_0_dma_memory_region: c71-dma-memory@a6000000 {
107 compatible = "shared-dma-pool";
108 reg = <0x00 0xa6000000 0x00 0x100000>;
109 no-map;
110 };
111
112 c71_0_memory_region: c71-memory@a6100000 {
113 compatible = "shared-dma-pool";
114 reg = <0x00 0xa6100000 0x00 0xf00000>;
115 no-map;
116 };
117
118 c71_1_dma_memory_region: c71-dma-memory@a7000000 {
119 compatible = "shared-dma-pool";
120 reg = <0x00 0xa7000000 0x00 0x100000>;
121 no-map;
122 };
123
124 c71_1_memory_region: c71-memory@a7100000 {
125 compatible = "shared-dma-pool";
126 reg = <0x00 0xa7100000 0x00 0xf00000>;
127 no-map;
128 };
129
130 rtos_ipc_memory_region: ipc-memories@a8000000 {
131 reg = <0x00 0xa8000000 0x00 0x01c00000>;
132 alignment = <0x1000>;
133 no-map;
134 };
135 };
136
137 mux0: mux-controller-0 {
138 compatible = "gpio-mux";
139 #mux-state-cells = <1>;
140 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
141 };
142
143 mux1: mux-controller-1 {
144 compatible = "gpio-mux";
145 #mux-state-cells = <1>;
146 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
147 };
148
149 transceiver0: can-phy0 {
150 /* standby pin has been grounded by default */
151 compatible = "ti,tcan1042";
152 #phy-cells = <0>;
153 max-bitrate = <5000000>;
154 };
155 };
156
157 &wkup_pmx0 {
158 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
159 pinctrl-single,pins = <
160 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
161 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
162 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
163 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
164 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
165 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
166 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
167 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
168 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
169 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
170 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
171 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
172 >;
173 };
174 };
175
176 &wkup_pmx1 {
177 pmic_irq_pins_default: pmic-irq-default-pins {
178 pinctrl-single,pins = <
179 /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
180 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7)
181 >;
182 };
183 };
184
185 &wkup_pmx2 {
186 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
187 pinctrl-single,pins = <
188 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
189 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
190 >;
191 };
192 };
193
194 &main_pmx0 {
195 main_i2c0_pins_default: main-i2c0-default-pins {
196 pinctrl-single,pins = <
197 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
198 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
199 >;
200 };
201
202 main_mcan16_pins_default: main-mcan16-default-pins {
203 pinctrl-single,pins = <
204 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
205 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
206 >;
207 };
208 };
209
210 &wkup_i2c0 {
211 status = "okay";
212 pinctrl-names = "default";
213 pinctrl-0 = <&wkup_i2c0_pins_default>;
214 clock-frequency = <400000>;
215
216 eeprom@50 {
217 /* CAV24C256WE-GT3 */
218 compatible = "atmel,24c256";
219 reg = <0x50>;
220 };
221
222 tps659411: pmic@48 {
223 compatible = "ti,tps6594-q1";
224 reg = <0x48>;
225 system-power-controller;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pmic_irq_pins_default>;
228 interrupt-parent = <&wkup_gpio0>;
229 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
230 gpio-controller;
231 #gpio-cells = <2>;
232 ti,primary-pmic;
233 buck1234-supply = <&vsys_3v3>;
234 buck5-supply = <&vsys_3v3>;
235 ldo1-supply = <&vsys_3v3>;
236 ldo2-supply = <&vsys_3v3>;
237 ldo3-supply = <&vsys_3v3>;
238 ldo4-supply = <&vsys_3v3>;
239
240 regulators {
241 bucka1234: buck1234 {
242 regulator-name = "vdd_cpu_avs";
243 regulator-min-microvolt = <600000>;
244 regulator-max-microvolt = <900000>;
245 regulator-boot-on;
246 regulator-always-on;
247 bootph-pre-ram;
248 };
249
250 bucka5: buck5 {
251 regulator-name = "vdd_mcu_0v85";
252 regulator-min-microvolt = <850000>;
253 regulator-max-microvolt = <850000>;
254 regulator-boot-on;
255 regulator-always-on;
256 };
257
258 ldoa1: ldo1 {
259 regulator-name = "vdd_mcuwk_0v8";
260 regulator-min-microvolt = <800000>;
261 regulator-max-microvolt = <800000>;
262 regulator-boot-on;
263 regulator-always-on;
264 };
265
266 ldoa2: ldo2 {
267 regulator-name = "vdd_mcu_gpioret_3v3";
268 regulator-min-microvolt = <3300000>;
269 regulator-max-microvolt = <3300000>;
270 regulator-boot-on;
271 regulator-always-on;
272 };
273
274 ldoa3: ldo3 {
275 regulator-name = "vdd_mcuio_1v8";
276 regulator-min-microvolt = <1800000>;
277 regulator-max-microvolt = <1800000>;
278 regulator-boot-on;
279 regulator-always-on;
280 };
281
282 ldoa4: ldo4 {
283 regulator-name = "vda_mcu_1v8";
284 regulator-min-microvolt = <1800000>;
285 regulator-max-microvolt = <1800000>;
286 regulator-boot-on;
287 regulator-always-on;
288 };
289 };
290 };
291
292 tps659414: pmic@4c {
293 compatible = "ti,tps6594-q1";
294 reg = <0x4c>;
295 system-power-controller;
296 interrupt-parent = <&wkup_gpio0>;
297 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
298 gpio-controller;
299 #gpio-cells = <2>;
300 buck1-supply = <&vsys_3v3>;
301 buck2-supply = <&vsys_3v3>;
302 buck3-supply = <&vsys_3v3>;
303 buck4-supply = <&vsys_3v3>;
304 buck5-supply = <&vsys_3v3>;
305 ldo1-supply = <&vsys_3v3>;
306 ldo2-supply = <&vsys_3v3>;
307 ldo3-supply = <&vsys_3v3>;
308 ldo4-supply = <&vsys_3v3>;
309
310 regulators {
311 buckb1: buck1 {
312 regulator-name = "vdd_io_1v8_reg";
313 regulator-min-microvolt = <1800000>;
314 regulator-max-microvolt = <1800000>;
315 regulator-always-on;
316 regulator-boot-on;
317 };
318
319 buckb2: buck2 {
320 regulator-name = "vdd_fpd_1v1";
321 regulator-min-microvolt = <1100000>;
322 regulator-max-microvolt = <1100000>;
323 regulator-boot-on;
324 regulator-always-on;
325 };
326
327 buckb3: buck3 {
328 regulator-name = "vdd_phy_1v8";
329 regulator-min-microvolt = <1800000>;
330 regulator-max-microvolt = <1800000>;
331 regulator-boot-on;
332 regulator-always-on;
333 };
334
335 buckb4: buck4 {
336 regulator-name = "vdd_ddr_1v1";
337 regulator-min-microvolt = <1100000>;
338 regulator-max-microvolt = <1100000>;
339 regulator-boot-on;
340 regulator-always-on;
341 };
342
343 buckb5: buck5 {
344 regulator-name = "vdd_ram_0v85";
345 regulator-min-microvolt = <850000>;
346 regulator-max-microvolt = <850000>;
347 regulator-boot-on;
348 regulator-always-on;
349 };
350
351 ldob1: ldo1 {
352 regulator-name = "vdd_wk_0v8";
353 regulator-min-microvolt = <800000>;
354 regulator-max-microvolt = <800000>;
355 regulator-boot-on;
356 regulator-always-on;
357 };
358
359 ldob2: ldo2 {
360 regulator-name = "vdd_gpioret_3v3";
361 regulator-min-microvolt = <3300000>;
362 regulator-max-microvolt = <3300000>;
363 regulator-boot-on;
364 regulator-always-on;
365 };
366
367 ldob3: ldo3 {
368 regulator-name = "vda_dll_0v8";
369 regulator-min-microvolt = <800000>;
370 regulator-max-microvolt = <800000>;
371 regulator-boot-on;
372 regulator-always-on;
373 };
374
375 ldob4: ldo4 {
376 regulator-name = "vda_pll_1v8";
377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <1800000>;
379 regulator-boot-on;
380 regulator-always-on;
381 };
382 };
383 };
384
385 lp876411: pmic@58 {
386 compatible = "ti,lp8764-q1";
387 reg = <0x58>;
388 system-power-controller;
389 interrupt-parent = <&wkup_gpio0>;
390 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
391 gpio-controller;
392 #gpio-cells = <2>;
393 buck1234-supply = <&vsys_3v3>;
394
395 regulators {
396 buckc1234: buck1234 {
397 regulator-name = "vdd_core_0v8";
398 regulator-min-microvolt = <800000>;
399 regulator-max-microvolt = <800000>;
400 regulator-boot-on;
401 regulator-always-on;
402 };
403 };
404 };
405 };
406
407 &main_i2c0 {
408 status = "okay";
409 pinctrl-names = "default";
410 pinctrl-0 = <&main_i2c0_pins_default>;
411 clock-frequency = <400000>;
412
413 exp_som: gpio@21 {
414 compatible = "ti,tca6408";
415 reg = <0x21>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
419 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
420 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
421 "GPIO_LIN_EN", "CAN_STB";
422 };
423 };
424
425 &main_mcan16 {
426 status = "okay";
427 pinctrl-0 = <&main_mcan16_pins_default>;
428 pinctrl-names = "default";
429 phys = <&transceiver0>;
430 };
431
432 &ospi0 {
433 status = "okay";
434 pinctrl-names = "default";
435 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
436
437 flash@0 {
438 compatible = "jedec,spi-nor";
439 reg = <0x0>;
440 spi-tx-bus-width = <8>;
441 spi-rx-bus-width = <8>;
442 spi-max-frequency = <25000000>;
443 cdns,tshsl-ns = <60>;
444 cdns,tsd2d-ns = <60>;
445 cdns,tchsh-ns = <60>;
446 cdns,tslch-ns = <60>;
447 cdns,read-delay = <4>;
448 };
449 };
450
451 &mailbox0_cluster0 {
452 status = "okay";
453 interrupts = <436>;
454 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
455 ti,mbox-rx = <0 0 0>;
456 ti,mbox-tx = <1 0 0>;
457 };
458
459 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
460 ti,mbox-rx = <2 0 0>;
461 ti,mbox-tx = <3 0 0>;
462 };
463 };
464
465 &mailbox0_cluster1 {
466 status = "okay";
467 interrupts = <432>;
468 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
469 ti,mbox-rx = <0 0 0>;
470 ti,mbox-tx = <1 0 0>;
471 };
472
473 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
474 ti,mbox-rx = <2 0 0>;
475 ti,mbox-tx = <3 0 0>;
476 };
477 };
478
479 &mailbox0_cluster2 {
480 status = "okay";
481 interrupts = <428>;
482 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
483 ti,mbox-rx = <0 0 0>;
484 ti,mbox-tx = <1 0 0>;
485 };
486
487 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
488 ti,mbox-rx = <2 0 0>;
489 ti,mbox-tx = <3 0 0>;
490 };
491 };
492
493 &mailbox0_cluster4 {
494 status = "okay";
495 interrupts = <420>;
496 mbox_c71_0: mbox-c71-0 {
497 ti,mbox-rx = <0 0 0>;
498 ti,mbox-tx = <1 0 0>;
499 };
500
501 mbox_c71_1: mbox-c71-1 {
502 ti,mbox-rx = <2 0 0>;
503 ti,mbox-tx = <3 0 0>;
504 };
505 };
506
507 &mcu_r5fss0_core0 {
508 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
509 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
510 <&mcu_r5fss0_core0_memory_region>;
511 };
512
513 &mcu_r5fss0_core1 {
514 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
515 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
516 <&mcu_r5fss0_core1_memory_region>;
517 };
518
519 &main_r5fss0 {
520 ti,cluster-mode = <0>;
521 };
522
523 &main_r5fss1 {
524 ti,cluster-mode = <0>;
525 };
526
527 /* Timers are used by Remoteproc firmware */
528 &main_timer0 {
529 status = "reserved";
530 };
531
532 &main_timer1 {
533 status = "reserved";
534 };
535
536 &main_timer2 {
537 status = "reserved";
538 };
539
540 &main_timer3 {
541 status = "reserved";
542 };
543
544 &main_timer4 {
545 status = "reserved";
546 };
547
548 &main_timer5 {
549 status = "reserved";
550 };
551
552 &main_r5fss0_core0 {
553 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
554 memory-region = <&main_r5fss0_core0_dma_memory_region>,
555 <&main_r5fss0_core0_memory_region>;
556 };
557
558 &main_r5fss0_core1 {
559 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
560 memory-region = <&main_r5fss0_core1_dma_memory_region>,
561 <&main_r5fss0_core1_memory_region>;
562 };
563
564 &main_r5fss1_core0 {
565 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
566 memory-region = <&main_r5fss1_core0_dma_memory_region>,
567 <&main_r5fss1_core0_memory_region>;
568 };
569
570 &main_r5fss1_core1 {
571 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
572 memory-region = <&main_r5fss1_core1_dma_memory_region>,
573 <&main_r5fss1_core1_memory_region>;
574 };
575
576 &c71_0 {
577 status = "okay";
578 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
579 memory-region = <&c71_0_dma_memory_region>,
580 <&c71_0_memory_region>;
581 };
582
583 &c71_1 {
584 status = "okay";
585 mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
586 memory-region = <&c71_1_dma_memory_region>,
587 <&c71_1_memory_region>;
588 };
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