1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree file for the J722S EVM
4 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Schematics: https://www.ti.com/lit/zip/sprr495
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include "k3-j722s.dtsi"
14 #include "k3-serdes.h"
15
16 / {
17 compatible = "ti,j722s-evm", "ti,j722s";
18 model = "Texas Instruments J722S EVM";
19
20 aliases {
21 serial0 = &wkup_uart0;
22 serial2 = &main_uart0;
23 serial3 = &main_uart5;
24 mmc0 = &sdhci0;
25 mmc1 = &sdhci1;
26 };
27
28 chosen {
29 stdout-path = &main_uart0;
30 };
31
32 memory@80000000 {
33 /* 8G RAM */
34 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
35 <0x00000008 0x80000000 0x00000001 0x80000000>;
36 device_type = "memory";
37 bootph-pre-ram;
38 };
39
40 reserved_memory: reserved-memory {
41 #address-cells = <2>;
42 #size-cells = <2>;
43 ranges;
44
45 secure_tfa_ddr: tfa@9e780000 {
46 reg = <0x00 0x9e780000 0x00 0x80000>;
47 no-map;
48 };
49
50 secure_ddr: optee@9e800000 {
51 reg = <0x00 0x9e800000 0x00 0x01800000>;
52 no-map;
53 };
54
55 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
56 compatible = "shared-dma-pool";
57 reg = <0x00 0xa0000000 0x00 0x100000>;
58 no-map;
59 };
60
61 wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
62 compatible = "shared-dma-pool";
63 reg = <0x00 0xa0100000 0x00 0xf00000>;
64 no-map;
65 };
66
67 mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
68 compatible = "shared-dma-pool";
69 reg = <0x00 0xa1000000 0x00 0x100000>;
70 no-map;
71 };
72
73 mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
74 compatible = "shared-dma-pool";
75 reg = <0x00 0xa1100000 0x00 0xf00000>;
76 no-map;
77 };
78
79 main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
80 compatible = "shared-dma-pool";
81 reg = <0x00 0xa2000000 0x00 0x100000>;
82 no-map;
83 };
84
85 main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
86 compatible = "shared-dma-pool";
87 reg = <0x00 0xa2100000 0x00 0xf00000>;
88 no-map;
89 };
90
91 c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
92 compatible = "shared-dma-pool";
93 reg = <0x00 0xa3000000 0x00 0x100000>;
94 no-map;
95 };
96
97 c7x_0_memory_region: c7x-memory@a3100000 {
98 compatible = "shared-dma-pool";
99 reg = <0x00 0xa3100000 0x00 0xf00000>;
100 no-map;
101 };
102
103 c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
104 compatible = "shared-dma-pool";
105 reg = <0x00 0xa4000000 0x00 0x100000>;
106 no-map;
107 };
108
109 c7x_1_memory_region: c7x-memory@a4100000 {
110 compatible = "shared-dma-pool";
111 reg = <0x00 0xa4100000 0x00 0xf00000>;
112 no-map;
113 };
114
115 rtos_ipc_memory_region: ipc-memories@a5000000 {
116 reg = <0x00 0xa5000000 0x00 0x1c00000>;
117 alignment = <0x1000>;
118 no-map;
119 };
120 };
121
122 vmain_pd: regulator-0 {
123 /* TPS65988 PD CONTROLLER OUTPUT */
124 compatible = "regulator-fixed";
125 regulator-name = "vmain_pd";
126 regulator-min-microvolt = <5000000>;
127 regulator-max-microvolt = <5000000>;
128 regulator-always-on;
129 regulator-boot-on;
130 bootph-all;
131 };
132
133 vsys_5v0: regulator-vsys5v0 {
134 /* Output of LM5140 */
135 compatible = "regulator-fixed";
136 regulator-name = "vsys_5v0";
137 regulator-min-microvolt = <5000000>;
138 regulator-max-microvolt = <5000000>;
139 vin-supply = <&vmain_pd>;
140 regulator-always-on;
141 regulator-boot-on;
142 };
143
144 vdd_mmc1: regulator-mmc1 {
145 /* TPS22918DBVR */
146 compatible = "regulator-fixed";
147 regulator-name = "vdd_mmc1";
148 regulator-min-microvolt = <3300000>;
149 regulator-max-microvolt = <3300000>;
150 regulator-boot-on;
151 enable-active-high;
152 gpio = <&exp1 15 GPIO_ACTIVE_HIGH>;
153 bootph-all;
154 };
155
156 vdd_sd_dv: regulator-TLV71033 {
157 compatible = "regulator-gpio";
158 regulator-name = "tlv71033";
159 pinctrl-names = "default";
160 pinctrl-0 = <&vdd_sd_dv_pins_default>;
161 regulator-min-microvolt = <1800000>;
162 regulator-max-microvolt = <3300000>;
163 regulator-boot-on;
164 vin-supply = <&vsys_5v0>;
165 gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
166 states = <1800000 0x0>,
167 <3300000 0x1>;
168 };
169
170 vsys_io_3v3: regulator-vsys-io-3v3 {
171 compatible = "regulator-fixed";
172 regulator-name = "vsys_io_3v3";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 regulator-always-on;
176 regulator-boot-on;
177 };
178
179 vsys_io_1v8: regulator-vsys-io-1v8 {
180 compatible = "regulator-fixed";
181 regulator-name = "vsys_io_1v8";
182 regulator-min-microvolt = <1800000>;
183 regulator-max-microvolt = <1800000>;
184 regulator-always-on;
185 regulator-boot-on;
186 };
187
188 vsys_io_1v2: regulator-vsys-io-1v2 {
189 compatible = "regulator-fixed";
190 regulator-name = "vsys_io_1v2";
191 regulator-min-microvolt = <1200000>;
192 regulator-max-microvolt = <1200000>;
193 regulator-always-on;
194 regulator-boot-on;
195 };
196
197 codec_audio: sound {
198 compatible = "simple-audio-card";
199 simple-audio-card,name = "J722S-EVM";
200 simple-audio-card,widgets =
201 "Headphone", "Headphone Jack",
202 "Line", "Line In",
203 "Microphone", "Microphone Jack";
204 simple-audio-card,routing =
205 "Headphone Jack", "HPLOUT",
206 "Headphone Jack", "HPROUT",
207 "LINE1L", "Line In",
208 "LINE1R", "Line In",
209 "MIC3R", "Microphone Jack",
210 "Microphone Jack", "Mic Bias";
211 simple-audio-card,format = "dsp_b";
212 simple-audio-card,bitclock-master = <&sound_master>;
213 simple-audio-card,frame-master = <&sound_master>;
214 simple-audio-card,bitclock-inversion;
215
216 simple-audio-card,cpu {
217 sound-dai = <&mcasp1>;
218 };
219
220 sound_master: simple-audio-card,codec {
221 sound-dai = <&tlv320aic3106>;
222 clocks = <&audio_refclk1>;
223 };
224 };
225
226 transceiver0: can-phy0 {
227 compatible = "ti,tcan1042";
228 #phy-cells = <0>;
229 max-bitrate = <5000000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
232 standby-gpios = <&mcu_gpio0 12 GPIO_ACTIVE_HIGH>;
233 };
234
235 transceiver1: can-phy1 {
236 compatible = "ti,tcan1042";
237 #phy-cells = <0>;
238 max-bitrate = <5000000>;
239 };
240
241 transceiver2: can-phy2 {
242 compatible = "ti,tcan1042";
243 #phy-cells = <0>;
244 max-bitrate = <5000000>;
245 standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>;
246 };
247 };
248
249 &main_pmx0 {
250
251 main_mcan0_pins_default: main-mcan0-default-pins {
252 pinctrl-single,pins = <
253 J722S_IOPAD(0x1dc, PIN_INPUT, 0) /* (C22) MCAN0_RX */
254 J722S_IOPAD(0x1d8, PIN_OUTPUT, 0) /*(D22) MCAN0_TX */
255 >;
256 };
257
258 main_i2c0_pins_default: main-i2c0-default-pins {
259 pinctrl-single,pins = <
260 J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
261 J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
262 >;
263 bootph-all;
264 };
265
266 main_uart0_pins_default: main-uart0-default-pins {
267 pinctrl-single,pins = <
268 J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
269 J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
270 >;
271 bootph-all;
272 };
273
274 main_uart5_pins_default: main-uart5-default-pins {
275 pinctrl-single,pins = <
276 J722S_IOPAD(0x0108, PIN_INPUT, 3) /* (J27) UART5_RXD */
277 J722S_IOPAD(0x010c, PIN_OUTPUT, 3) /* (H27) UART5_TXD */
278 >;
279 };
280
281 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
282 pinctrl-single,pins = <
283 J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */
284 >;
285 bootph-all;
286 };
287
288 main_mmc1_pins_default: main-mmc1-default-pins {
289 pinctrl-single,pins = <
290 J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */
291 J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */
292 J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */
293 J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */
294 J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */
295 J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
296 J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */
297 >;
298 bootph-all;
299 };
300
301 mdio_pins_default: mdio-default-pins {
302 pinctrl-single,pins = <
303 J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */
304 J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */
305 >;
306 };
307
308 ospi0_pins_default: ospi0-default-pins {
309 pinctrl-single,pins = <
310 J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */
311 J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */
312 J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */
313 J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */
314 J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */
315 J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */
316 J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */
317 J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */
318 J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */
319 J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */
320 J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */
321 >;
322 bootph-all;
323 };
324
325 rgmii1_pins_default: rgmii1-default-pins {
326 pinctrl-single,pins = <
327 J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */
328 J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */
329 J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */
330 J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */
331 J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */
332 J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */
333 J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */
334 J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */
335 J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */
336 J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */
337 J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
338 J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
339 >;
340 };
341
342 main_usb1_pins_default: main-usb1-default-pins {
343 pinctrl-single,pins = <
344 J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
345 >;
346 };
347
348 main_mcasp1_pins_default: main-mcasp1-default-pins {
349 pinctrl-single,pins = <
350 J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */
351 J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */
352 J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */
353 J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */
354 >;
355 };
356
357 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
358 pinctrl-single,pins = <
359 J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
360 >;
361 };
362 };
363
364 &cpsw3g {
365 status = "okay";
366 pinctrl-names = "default";
367 pinctrl-0 = <&rgmii1_pins_default>;
368 };
369
370 &cpsw3g_mdio {
371 status = "okay";
372 pinctrl-names = "default";
373 pinctrl-0 = <&mdio_pins_default>;
374
375 cpsw3g_phy0: ethernet-phy@0 {
376 reg = <0>;
377 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
378 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
379 ti,min-output-impedance;
380 };
381 };
382
383 &cpsw_port1 {
384 phy-mode = "rgmii-rxid";
385 phy-handle = <&cpsw3g_phy0>;
386 status = "okay";
387 };
388
389 &main_gpio1 {
390 status = "okay";
391 };
392
393 &main_uart0 {
394 pinctrl-names = "default";
395 pinctrl-0 = <&main_uart0_pins_default>;
396 status = "okay";
397 bootph-all;
398 };
399
400 &main_uart5 {
401 /* MAIN UART 5 is used by System firmware */
402 pinctrl-names = "default";
403 pinctrl-0 = <&main_uart5_pins_default>;
404 status = "reserved";
405 };
406
407 &mcu_pmx0 {
408
409 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
410 pinctrl-single,pins = <
411 J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */
412 J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */
413 >;
414 };
415
416 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
417 pinctrl-single,pins = <
418 J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */
419 J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
420 >;
421 };
422
423 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
424 pinctrl-single,pins = <
425 J722S_MCU_IOPAD(0x0030, PIN_OUTPUT, 7) /* (C3) MCU_GPIO0_12 */
426 >;
427 };
428
429 wkup_uart0_pins_default: wkup-uart0-default-pins {
430 pinctrl-single,pins = <
431 J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
432 J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */
433 J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */
434 J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */
435 >;
436 bootph-all;
437 };
438
439 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
440 pinctrl-single,pins = <
441 J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */
442 J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */
443 >;
444 bootph-all;
445 };
446 };
447
448 &wkup_uart0 {
449 /* WKUP UART0 is used by Device Manager firmware */
450 pinctrl-names = "default";
451 pinctrl-0 = <&wkup_uart0_pins_default>;
452 status = "reserved";
453 bootph-all;
454 };
455
456 &wkup_i2c0 {
457 pinctrl-names = "default";
458 pinctrl-0 = <&wkup_i2c0_pins_default>;
459 clock-frequency = <400000>;
460 status = "okay";
461 bootph-all;
462 };
463
464 &k3_clks {
465 /* Configure AUDIO_EXT_REFCLK1 pin as output */
466 pinctrl-names = "default";
467 pinctrl-0 = <&audio_ext_refclk1_pins_default>;
468 };
469
470 &main_i2c0 {
471 pinctrl-names = "default";
472 pinctrl-0 = <&main_i2c0_pins_default>;
473 clock-frequency = <400000>;
474 status = "okay";
475 bootph-all;
476
477 exp1: gpio@23 {
478 compatible = "ti,tca6424";
479 reg = <0x23>;
480 gpio-controller;
481 #gpio-cells = <2>;
482 gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL",
483 "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#",
484 "CSI_VIO_SEL", "USB2.0_MUX_SEL",
485 "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2",
486 "LMK1_OE1", "LMK1_OE0",
487 "LMK2_OE0", "LMK2_OE1",
488 "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn",
489 "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN",
490 "USER_LED2", "MCAN0_STB",
491 "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
492 "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
493 "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
494
495 p05-hog {
496 /* P05 - USB2.0_MUX_SEL */
497 gpio-hog;
498 gpios = <5 GPIO_ACTIVE_HIGH>;
499 output-high;
500 };
501
502 p01_hog: p01-hog {
503 /* P01 - TRC_MUX_SEL */
504 gpio-hog;
505 gpios = <0 GPIO_ACTIVE_HIGH>;
506 output-low;
507 line-name = "TRC_MUX_SEL";
508 };
509
510 p02_hog: p02-hog {
511 /* P02 - MCASP1_FET_SEL */
512 gpio-hog;
513 gpios = <2 GPIO_ACTIVE_HIGH>;
514 output-high;
515 line-name = "MCASP1_FET_SEL";
516 };
517
518 p13_hog: p13-hog {
519 /* P13 - GPIO_AUD_RSTn */
520 gpio-hog;
521 gpios = <13 GPIO_ACTIVE_HIGH>;
522 output-high;
523 line-name = "GPIO_AUD_RSTn";
524 };
525 };
526
527 tlv320aic3106: audio-codec@1b {
528 #sound-dai-cells = <0>;
529 compatible = "ti,tlv320aic3106";
530 reg = <0x1b>;
531 ai3x-micbias-vg = <1>; /* 2.0V */
532 AVDD-supply = <&vsys_io_3v3>;
533 IOVDD-supply = <&vsys_io_3v3>;
534 DRVDD-supply = <&vsys_io_3v3>;
535 DVDD-supply = <&vsys_io_1v8>;
536 };
537 };
538
539 &ospi0 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&ospi0_pins_default>;
542 status = "okay";
543
544 flash@0 {
545 compatible = "jedec,spi-nor";
546 reg = <0x0>;
547 spi-tx-bus-width = <8>;
548 spi-rx-bus-width = <8>;
549 spi-max-frequency = <25000000>;
550 cdns,tshsl-ns = <60>;
551 cdns,tsd2d-ns = <60>;
552 cdns,tchsh-ns = <60>;
553 cdns,tslch-ns = <60>;
554 cdns,read-delay = <4>;
555 bootph-all;
556
557 partitions {
558 compatible = "fixed-partitions";
559 #address-cells = <1>;
560 #size-cells = <1>;
561
562 partition@0 {
563 label = "ospi.tiboot3";
564 reg = <0x00 0x80000>;
565 };
566
567 partition@80000 {
568 label = "ospi.tispl";
569 reg = <0x80000 0x200000>;
570 };
571
572 partition@280000 {
573 label = "ospi.u-boot";
574 reg = <0x280000 0x400000>;
575 };
576
577 partition@680000 {
578 label = "ospi.env";
579 reg = <0x680000 0x40000>;
580 };
581
582 partition@6c0000 {
583 label = "ospi.env.backup";
584 reg = <0x6c0000 0x40000>;
585 };
586
587 partition@800000 {
588 label = "ospi.rootfs";
589 reg = <0x800000 0x37c0000>;
590 };
591
592 partition@3fc0000 {
593 label = "ospi.phypattern";
594 reg = <0x3fc0000 0x40000>;
595 };
596 };
597 };
598
599 };
600
601 &sdhci0 {
602 disable-wp;
603 bootph-all;
604 ti,driver-strength-ohm = <50>;
605 status = "okay";
606 };
607
608 &sdhci1 {
609 /* SD/MMC */
610 vmmc-supply = <&vdd_mmc1>;
611 vqmmc-supply = <&vdd_sd_dv>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&main_mmc1_pins_default>;
614 ti,driver-strength-ohm = <50>;
615 disable-wp;
616 status = "okay";
617 bootph-all;
618 };
619
620 &mailbox0_cluster0 {
621 status = "okay";
622
623 mbox_wkup_r5_0: mbox-wkup-r5-0 {
624 ti,mbox-rx = <0 0 0>;
625 ti,mbox-tx = <1 0 0>;
626 };
627 };
628
629 &mailbox0_cluster1 {
630 status = "okay";
631
632 mbox_mcu_r5_0: mbox-mcu-r5-0 {
633 ti,mbox-rx = <0 0 0>;
634 ti,mbox-tx = <1 0 0>;
635 };
636 };
637
638 &mailbox0_cluster2 {
639 status = "okay";
640
641 mbox_c7x_0: mbox-c7x-0 {
642 ti,mbox-rx = <0 0 0>;
643 ti,mbox-tx = <1 0 0>;
644 };
645 };
646
647 &mailbox0_cluster3 {
648 status = "okay";
649
650 mbox_main_r5_0: mbox-main-r5-0 {
651 ti,mbox-rx = <0 0 0>;
652 ti,mbox-tx = <1 0 0>;
653 };
654
655 mbox_c7x_1: mbox-c7x-1 {
656 ti,mbox-rx = <2 0 0>;
657 ti,mbox-tx = <3 0 0>;
658 };
659 };
660
661 /* Timers are used by Remoteproc firmware */
662 &main_timer0 {
663 status = "reserved";
664 };
665
666 &main_timer1 {
667 status = "reserved";
668 };
669
670 &main_timer2 {
671 status = "reserved";
672 };
673
674 &wkup_r5fss0 {
675 status = "okay";
676 };
677
678 &wkup_r5fss0_core0 {
679 mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
680 memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
681 <&wkup_r5fss0_core0_memory_region>;
682 };
683
684 &mcu_r5fss0 {
685 status = "okay";
686 };
687
688 &mcu_r5fss0_core0 {
689 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
690 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
691 <&mcu_r5fss0_core0_memory_region>;
692 };
693
694 &main_r5fss0 {
695 status = "okay";
696 };
697
698 &main_r5fss0_core0 {
699 mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
700 memory-region = <&main_r5fss0_core0_dma_memory_region>,
701 <&main_r5fss0_core0_memory_region>;
702 };
703
704 &c7x_0 {
705 mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
706 memory-region = <&c7x_0_dma_memory_region>,
707 <&c7x_0_memory_region>;
708 status = "okay";
709 };
710
711 &c7x_1 {
712 mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
713 memory-region = <&c7x_1_dma_memory_region>,
714 <&c7x_1_memory_region>;
715 status = "okay";
716 };
717
718 &serdes_ln_ctrl {
719 idle-states = <J722S_SERDES0_LANE0_USB>,
720 <J722S_SERDES1_LANE0_PCIE0_LANE0>;
721 };
722
723 &serdes0 {
724 status = "okay";
725 serdes0_usb_link: phy@0 {
726 reg = <0>;
727 cdns,num-lanes = <1>;
728 #phy-cells = <0>;
729 cdns,phy-type = <PHY_TYPE_USB3>;
730 resets = <&serdes_wiz0 1>;
731 };
732 };
733
734 &serdes1 {
735 status = "okay";
736 serdes1_pcie_link: phy@0 {
737 reg = <0>;
738 cdns,num-lanes = <1>;
739 #phy-cells = <0>;
740 cdns,phy-type = <PHY_TYPE_PCIE>;
741 resets = <&serdes_wiz1 1>;
742 };
743 };
744
745 &pcie0_rc {
746 reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
747 phys = <&serdes1_pcie_link>;
748 phy-names = "pcie-phy";
749 status = "okay";
750 };
751
752 &usbss0 {
753 ti,vbus-divider;
754 status = "okay";
755 };
756
757 &usb0 {
758 dr_mode = "otg";
759 usb-role-switch;
760 };
761
762 &usbss1 {
763 pinctrl-names = "default";
764 pinctrl-0 = <&main_usb1_pins_default>;
765 ti,vbus-divider;
766 status = "okay";
767 };
768
769 &usb1 {
770 dr_mode = "host";
771 maximum-speed = "super-speed";
772 phys = <&serdes0_usb_link>;
773 phy-names = "cdns3,usb3-phy";
774 };
775
776 &mcasp1 {
777 status = "okay";
778 #sound-dai-cells = <0>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&main_mcasp1_pins_default>;
781 op-mode = <0>; /* MCASP_IIS_MODE */
782 tdm-slots = <2>;
783 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
784 1 0 2 0
785 0 0 0 0
786 0 0 0 0
787 0 0 0 0
788 >;
789 };
790
791 &mcu_mcan0 {
792 pinctrl-names = "default";
793 pinctrl-0 = <&mcu_mcan0_pins_default>;
794 phys = <&transceiver0>;
795 status = "okay";
796 };
797
798 &mcu_mcan1 {
799 pinctrl-names = "default";
800 pinctrl-0 = <&mcu_mcan1_pins_default>;
801 phys = <&transceiver1>;
802 status = "okay";
803 };
804
805 &main_mcan0 {
806 pinctrl-names = "default";
807 pinctrl-0 = <&main_mcan0_pins_default>;
808 phys = <&transceiver2>;
809 status = "okay";
810 };
811
812 &mcu_gpio0 {
813 status = "okay";
814 };
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