1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for J784S4 SoC Family
4 *
5 * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
6 *
7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 *
9 */
10
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
14
15 #include "k3-pinctrl.h"
16
17 / {
18 model = "Texas Instruments K3 J784S4 SoC";
19 compatible = "ti,j784s4";
20 interrupt-parent = <&gic500>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cpu-map {
28 cluster0: cluster0 {
29 core0 {
30 cpu = <&cpu0>;
31 };
32
33 core1 {
34 cpu = <&cpu1>;
35 };
36
37 core2 {
38 cpu = <&cpu2>;
39 };
40
41 core3 {
42 cpu = <&cpu3>;
43 };
44 };
45
46 cluster1: cluster1 {
47 core0 {
48 cpu = <&cpu4>;
49 };
50
51 core1 {
52 cpu = <&cpu5>;
53 };
54
55 core2 {
56 cpu = <&cpu6>;
57 };
58
59 core3 {
60 cpu = <&cpu7>;
61 };
62 };
63 };
64
65 cpu0: cpu@0 {
66 compatible = "arm,cortex-a72";
67 reg = <0x000>;
68 device_type = "cpu";
69 enable-method = "psci";
70 i-cache-size = <0xc000>;
71 i-cache-line-size = <64>;
72 i-cache-sets = <256>;
73 d-cache-size = <0x8000>;
74 d-cache-line-size = <64>;
75 d-cache-sets = <256>;
76 next-level-cache = <&L2_0>;
77 };
78
79 cpu1: cpu@1 {
80 compatible = "arm,cortex-a72";
81 reg = <0x001>;
82 device_type = "cpu";
83 enable-method = "psci";
84 i-cache-size = <0xc000>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <256>;
87 d-cache-size = <0x8000>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <256>;
90 next-level-cache = <&L2_0>;
91 };
92
93 cpu2: cpu@2 {
94 compatible = "arm,cortex-a72";
95 reg = <0x002>;
96 device_type = "cpu";
97 enable-method = "psci";
98 i-cache-size = <0xc000>;
99 i-cache-line-size = <64>;
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <256>;
104 next-level-cache = <&L2_0>;
105 };
106
107 cpu3: cpu@3 {
108 compatible = "arm,cortex-a72";
109 reg = <0x003>;
110 device_type = "cpu";
111 enable-method = "psci";
112 i-cache-size = <0xc000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <256>;
118 next-level-cache = <&L2_0>;
119 };
120
121 cpu4: cpu@100 {
122 compatible = "arm,cortex-a72";
123 reg = <0x100>;
124 device_type = "cpu";
125 enable-method = "psci";
126 i-cache-size = <0xc000>;
127 i-cache-line-size = <64>;
128 i-cache-sets = <256>;
129 d-cache-size = <0x8000>;
130 d-cache-line-size = <64>;
131 d-cache-sets = <256>;
132 next-level-cache = <&L2_1>;
133 };
134
135 cpu5: cpu@101 {
136 compatible = "arm,cortex-a72";
137 reg = <0x101>;
138 device_type = "cpu";
139 enable-method = "psci";
140 i-cache-size = <0xc000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
146 next-level-cache = <&L2_1>;
147 };
148
149 cpu6: cpu@102 {
150 compatible = "arm,cortex-a72";
151 reg = <0x102>;
152 device_type = "cpu";
153 enable-method = "psci";
154 i-cache-size = <0xc000>;
155 i-cache-line-size = <64>;
156 i-cache-sets = <256>;
157 d-cache-size = <0x8000>;
158 d-cache-line-size = <64>;
159 d-cache-sets = <256>;
160 next-level-cache = <&L2_1>;
161 };
162
163 cpu7: cpu@103 {
164 compatible = "arm,cortex-a72";
165 reg = <0x103>;
166 device_type = "cpu";
167 enable-method = "psci";
168 i-cache-size = <0xc000>;
169 i-cache-line-size = <64>;
170 i-cache-sets = <256>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <256>;
174 next-level-cache = <&L2_1>;
175 };
176 };
177
178 L2_0: l2-cache0 {
179 compatible = "cache";
180 cache-level = <2>;
181 cache-unified;
182 cache-size = <0x200000>;
183 cache-line-size = <64>;
184 cache-sets = <1024>;
185 next-level-cache = <&msmc_l3>;
186 };
187
188 L2_1: l2-cache1 {
189 compatible = "cache";
190 cache-level = <2>;
191 cache-unified;
192 cache-size = <0x200000>;
193 cache-line-size = <64>;
194 cache-sets = <1024>;
195 next-level-cache = <&msmc_l3>;
196 };
197
198 msmc_l3: l3-cache0 {
199 compatible = "cache";
200 cache-level = <3>;
201 cache-unified;
202 };
203
204 firmware {
205 optee {
206 compatible = "linaro,optee-tz";
207 method = "smc";
208 };
209
210 psci: psci {
211 compatible = "arm,psci-1.0";
212 method = "smc";
213 };
214 };
215
216 a72_timer0: timer-cl0-cpu0 {
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
222 };
223
224 pmu: pmu {
225 compatible = "arm,cortex-a72-pmu";
226 /* Recommendation from GIC500 TRM Table A.3 */
227 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
228 };
229
230 cbass_main: bus@100000 {
231 bootph-all;
232 compatible = "simple-bus";
233 #address-cells = <2>;
234 #size-cells = <2>;
235 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
236 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
237 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
238 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
239 <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
240 <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
241 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
242 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
243 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
244 <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
245 <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
246 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
247 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
248 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
249 <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
250 <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
251 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
252 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
253 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
254 <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
255 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
256 <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
257 <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
258 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
259 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
260 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
261
262 /* MCUSS_WKUP Range */
263 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
264 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
265 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
266 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
267 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
268 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
269 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
270 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
271 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
272 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
273 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
274 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
275
276 cbass_mcu_wakeup: bus@28380000 {
277 bootph-all;
278 compatible = "simple-bus";
279 #address-cells = <2>;
280 #size-cells = <2>;
281 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
282 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
283 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
284 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
285 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
286 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
287 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
288 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
289 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
290 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
291 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
292 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
293 };
294 };
295
296 thermal_zones: thermal-zones {
297 #include "k3-j784s4-thermal.dtsi"
298 };
299 };
300
301 /* Now include peripherals from each bus segment */
302 #include "k3-j784s4-main.dtsi"
303 #include "k3-j784s4-mcu-wakeup.dtsi"
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