1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dts file for KV260 revA Carrier Card
4 *
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15
16 /dts-v1/;
17 /plugin/;
18
19 &{/} {
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
22 "xlnx,zynqmp-sk-kv260-revB",
23 "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
24 model = "ZynqMP KV260 revB";
25
26 ina260-u14 {
27 compatible = "iio-hwmon";
28 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
29 };
30
31 si5332_0: si5332-0 { /* u17 */
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <125000000>;
35 };
36
37 si5332_1: si5332-1 { /* u17 */
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
41 };
42
43 si5332_2: si5332-2 { /* u17 */
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <48000000>;
47 };
48
49 si5332_3: si5332-3 { /* u17 */
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <24000000>;
53 };
54
55 si5332_4: si5332-4 { /* u17 */
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <26000000>;
59 };
60
61 si5332_5: si5332-5 { /* u17 */
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
65 };
66
67 dpcon {
68 compatible = "dp-connector";
69 label = "P11";
70 type = "full-size";
71
72 port {
73 dpcon_in: endpoint {
74 remote-endpoint = <&dpsub_dp_out>;
75 };
76 };
77 };
78 };
79
80 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
81 #address-cells = <1>;
82 #size-cells = <0>;
83 pinctrl-names = "default", "gpio";
84 pinctrl-0 = <&pinctrl_i2c1_default>;
85 pinctrl-1 = <&pinctrl_i2c1_gpio>;
86 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
87 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
88
89 u14: ina260@40 { /* u14 */
90 compatible = "ti,ina260";
91 #io-channel-cells = <1>;
92 label = "ina260-u14";
93 reg = <0x40>;
94 };
95 /* u43 - 0x2d - USB hub */
96 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
97 };
98
99 /* DP/USB 3.0 */
100 &psgtr {
101 status = "okay";
102 /* pcie, usb3, sata */
103 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
104 clock-names = "ref0", "ref1", "ref2";
105 };
106
107 &zynqmp_dpsub {
108 status = "okay";
109 phy-names = "dp-phy0", "dp-phy1";
110 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
111 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
112
113 ports {
114 port@5 {
115 dpsub_dp_out: endpoint {
116 remote-endpoint = <&dpcon_in>;
117 };
118 };
119 };
120 };
121
122 &zynqmp_dpdma {
123 status = "okay";
124 assigned-clock-rates = <600000000>;
125 };
126
127 &usb0 {
128 status = "okay";
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_usb0_default>;
131 phy-names = "usb3-phy";
132 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
133 assigned-clock-rates = <250000000>, <20000000>;
134 };
135
136 &dwc3_0 {
137 status = "okay";
138 dr_mode = "host";
139 snps,usb3_lpm_capable;
140 maximum-speed = "super-speed";
141 };
142
143 &sdhci1 { /* on CC with tuned parameters */
144 status = "okay";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_sdhci1_default>;
147 /*
148 * SD 3.0 requires level shifter and this property
149 * should be removed if the board has level shifter and
150 * need to work in UHS mode
151 */
152 no-1-8-v;
153 disable-wp;
154 xlnx,mio-bank = <1>;
155 clk-phase-sd-hs = <126>, <60>;
156 clk-phase-uhs-sdr25 = <120>, <60>;
157 clk-phase-uhs-ddr50 = <126>, <48>;
158 assigned-clock-rates = <187498123>;
159 bus-width = <4>;
160 };
161
162 &gem3 {
163 status = "okay";
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_gem3_default>;
166 phy-handle = <&phy0>;
167 phy-mode = "rgmii-id";
168 assigned-clock-rates = <250000000>;
169
170 mdio: mdio {
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 phy0: ethernet-phy@1 {
175 #phy-cells = <1>;
176 reg = <1>;
177 compatible = "ethernet-phy-id2000.a231";
178 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
179 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
180 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
181 ti,dp83867-rxctrl-strap-quirk;
182 reset-assert-us = <100>;
183 reset-deassert-us = <280>;
184 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
185 };
186 };
187 };
188
189 &pinctrl0 {
190 status = "okay";
191
192 pinctrl_gpio0_default: gpio0-default {
193 conf {
194 groups = "gpio0_38_grp";
195 bias-pull-up;
196 power-source = <IO_STANDARD_LVCMOS18>;
197 };
198
199 mux {
200 groups = "gpio0_38_grp";
201 function = "gpio0";
202 };
203
204 conf-tx {
205 pins = "MIO38";
206 bias-disable;
207 output-enable;
208 };
209 };
210
211 pinctrl_uart1_default: uart1-default {
212 conf {
213 groups = "uart1_9_grp";
214 slew-rate = <SLEW_RATE_SLOW>;
215 power-source = <IO_STANDARD_LVCMOS18>;
216 drive-strength = <12>;
217 };
218
219 conf-rx {
220 pins = "MIO37";
221 bias-high-impedance;
222 };
223
224 conf-tx {
225 pins = "MIO36";
226 bias-disable;
227 output-enable;
228 };
229
230 mux {
231 groups = "uart1_9_grp";
232 function = "uart1";
233 };
234 };
235
236 pinctrl_i2c1_default: i2c1-default {
237 conf {
238 groups = "i2c1_6_grp";
239 bias-pull-up;
240 slew-rate = <SLEW_RATE_SLOW>;
241 power-source = <IO_STANDARD_LVCMOS18>;
242 };
243
244 mux {
245 groups = "i2c1_6_grp";
246 function = "i2c1";
247 };
248 };
249
250 pinctrl_i2c1_gpio: i2c1-gpio-grp {
251 conf {
252 groups = "gpio0_24_grp", "gpio0_25_grp";
253 slew-rate = <SLEW_RATE_SLOW>;
254 power-source = <IO_STANDARD_LVCMOS18>;
255 };
256
257 mux {
258 groups = "gpio0_24_grp", "gpio0_25_grp";
259 function = "gpio0";
260 };
261 };
262
263 pinctrl_gem3_default: gem3-default {
264 conf {
265 groups = "ethernet3_0_grp";
266 slew-rate = <SLEW_RATE_SLOW>;
267 power-source = <IO_STANDARD_LVCMOS18>;
268 };
269
270 conf-rx {
271 pins = "MIO70", "MIO72", "MIO74";
272 bias-high-impedance;
273 low-power-disable;
274 };
275
276 conf-bootstrap {
277 pins = "MIO71", "MIO73", "MIO75";
278 bias-disable;
279 output-enable;
280 low-power-disable;
281 };
282
283 conf-tx {
284 pins = "MIO64", "MIO65", "MIO66",
285 "MIO67", "MIO68", "MIO69";
286 bias-disable;
287 output-enable;
288 low-power-enable;
289 };
290
291 conf-mdio {
292 groups = "mdio3_0_grp";
293 slew-rate = <SLEW_RATE_SLOW>;
294 power-source = <IO_STANDARD_LVCMOS18>;
295 bias-disable;
296 output-enable;
297 };
298
299 mux-mdio {
300 function = "mdio3";
301 groups = "mdio3_0_grp";
302 };
303
304 mux {
305 function = "ethernet3";
306 groups = "ethernet3_0_grp";
307 };
308 };
309
310 pinctrl_usb0_default: usb0-default {
311 conf {
312 groups = "usb0_0_grp";
313 power-source = <IO_STANDARD_LVCMOS18>;
314 };
315
316 conf-rx {
317 pins = "MIO52", "MIO53", "MIO55";
318 bias-high-impedance;
319 drive-strength = <12>;
320 slew-rate = <SLEW_RATE_FAST>;
321 };
322
323 conf-tx {
324 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
325 "MIO60", "MIO61", "MIO62", "MIO63";
326 bias-disable;
327 output-enable;
328 drive-strength = <4>;
329 slew-rate = <SLEW_RATE_SLOW>;
330 };
331
332 mux {
333 groups = "usb0_0_grp";
334 function = "usb0";
335 };
336 };
337
338 pinctrl_sdhci1_default: sdhci1-default {
339 conf {
340 groups = "sdio1_0_grp";
341 slew-rate = <SLEW_RATE_SLOW>;
342 power-source = <IO_STANDARD_LVCMOS18>;
343 bias-disable;
344 output-enable;
345 };
346
347 conf-cd {
348 groups = "sdio1_cd_0_grp";
349 bias-high-impedance;
350 bias-pull-up;
351 slew-rate = <SLEW_RATE_SLOW>;
352 power-source = <IO_STANDARD_LVCMOS18>;
353 };
354
355 mux-cd {
356 groups = "sdio1_cd_0_grp";
357 function = "sdio1_cd";
358 };
359
360 mux {
361 groups = "sdio1_0_grp";
362 function = "sdio1";
363 };
364 };
365 };
366
367 &gpio {
368 status = "okay";
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_gpio0_default>;
371 };
372
373 &uart1 {
374 status = "okay";
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_uart1_default>;
377 };
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