1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dts file for Xilinx ZynqMP ZCU111
4 *
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11 /dts-v1/;
12
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
19
20 / {
21 model = "ZynqMP ZCU111 RevA";
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
23
24 aliases {
25 ethernet0 = &gem3;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 mmc0 = &sdhci1;
29 nvmem0 = &eeprom;
30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &dcc;
33 spi0 = &qspi;
34 usb0 = &usb0;
35 };
36
37 chosen {
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45 /* Another 4GB connected to PL */
46 };
47
48 gpio-keys {
49 compatible = "gpio-keys";
50 autorepeat;
51 switch-19 {
52 label = "sw19";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN>;
55 wakeup-source;
56 autorepeat;
57 };
58 };
59
60 leds {
61 compatible = "gpio-leds";
62 heartbeat-led {
63 label = "heartbeat";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
66 };
67 };
68
69 ina226-u67 {
70 compatible = "iio-hwmon";
71 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
72 };
73 ina226-u59 {
74 compatible = "iio-hwmon";
75 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
76 };
77 ina226-u61 {
78 compatible = "iio-hwmon";
79 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
80 };
81 ina226-u60 {
82 compatible = "iio-hwmon";
83 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
84 };
85 ina226-u64 {
86 compatible = "iio-hwmon";
87 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
88 };
89 ina226-u69 {
90 compatible = "iio-hwmon";
91 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
92 };
93 ina226-u66 {
94 compatible = "iio-hwmon";
95 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
96 };
97 ina226-u65 {
98 compatible = "iio-hwmon";
99 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
100 };
101 ina226-u63 {
102 compatible = "iio-hwmon";
103 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
104 };
105 ina226-u3 {
106 compatible = "iio-hwmon";
107 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
108 };
109 ina226-u71 {
110 compatible = "iio-hwmon";
111 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
112 };
113 ina226-u77 {
114 compatible = "iio-hwmon";
115 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
116 };
117 ina226-u73 {
118 compatible = "iio-hwmon";
119 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
120 };
121 ina226-u79 {
122 compatible = "iio-hwmon";
123 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
124 };
125
126 /* 48MHz reference crystal */
127 ref48: ref48M {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <48000000>;
131 };
132 };
133
134 &dcc {
135 status = "okay";
136 };
137
138 &fpd_dma_chan1 {
139 status = "okay";
140 };
141
142 &fpd_dma_chan2 {
143 status = "okay";
144 };
145
146 &fpd_dma_chan3 {
147 status = "okay";
148 };
149
150 &fpd_dma_chan4 {
151 status = "okay";
152 };
153
154 &fpd_dma_chan5 {
155 status = "okay";
156 };
157
158 &fpd_dma_chan6 {
159 status = "okay";
160 };
161
162 &fpd_dma_chan7 {
163 status = "okay";
164 };
165
166 &fpd_dma_chan8 {
167 status = "okay";
168 };
169
170 &gem3 {
171 status = "okay";
172 phy-handle = <&phy0>;
173 phy-mode = "rgmii-id";
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_gem3_default>;
176 mdio: mdio {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 phy0: ethernet-phy@c {
180 #phy-cells = <1>;
181 compatible = "ethernet-phy-id2000.a231";
182 reg = <0xc>;
183 ti,rx-internal-delay = <0x8>;
184 ti,tx-internal-delay = <0xa>;
185 ti,fifo-depth = <0x1>;
186 ti,dp83867-rxctrl-strap-quirk;
187 reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
188 };
189 };
190 };
191
192 &gpio {
193 status = "okay";
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_gpio_default>;
196 };
197
198 &gpu {
199 status = "okay";
200 };
201
202 &i2c0 {
203 status = "okay";
204 clock-frequency = <400000>;
205 pinctrl-names = "default", "gpio";
206 pinctrl-0 = <&pinctrl_i2c0_default>;
207 pinctrl-1 = <&pinctrl_i2c0_gpio>;
208 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
209 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
210
211 tca6416_u22: gpio@20 {
212 compatible = "ti,tca6416";
213 reg = <0x20>;
214 gpio-controller; /* interrupt not connected */
215 #gpio-cells = <2>;
216 /*
217 * IRQ not connected
218 * Lines:
219 * 0 - MAX6643_OT_B
220 * 1 - MAX6643_FANFAIL_B
221 * 2 - MIO26_PMU_INPUT_LS
222 * 4 - SFP_SI5382_INT_ALM
223 * 5 - IIC_MUX_RESET_B
224 * 6 - GEM3_EXP_RESET_B
225 * 10 - FMCP_HSPC_PRSNT_M2C_B
226 * 11 - CLK_SPI_MUX_SEL0
227 * 12 - CLK_SPI_MUX_SEL1
228 * 16 - IRPS5401_ALERT_B
229 * 17 - INA226_PMBUS_ALERT
230 * 3, 7, 13-15 - not connected
231 */
232 };
233
234 i2c-mux@75 { /* u23 */
235 compatible = "nxp,pca9544";
236 #address-cells = <1>;
237 #size-cells = <0>;
238 reg = <0x75>;
239 i2c@0 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 reg = <0>;
243 /* PS_PMBUS */
244 /* PMBUS_ALERT done via pca9544 */
245 u67: ina226@40 { /* u67 */
246 compatible = "ti,ina226";
247 #io-channel-cells = <1>;
248 label = "ina226-u67";
249 reg = <0x40>;
250 shunt-resistor = <2000>;
251 };
252 u59: ina226@41 { /* u59 */
253 compatible = "ti,ina226";
254 #io-channel-cells = <1>;
255 label = "ina226-u59";
256 reg = <0x41>;
257 shunt-resistor = <5000>;
258 };
259 u61: ina226@42 { /* u61 */
260 compatible = "ti,ina226";
261 #io-channel-cells = <1>;
262 label = "ina226-u61";
263 reg = <0x42>;
264 shunt-resistor = <5000>;
265 };
266 u60: ina226@43 { /* u60 */
267 compatible = "ti,ina226";
268 #io-channel-cells = <1>;
269 label = "ina226-u60";
270 reg = <0x43>;
271 shunt-resistor = <5000>;
272 };
273 u64: ina226@45 { /* u64 */
274 compatible = "ti,ina226";
275 #io-channel-cells = <1>;
276 label = "ina226-u64";
277 reg = <0x45>;
278 shunt-resistor = <5000>;
279 };
280 u69: ina226@46 { /* u69 */
281 compatible = "ti,ina226";
282 #io-channel-cells = <1>;
283 label = "ina226-u69";
284 reg = <0x46>;
285 shunt-resistor = <2000>;
286 };
287 u66: ina226@47 { /* u66 */
288 compatible = "ti,ina226";
289 #io-channel-cells = <1>;
290 label = "ina226-u66";
291 reg = <0x47>;
292 shunt-resistor = <5000>;
293 };
294 u65: ina226@48 { /* u65 */
295 compatible = "ti,ina226";
296 #io-channel-cells = <1>;
297 label = "ina226-u65";
298 reg = <0x48>;
299 shunt-resistor = <5000>;
300 };
301 u63: ina226@49 { /* u63 */
302 compatible = "ti,ina226";
303 #io-channel-cells = <1>;
304 label = "ina226-u63";
305 reg = <0x49>;
306 shunt-resistor = <5000>;
307 };
308 u3: ina226@4a { /* u3 */
309 compatible = "ti,ina226";
310 #io-channel-cells = <1>;
311 label = "ina226-u3";
312 reg = <0x4a>;
313 shunt-resistor = <5000>;
314 };
315 u71: ina226@4b { /* u71 */
316 compatible = "ti,ina226";
317 #io-channel-cells = <1>;
318 label = "ina226-u71";
319 reg = <0x4b>;
320 shunt-resistor = <5000>;
321 };
322 u77: ina226@4c { /* u77 */
323 compatible = "ti,ina226";
324 #io-channel-cells = <1>;
325 label = "ina226-u77";
326 reg = <0x4c>;
327 shunt-resistor = <5000>;
328 };
329 u73: ina226@4d { /* u73 */
330 compatible = "ti,ina226";
331 #io-channel-cells = <1>;
332 label = "ina226-u73";
333 reg = <0x4d>;
334 shunt-resistor = <5000>;
335 };
336 u79: ina226@4e { /* u79 */
337 compatible = "ti,ina226";
338 #io-channel-cells = <1>;
339 label = "ina226-u79";
340 reg = <0x4e>;
341 shunt-resistor = <5000>;
342 };
343 };
344 i2c@1 {
345 #address-cells = <1>;
346 #size-cells = <0>;
347 reg = <1>;
348 /* NC */
349 };
350 i2c@2 {
351 #address-cells = <1>;
352 #size-cells = <0>;
353 reg = <2>;
354 irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
355 compatible = "infineon,irps5401";
356 reg = <0x43>;
357 };
358 irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
359 compatible = "infineon,irps5401";
360 reg = <0x44>;
361 };
362 irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
363 compatible = "infineon,irps5401";
364 reg = <0x45>;
365 };
366 /* u68 IR38064 +0 */
367 /* u70 IR38060 +1 */
368 /* u74 IR38060 +2 */
369 /* u75 IR38060 +6 */
370 /* J19 header too */
371
372 };
373 i2c@3 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 reg = <3>;
377 /* SYSMON */
378 };
379 };
380 };
381
382 &i2c1 {
383 status = "okay";
384 clock-frequency = <400000>;
385 pinctrl-names = "default", "gpio";
386 pinctrl-0 = <&pinctrl_i2c1_default>;
387 pinctrl-1 = <&pinctrl_i2c1_gpio>;
388 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
389 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
390
391 i2c-mux@74 { /* u26 */
392 compatible = "nxp,pca9548";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 reg = <0x74>;
396 i2c@0 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 reg = <0>;
400 /*
401 * IIC_EEPROM 1kB memory which uses 256B blocks
402 * where every block has different address.
403 * 0 - 256B address 0x54
404 * 256B - 512B address 0x55
405 * 512B - 768B address 0x56
406 * 768B - 1024B address 0x57
407 */
408 eeprom: eeprom@54 { /* u88 */
409 compatible = "atmel,24c08";
410 reg = <0x54>;
411 };
412 };
413 i2c@1 {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 reg = <1>;
417 si5341: clock-generator@36 { /* SI5341 - u46 */
418 compatible = "silabs,si5341";
419 reg = <0x36>;
420 #clock-cells = <2>;
421 #address-cells = <1>;
422 #size-cells = <0>;
423 clocks = <&ref48>;
424 clock-names = "xtal";
425 clock-output-names = "si5341";
426
427 si5341_0: out@0 {
428 /* refclk0 for PS-GT, used for DP */
429 reg = <0>;
430 always-on;
431 };
432 si5341_2: out@2 {
433 /* refclk2 for PS-GT, used for USB3 */
434 reg = <2>;
435 always-on;
436 };
437 si5341_3: out@3 {
438 /* refclk3 for PS-GT, used for SATA */
439 reg = <3>;
440 always-on;
441 };
442 si5341_5: out@5 {
443 /* refclk5 PL CLK100 */
444 reg = <5>;
445 always-on;
446 };
447 si5341_6: out@6 {
448 /* refclk6 PL CLK125 */
449 reg = <6>;
450 always-on;
451 };
452 si5341_9: out@9 {
453 /* refclk9 used for PS_REF_CLK 33.3 MHz */
454 reg = <9>;
455 always-on;
456 };
457 };
458 };
459 i2c@2 {
460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <2>;
463 si570_1: clock-generator@5d { /* USER SI570 - u47 */
464 #clock-cells = <0>;
465 compatible = "silabs,si570";
466 reg = <0x5d>;
467 temperature-stability = <50>;
468 factory-fout = <300000000>;
469 clock-frequency = <300000000>;
470 clock-output-names = "si570_user";
471 };
472 };
473 i2c@3 {
474 #address-cells = <1>;
475 #size-cells = <0>;
476 reg = <3>;
477 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
478 #clock-cells = <0>;
479 compatible = "silabs,si570";
480 reg = <0x5d>;
481 temperature-stability = <50>;
482 factory-fout = <156250000>;
483 clock-frequency = <156250000>;
484 clock-output-names = "si570_mgt";
485 };
486 };
487 i2c@4 {
488 #address-cells = <1>;
489 #size-cells = <0>;
490 reg = <4>;
491 /* SI5382 - u48 */
492 };
493 i2c@5 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 reg = <5>;
497 sc18is603@2f { /* sc18is602 - u93 */
498 compatible = "nxp,sc18is603";
499 reg = <0x2f>;
500 /* 4 gpios for CS not handled by driver */
501 /*
502 * USB2ANY cable or
503 * LMK04208 - u90 or
504 * LMX2594 - u102 or
505 * LMX2594 - u103 or
506 * LMX2594 - u104
507 */
508 };
509 };
510 i2c@6 {
511 #address-cells = <1>;
512 #size-cells = <0>;
513 reg = <6>;
514 /* FMC connector */
515 };
516 /* 7 NC */
517 };
518
519 i2c-mux@75 {
520 compatible = "nxp,pca9548"; /* u27 */
521 #address-cells = <1>;
522 #size-cells = <0>;
523 reg = <0x75>;
524
525 i2c@0 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 reg = <0>;
529 /* FMCP_HSPC_IIC */
530 };
531 i2c@1 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 reg = <1>;
535 /* NC */
536 };
537 i2c@2 {
538 #address-cells = <1>;
539 #size-cells = <0>;
540 reg = <2>;
541 /* SYSMON */
542 };
543 i2c@3 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 reg = <3>;
547 /* DDR4 SODIMM */
548 };
549 i2c@4 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 reg = <4>;
553 /* SFP3 */
554 };
555 i2c@5 {
556 #address-cells = <1>;
557 #size-cells = <0>;
558 reg = <5>;
559 /* SFP2 */
560 };
561 i2c@6 {
562 #address-cells = <1>;
563 #size-cells = <0>;
564 reg = <6>;
565 /* SFP1 */
566 };
567 i2c@7 {
568 #address-cells = <1>;
569 #size-cells = <0>;
570 reg = <7>;
571 /* SFP0 */
572 };
573 };
574 };
575
576 &pinctrl0 {
577 status = "okay";
578 pinctrl_i2c0_default: i2c0-default {
579 mux {
580 groups = "i2c0_3_grp";
581 function = "i2c0";
582 };
583
584 conf {
585 groups = "i2c0_3_grp";
586 bias-pull-up;
587 slew-rate = <SLEW_RATE_SLOW>;
588 power-source = <IO_STANDARD_LVCMOS18>;
589 };
590 };
591
592 pinctrl_i2c0_gpio: i2c0-gpio-grp {
593 mux {
594 groups = "gpio0_14_grp", "gpio0_15_grp";
595 function = "gpio0";
596 };
597
598 conf {
599 groups = "gpio0_14_grp", "gpio0_15_grp";
600 slew-rate = <SLEW_RATE_SLOW>;
601 power-source = <IO_STANDARD_LVCMOS18>;
602 };
603 };
604
605 pinctrl_i2c1_default: i2c1-default {
606 mux {
607 groups = "i2c1_4_grp";
608 function = "i2c1";
609 };
610
611 conf {
612 groups = "i2c1_4_grp";
613 bias-pull-up;
614 slew-rate = <SLEW_RATE_SLOW>;
615 power-source = <IO_STANDARD_LVCMOS18>;
616 };
617 };
618
619 pinctrl_i2c1_gpio: i2c1-gpio-grp {
620 mux {
621 groups = "gpio0_16_grp", "gpio0_17_grp";
622 function = "gpio0";
623 };
624
625 conf {
626 groups = "gpio0_16_grp", "gpio0_17_grp";
627 slew-rate = <SLEW_RATE_SLOW>;
628 power-source = <IO_STANDARD_LVCMOS18>;
629 };
630 };
631
632 pinctrl_uart0_default: uart0-default {
633 mux {
634 groups = "uart0_4_grp";
635 function = "uart0";
636 };
637
638 conf {
639 groups = "uart0_4_grp";
640 slew-rate = <SLEW_RATE_SLOW>;
641 power-source = <IO_STANDARD_LVCMOS18>;
642 };
643
644 conf-rx {
645 pins = "MIO18";
646 bias-high-impedance;
647 };
648
649 conf-tx {
650 pins = "MIO19";
651 bias-disable;
652 };
653 };
654
655 pinctrl_usb0_default: usb0-default {
656 mux {
657 groups = "usb0_0_grp";
658 function = "usb0";
659 };
660
661 conf {
662 groups = "usb0_0_grp";
663 power-source = <IO_STANDARD_LVCMOS18>;
664 };
665
666 conf-rx {
667 pins = "MIO52", "MIO53", "MIO55";
668 bias-high-impedance;
669 drive-strength = <12>;
670 slew-rate = <SLEW_RATE_FAST>;
671 };
672
673 conf-tx {
674 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
675 "MIO60", "MIO61", "MIO62", "MIO63";
676 bias-disable;
677 drive-strength = <4>;
678 slew-rate = <SLEW_RATE_SLOW>;
679 };
680 };
681
682 pinctrl_gem3_default: gem3-default {
683 mux {
684 function = "ethernet3";
685 groups = "ethernet3_0_grp";
686 };
687
688 conf {
689 groups = "ethernet3_0_grp";
690 slew-rate = <SLEW_RATE_SLOW>;
691 power-source = <IO_STANDARD_LVCMOS18>;
692 };
693
694 conf-rx {
695 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
696 "MIO75";
697 bias-high-impedance;
698 low-power-disable;
699 };
700
701 conf-tx {
702 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
703 "MIO69";
704 bias-disable;
705 low-power-enable;
706 };
707
708 mux-mdio {
709 function = "mdio3";
710 groups = "mdio3_0_grp";
711 };
712
713 conf-mdio {
714 groups = "mdio3_0_grp";
715 slew-rate = <SLEW_RATE_SLOW>;
716 power-source = <IO_STANDARD_LVCMOS18>;
717 bias-disable;
718 };
719 };
720
721 pinctrl_sdhci1_default: sdhci1-default {
722 mux {
723 groups = "sdio1_0_grp";
724 function = "sdio1";
725 };
726
727 conf {
728 groups = "sdio1_0_grp";
729 slew-rate = <SLEW_RATE_SLOW>;
730 power-source = <IO_STANDARD_LVCMOS18>;
731 bias-disable;
732 };
733
734 mux-cd {
735 groups = "sdio1_cd_0_grp";
736 function = "sdio1_cd";
737 };
738
739 conf-cd {
740 groups = "sdio1_cd_0_grp";
741 bias-high-impedance;
742 bias-pull-up;
743 slew-rate = <SLEW_RATE_SLOW>;
744 power-source = <IO_STANDARD_LVCMOS18>;
745 };
746 };
747
748 pinctrl_gpio_default: gpio-default {
749 mux {
750 function = "gpio0";
751 groups = "gpio0_22_grp", "gpio0_23_grp";
752 };
753
754 conf {
755 groups = "gpio0_22_grp", "gpio0_23_grp";
756 slew-rate = <SLEW_RATE_SLOW>;
757 power-source = <IO_STANDARD_LVCMOS18>;
758 };
759
760 mux-msp {
761 function = "gpio0";
762 groups = "gpio0_13_grp", "gpio0_38_grp";
763 };
764
765 conf-msp {
766 groups = "gpio0_13_grp", "gpio0_38_grp";
767 slew-rate = <SLEW_RATE_SLOW>;
768 power-source = <IO_STANDARD_LVCMOS18>;
769 };
770
771 conf-pull-up {
772 pins = "MIO22";
773 bias-pull-up;
774 };
775
776 conf-pull-none {
777 pins = "MIO13", "MIO23", "MIO38";
778 bias-disable;
779 };
780 };
781 };
782
783 &psgtr {
784 status = "okay";
785 /* nc, dp, usb3, sata */
786 clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
787 clock-names = "ref1", "ref2", "ref3";
788 };
789
790 &qspi {
791 status = "okay";
792 flash@0 {
793 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
794 #address-cells = <1>;
795 #size-cells = <1>;
796 reg = <0x0>;
797 spi-tx-bus-width = <4>;
798 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
799 spi-max-frequency = <108000000>; /* Based on DC1 spec */
800 };
801 };
802
803 &rtc {
804 status = "okay";
805 };
806
807 &sata {
808 status = "okay";
809 /* SATA OOB timing settings */
810 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
811 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
812 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
813 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
814 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
815 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
816 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
817 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
818 phy-names = "sata-phy";
819 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
820 };
821
822 /* SD1 with level shifter */
823 &sdhci1 {
824 status = "okay";
825 pinctrl-names = "default";
826 pinctrl-0 = <&pinctrl_sdhci1_default>;
827 disable-wp;
828 /*
829 * This property should be removed for supporting UHS mode
830 */
831 no-1-8-v;
832 xlnx,mio-bank = <1>;
833 };
834
835 &uart0 {
836 status = "okay";
837 pinctrl-names = "default";
838 pinctrl-0 = <&pinctrl_uart0_default>;
839 };
840
841 /* ULPI SMSC USB3320 */
842 &usb0 {
843 status = "okay";
844 pinctrl-names = "default";
845 pinctrl-0 = <&pinctrl_usb0_default>;
846 phy-names = "usb3-phy";
847 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
848 };
849
850 &dwc3_0 {
851 status = "okay";
852 dr_mode = "host";
853 snps,usb3_lpm_capable;
854 maximum-speed = "super-speed";
855 };
856
857 &zynqmp_dpdma {
858 status = "okay";
859 };
860
861 &zynqmp_dpsub {
862 status = "okay";
863 phy-names = "dp-phy0", "dp-phy1";
864 phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
865 <&psgtr 0 PHY_TYPE_DP 1 1>;
866 };
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