1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dts file for Xilinx ZynqMP
4 *
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21
22 / {
23 compatible = "xlnx,zynqmp";
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 options {
28 u-boot {
29 compatible = "u-boot,config";
30 bootscr-address = /bits/ 64 <0x20000000>;
31 };
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 compatible = "arm,cortex-a53";
40 device_type = "cpu";
41 enable-method = "psci";
42 operating-points-v2 = <&cpu_opp_table>;
43 reg = <0x0>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 next-level-cache = <&L2>;
46 };
47
48 cpu1: cpu@1 {
49 compatible = "arm,cortex-a53";
50 device_type = "cpu";
51 enable-method = "psci";
52 reg = <0x1>;
53 operating-points-v2 = <&cpu_opp_table>;
54 cpu-idle-states = <&CPU_SLEEP_0>;
55 next-level-cache = <&L2>;
56 };
57
58 cpu2: cpu@2 {
59 compatible = "arm,cortex-a53";
60 device_type = "cpu";
61 enable-method = "psci";
62 reg = <0x2>;
63 operating-points-v2 = <&cpu_opp_table>;
64 cpu-idle-states = <&CPU_SLEEP_0>;
65 next-level-cache = <&L2>;
66 };
67
68 cpu3: cpu@3 {
69 compatible = "arm,cortex-a53";
70 device_type = "cpu";
71 enable-method = "psci";
72 reg = <0x3>;
73 operating-points-v2 = <&cpu_opp_table>;
74 cpu-idle-states = <&CPU_SLEEP_0>;
75 next-level-cache = <&L2>;
76 };
77
78 L2: l2-cache {
79 compatible = "cache";
80 cache-level = <2>;
81 cache-unified;
82 };
83
84 idle-states {
85 entry-method = "psci";
86
87 CPU_SLEEP_0: cpu-sleep-0 {
88 compatible = "arm,idle-state";
89 arm,psci-suspend-param = <0x40000000>;
90 local-timer-stop;
91 entry-latency-us = <300>;
92 exit-latency-us = <600>;
93 min-residency-us = <10000>;
94 };
95 };
96 };
97
98 cpu_opp_table: opp-table-cpu {
99 compatible = "operating-points-v2";
100 opp-shared;
101 opp00 {
102 opp-hz = /bits/ 64 <1199999988>;
103 opp-microvolt = <1000000>;
104 clock-latency-ns = <500000>;
105 };
106 opp01 {
107 opp-hz = /bits/ 64 <599999994>;
108 opp-microvolt = <1000000>;
109 clock-latency-ns = <500000>;
110 };
111 opp02 {
112 opp-hz = /bits/ 64 <399999996>;
113 opp-microvolt = <1000000>;
114 clock-latency-ns = <500000>;
115 };
116 opp03 {
117 opp-hz = /bits/ 64 <299999997>;
118 opp-microvolt = <1000000>;
119 clock-latency-ns = <500000>;
120 };
121 };
122
123 reserved-memory {
124 #address-cells = <2>;
125 #size-cells = <2>;
126 ranges;
127
128 rproc_0_fw_image: memory@3ed00000 {
129 no-map;
130 reg = <0x0 0x3ed00000 0x0 0x40000>;
131 };
132
133 rproc_1_fw_image: memory@3ef00000 {
134 no-map;
135 reg = <0x0 0x3ef00000 0x0 0x40000>;
136 };
137 };
138
139 zynqmp_ipi: zynqmp-ipi {
140 bootph-all;
141 compatible = "xlnx,zynqmp-ipi-mailbox";
142 interrupt-parent = <&gic>;
143 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
144 xlnx,ipi-id = <0>;
145 #address-cells = <2>;
146 #size-cells = <2>;
147 ranges;
148
149 ipi_mailbox_pmu1: mailbox@ff9905c0 {
150 bootph-all;
151 compatible = "xlnx,zynqmp-ipi-dest-mailbox";
152 reg = <0x0 0xff9905c0 0x0 0x20>,
153 <0x0 0xff9905e0 0x0 0x20>,
154 <0x0 0xff990e80 0x0 0x20>,
155 <0x0 0xff990ea0 0x0 0x20>;
156 reg-names = "local_request_region",
157 "local_response_region",
158 "remote_request_region",
159 "remote_response_region";
160 #mbox-cells = <1>;
161 xlnx,ipi-id = <4>;
162 };
163 };
164
165 dcc: dcc {
166 compatible = "arm,dcc";
167 status = "disabled";
168 bootph-all;
169 };
170
171 pmu {
172 compatible = "arm,cortex-a53-pmu";
173 interrupt-parent = <&gic>;
174 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-affinity = <&cpu0>,
179 <&cpu1>,
180 <&cpu2>,
181 <&cpu3>;
182 };
183
184 psci {
185 compatible = "arm,psci-0.2";
186 method = "smc";
187 };
188
189 firmware {
190 optee: optee {
191 compatible = "linaro,optee-tz";
192 method = "smc";
193 };
194
195 zynqmp_firmware: zynqmp-firmware {
196 compatible = "xlnx,zynqmp-firmware";
197 #power-domain-cells = <1>;
198 method = "smc";
199 bootph-all;
200
201 zynqmp_power: power-management {
202 bootph-all;
203 compatible = "xlnx,zynqmp-power";
204 interrupt-parent = <&gic>;
205 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
206 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
207 mbox-names = "tx", "rx";
208 };
209
210 soc-nvmem {
211 compatible = "xlnx,zynqmp-nvmem-fw";
212 nvmem-layout {
213 compatible = "fixed-layout";
214 #address-cells = <1>;
215 #size-cells = <1>;
216
217 soc_revision: soc-revision@0 {
218 reg = <0x0 0x4>;
219 };
220 /* efuse access */
221 efuse_dna: efuse-dna@c {
222 reg = <0xc 0xc>;
223 };
224 efuse_usr0: efuse-usr0@20 {
225 reg = <0x20 0x4>;
226 };
227 efuse_usr1: efuse-usr1@24 {
228 reg = <0x24 0x4>;
229 };
230 efuse_usr2: efuse-usr2@28 {
231 reg = <0x28 0x4>;
232 };
233 efuse_usr3: efuse-usr3@2c {
234 reg = <0x2c 0x4>;
235 };
236 efuse_usr4: efuse-usr4@30 {
237 reg = <0x30 0x4>;
238 };
239 efuse_usr5: efuse-usr5@34 {
240 reg = <0x34 0x4>;
241 };
242 efuse_usr6: efuse-usr6@38 {
243 reg = <0x38 0x4>;
244 };
245 efuse_usr7: efuse-usr7@3c {
246 reg = <0x3c 0x4>;
247 };
248 efuse_miscusr: efuse-miscusr@40 {
249 reg = <0x40 0x4>;
250 };
251 efuse_chash: efuse-chash@50 {
252 reg = <0x50 0x4>;
253 };
254 efuse_pufmisc: efuse-pufmisc@54 {
255 reg = <0x54 0x4>;
256 };
257 efuse_sec: efuse-sec@58 {
258 reg = <0x58 0x4>;
259 };
260 efuse_spkid: efuse-spkid@5c {
261 reg = <0x5c 0x4>;
262 };
263 efuse_aeskey: efuse-aeskey@60 {
264 reg = <0x60 0x20>;
265 };
266 efuse_ppk0hash: efuse-ppk0hash@a0 {
267 reg = <0xa0 0x30>;
268 };
269 efuse_ppk1hash: efuse-ppk1hash@d0 {
270 reg = <0xd0 0x30>;
271 };
272 efuse_pufuser: efuse-pufuser@100 {
273 reg = <0x100 0x7F>;
274 };
275 };
276 };
277
278 zynqmp_pcap: pcap {
279 compatible = "xlnx,zynqmp-pcap-fpga";
280 };
281
282 xlnx_aes: zynqmp-aes {
283 compatible = "xlnx,zynqmp-aes";
284 };
285
286 zynqmp_reset: reset-controller {
287 compatible = "xlnx,zynqmp-reset";
288 #reset-cells = <1>;
289 };
290
291 pinctrl0: pinctrl {
292 compatible = "xlnx,zynqmp-pinctrl";
293 status = "disabled";
294 };
295
296 modepin_gpio: gpio {
297 compatible = "xlnx,zynqmp-gpio-modepin";
298 gpio-controller;
299 #gpio-cells = <2>;
300 };
301 };
302 };
303
304 timer {
305 compatible = "arm,armv8-timer";
306 interrupt-parent = <&gic>;
307 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
308 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
309 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
310 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
311 };
312
313 fpga_full: fpga-region {
314 compatible = "fpga-region";
315 fpga-mgr = <&zynqmp_pcap>;
316 #address-cells = <2>;
317 #size-cells = <2>;
318 ranges;
319 };
320
321 rproc_lockstep: remoteproc@ffe00000 {
322 compatible = "xlnx,zynqmp-r5fss";
323 xlnx,cluster-mode = <1>;
324 xlnx,tcm-mode = <1>;
325
326 #address-cells = <2>;
327 #size-cells = <2>;
328
329 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
330 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
331 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
332 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
333
334 r5f@0 {
335 compatible = "xlnx,zynqmp-r5f";
336 reg = <0x0 0x0 0x0 0x10000>,
337 <0x0 0x20000 0x0 0x10000>,
338 <0x0 0x10000 0x0 0x10000>,
339 <0x0 0x30000 0x0 0x10000>;
340 reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
341 power-domains = <&zynqmp_firmware PD_RPU_0>,
342 <&zynqmp_firmware PD_R5_0_ATCM>,
343 <&zynqmp_firmware PD_R5_0_BTCM>,
344 <&zynqmp_firmware PD_R5_1_ATCM>,
345 <&zynqmp_firmware PD_R5_1_BTCM>;
346 memory-region = <&rproc_0_fw_image>;
347 };
348
349 r5f@1 {
350 compatible = "xlnx,zynqmp-r5f";
351 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
352 reg-names = "atcm0", "btcm0";
353 power-domains = <&zynqmp_firmware PD_RPU_1>,
354 <&zynqmp_firmware PD_R5_1_ATCM>,
355 <&zynqmp_firmware PD_R5_1_BTCM>;
356 memory-region = <&rproc_1_fw_image>;
357 };
358 };
359
360 rproc_split: remoteproc-split@ffe00000 {
361 status = "disabled";
362 compatible = "xlnx,zynqmp-r5fss";
363 xlnx,cluster-mode = <0>;
364 xlnx,tcm-mode = <0>;
365
366 #address-cells = <2>;
367 #size-cells = <2>;
368
369 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
370 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
371 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
372 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
373
374 r5f@0 {
375 compatible = "xlnx,zynqmp-r5f";
376 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
377 reg-names = "atcm0", "btcm0";
378 power-domains = <&zynqmp_firmware PD_RPU_0>,
379 <&zynqmp_firmware PD_R5_0_ATCM>,
380 <&zynqmp_firmware PD_R5_0_BTCM>;
381 memory-region = <&rproc_0_fw_image>;
382 };
383
384 r5f@1 {
385 compatible = "xlnx,zynqmp-r5f";
386 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
387 reg-names = "atcm0", "btcm0";
388 power-domains = <&zynqmp_firmware PD_RPU_1>,
389 <&zynqmp_firmware PD_R5_1_ATCM>,
390 <&zynqmp_firmware PD_R5_1_BTCM>;
391 memory-region = <&rproc_1_fw_image>;
392 };
393 };
394
395 amba: axi {
396 compatible = "simple-bus";
397 bootph-all;
398 #address-cells = <2>;
399 #size-cells = <2>;
400 ranges;
401
402 can0: can@ff060000 {
403 compatible = "xlnx,zynq-can-1.0";
404 status = "disabled";
405 clock-names = "can_clk", "pclk";
406 reg = <0x0 0xff060000 0x0 0x1000>;
407 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
408 interrupt-parent = <&gic>;
409 tx-fifo-depth = <0x40>;
410 rx-fifo-depth = <0x40>;
411 resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
412 power-domains = <&zynqmp_firmware PD_CAN_0>;
413 };
414
415 can1: can@ff070000 {
416 compatible = "xlnx,zynq-can-1.0";
417 status = "disabled";
418 clock-names = "can_clk", "pclk";
419 reg = <0x0 0xff070000 0x0 0x1000>;
420 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-parent = <&gic>;
422 tx-fifo-depth = <0x40>;
423 rx-fifo-depth = <0x40>;
424 resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
425 power-domains = <&zynqmp_firmware PD_CAN_1>;
426 };
427
428 cci: cci@fd6e0000 {
429 compatible = "arm,cci-400";
430 status = "disabled";
431 reg = <0x0 0xfd6e0000 0x0 0x9000>;
432 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
433 #address-cells = <1>;
434 #size-cells = <1>;
435
436 pmu@9000 {
437 compatible = "arm,cci-400-pmu,r1";
438 reg = <0x9000 0x5000>;
439 interrupt-parent = <&gic>;
440 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
445 };
446 };
447
448 cpu0_debug: debug@fec10000 {
449 compatible = "arm,coresight-cpu-debug", "arm,primecell";
450 reg = <0x0 0xfec10000 0x0 0x1000>;
451 clock-names = "apb_pclk";
452 cpu = <&cpu0>;
453 };
454
455 cpu1_debug: debug@fed10000 {
456 compatible = "arm,coresight-cpu-debug", "arm,primecell";
457 reg = <0x0 0xfed10000 0x0 0x1000>;
458 clock-names = "apb_pclk";
459 cpu = <&cpu1>;
460 };
461
462 cpu2_debug: debug@fee10000 {
463 compatible = "arm,coresight-cpu-debug", "arm,primecell";
464 reg = <0x0 0xfee10000 0x0 0x1000>;
465 clock-names = "apb_pclk";
466 cpu = <&cpu2>;
467 };
468
469 cpu3_debug: debug@fef10000 {
470 compatible = "arm,coresight-cpu-debug", "arm,primecell";
471 reg = <0x0 0xfef10000 0x0 0x1000>;
472 clock-names = "apb_pclk";
473 cpu = <&cpu3>;
474 };
475
476 /* GDMA */
477 fpd_dma_chan1: dma-controller@fd500000 {
478 status = "disabled";
479 compatible = "xlnx,zynqmp-dma-1.0";
480 reg = <0x0 0xfd500000 0x0 0x1000>;
481 interrupt-parent = <&gic>;
482 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
483 clock-names = "clk_main", "clk_apb";
484 #dma-cells = <1>;
485 xlnx,bus-width = <128>;
486 /* iommus = <&smmu 0x14e8>; */
487 power-domains = <&zynqmp_firmware PD_GDMA>;
488 };
489
490 fpd_dma_chan2: dma-controller@fd510000 {
491 status = "disabled";
492 compatible = "xlnx,zynqmp-dma-1.0";
493 reg = <0x0 0xfd510000 0x0 0x1000>;
494 interrupt-parent = <&gic>;
495 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
496 clock-names = "clk_main", "clk_apb";
497 #dma-cells = <1>;
498 xlnx,bus-width = <128>;
499 /* iommus = <&smmu 0x14e9>; */
500 power-domains = <&zynqmp_firmware PD_GDMA>;
501 };
502
503 fpd_dma_chan3: dma-controller@fd520000 {
504 status = "disabled";
505 compatible = "xlnx,zynqmp-dma-1.0";
506 reg = <0x0 0xfd520000 0x0 0x1000>;
507 interrupt-parent = <&gic>;
508 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
509 clock-names = "clk_main", "clk_apb";
510 #dma-cells = <1>;
511 xlnx,bus-width = <128>;
512 /* iommus = <&smmu 0x14ea>; */
513 power-domains = <&zynqmp_firmware PD_GDMA>;
514 };
515
516 fpd_dma_chan4: dma-controller@fd530000 {
517 status = "disabled";
518 compatible = "xlnx,zynqmp-dma-1.0";
519 reg = <0x0 0xfd530000 0x0 0x1000>;
520 interrupt-parent = <&gic>;
521 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
522 clock-names = "clk_main", "clk_apb";
523 #dma-cells = <1>;
524 xlnx,bus-width = <128>;
525 /* iommus = <&smmu 0x14eb>; */
526 power-domains = <&zynqmp_firmware PD_GDMA>;
527 };
528
529 fpd_dma_chan5: dma-controller@fd540000 {
530 status = "disabled";
531 compatible = "xlnx,zynqmp-dma-1.0";
532 reg = <0x0 0xfd540000 0x0 0x1000>;
533 interrupt-parent = <&gic>;
534 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
535 clock-names = "clk_main", "clk_apb";
536 #dma-cells = <1>;
537 xlnx,bus-width = <128>;
538 /* iommus = <&smmu 0x14ec>; */
539 power-domains = <&zynqmp_firmware PD_GDMA>;
540 };
541
542 fpd_dma_chan6: dma-controller@fd550000 {
543 status = "disabled";
544 compatible = "xlnx,zynqmp-dma-1.0";
545 reg = <0x0 0xfd550000 0x0 0x1000>;
546 interrupt-parent = <&gic>;
547 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
548 clock-names = "clk_main", "clk_apb";
549 #dma-cells = <1>;
550 xlnx,bus-width = <128>;
551 /* iommus = <&smmu 0x14ed>; */
552 power-domains = <&zynqmp_firmware PD_GDMA>;
553 };
554
555 fpd_dma_chan7: dma-controller@fd560000 {
556 status = "disabled";
557 compatible = "xlnx,zynqmp-dma-1.0";
558 reg = <0x0 0xfd560000 0x0 0x1000>;
559 interrupt-parent = <&gic>;
560 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
561 clock-names = "clk_main", "clk_apb";
562 #dma-cells = <1>;
563 xlnx,bus-width = <128>;
564 /* iommus = <&smmu 0x14ee>; */
565 power-domains = <&zynqmp_firmware PD_GDMA>;
566 };
567
568 fpd_dma_chan8: dma-controller@fd570000 {
569 status = "disabled";
570 compatible = "xlnx,zynqmp-dma-1.0";
571 reg = <0x0 0xfd570000 0x0 0x1000>;
572 interrupt-parent = <&gic>;
573 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
574 clock-names = "clk_main", "clk_apb";
575 #dma-cells = <1>;
576 xlnx,bus-width = <128>;
577 /* iommus = <&smmu 0x14ef>; */
578 power-domains = <&zynqmp_firmware PD_GDMA>;
579 };
580
581 gic: interrupt-controller@f9010000 {
582 compatible = "arm,gic-400";
583 #interrupt-cells = <3>;
584 reg = <0x0 0xf9010000 0x0 0x10000>,
585 <0x0 0xf9020000 0x0 0x20000>,
586 <0x0 0xf9040000 0x0 0x20000>,
587 <0x0 0xf9060000 0x0 0x20000>;
588 interrupt-controller;
589 interrupt-parent = <&gic>;
590 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
591 };
592
593 gpu: gpu@fd4b0000 {
594 status = "disabled";
595 compatible = "xlnx,zynqmp-mali", "arm,mali-400";
596 reg = <0x0 0xfd4b0000 0x0 0x10000>;
597 interrupt-parent = <&gic>;
598 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
604 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
605 clock-names = "bus", "core";
606 power-domains = <&zynqmp_firmware PD_GPU>;
607 };
608
609 /* LPDDMA default allows only secured access. inorder to enable
610 * These dma channels, Users should ensure that these dma
611 * Channels are allowed for non secure access.
612 */
613 lpd_dma_chan1: dma-controller@ffa80000 {
614 status = "disabled";
615 compatible = "xlnx,zynqmp-dma-1.0";
616 reg = <0x0 0xffa80000 0x0 0x1000>;
617 interrupt-parent = <&gic>;
618 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
619 clock-names = "clk_main", "clk_apb";
620 #dma-cells = <1>;
621 xlnx,bus-width = <64>;
622 /* iommus = <&smmu 0x868>; */
623 power-domains = <&zynqmp_firmware PD_ADMA>;
624 };
625
626 lpd_dma_chan2: dma-controller@ffa90000 {
627 status = "disabled";
628 compatible = "xlnx,zynqmp-dma-1.0";
629 reg = <0x0 0xffa90000 0x0 0x1000>;
630 interrupt-parent = <&gic>;
631 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
632 clock-names = "clk_main", "clk_apb";
633 #dma-cells = <1>;
634 xlnx,bus-width = <64>;
635 /* iommus = <&smmu 0x869>; */
636 power-domains = <&zynqmp_firmware PD_ADMA>;
637 };
638
639 lpd_dma_chan3: dma-controller@ffaa0000 {
640 status = "disabled";
641 compatible = "xlnx,zynqmp-dma-1.0";
642 reg = <0x0 0xffaa0000 0x0 0x1000>;
643 interrupt-parent = <&gic>;
644 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
645 clock-names = "clk_main", "clk_apb";
646 #dma-cells = <1>;
647 xlnx,bus-width = <64>;
648 /* iommus = <&smmu 0x86a>; */
649 power-domains = <&zynqmp_firmware PD_ADMA>;
650 };
651
652 lpd_dma_chan4: dma-controller@ffab0000 {
653 status = "disabled";
654 compatible = "xlnx,zynqmp-dma-1.0";
655 reg = <0x0 0xffab0000 0x0 0x1000>;
656 interrupt-parent = <&gic>;
657 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
658 clock-names = "clk_main", "clk_apb";
659 #dma-cells = <1>;
660 xlnx,bus-width = <64>;
661 /* iommus = <&smmu 0x86b>; */
662 power-domains = <&zynqmp_firmware PD_ADMA>;
663 };
664
665 lpd_dma_chan5: dma-controller@ffac0000 {
666 status = "disabled";
667 compatible = "xlnx,zynqmp-dma-1.0";
668 reg = <0x0 0xffac0000 0x0 0x1000>;
669 interrupt-parent = <&gic>;
670 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
671 clock-names = "clk_main", "clk_apb";
672 #dma-cells = <1>;
673 xlnx,bus-width = <64>;
674 /* iommus = <&smmu 0x86c>; */
675 power-domains = <&zynqmp_firmware PD_ADMA>;
676 };
677
678 lpd_dma_chan6: dma-controller@ffad0000 {
679 status = "disabled";
680 compatible = "xlnx,zynqmp-dma-1.0";
681 reg = <0x0 0xffad0000 0x0 0x1000>;
682 interrupt-parent = <&gic>;
683 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
684 clock-names = "clk_main", "clk_apb";
685 #dma-cells = <1>;
686 xlnx,bus-width = <64>;
687 /* iommus = <&smmu 0x86d>; */
688 power-domains = <&zynqmp_firmware PD_ADMA>;
689 };
690
691 lpd_dma_chan7: dma-controller@ffae0000 {
692 status = "disabled";
693 compatible = "xlnx,zynqmp-dma-1.0";
694 reg = <0x0 0xffae0000 0x0 0x1000>;
695 interrupt-parent = <&gic>;
696 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
697 clock-names = "clk_main", "clk_apb";
698 #dma-cells = <1>;
699 xlnx,bus-width = <64>;
700 /* iommus = <&smmu 0x86e>; */
701 power-domains = <&zynqmp_firmware PD_ADMA>;
702 };
703
704 lpd_dma_chan8: dma-controller@ffaf0000 {
705 status = "disabled";
706 compatible = "xlnx,zynqmp-dma-1.0";
707 reg = <0x0 0xffaf0000 0x0 0x1000>;
708 interrupt-parent = <&gic>;
709 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
710 clock-names = "clk_main", "clk_apb";
711 #dma-cells = <1>;
712 xlnx,bus-width = <64>;
713 /* iommus = <&smmu 0x86f>; */
714 power-domains = <&zynqmp_firmware PD_ADMA>;
715 };
716
717 mc: memory-controller@fd070000 {
718 compatible = "xlnx,zynqmp-ddrc-2.40a";
719 reg = <0x0 0xfd070000 0x0 0x30000>;
720 interrupt-parent = <&gic>;
721 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
722 };
723
724 nand0: nand-controller@ff100000 {
725 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
726 status = "disabled";
727 reg = <0x0 0xff100000 0x0 0x1000>;
728 clock-names = "controller", "bus";
729 interrupt-parent = <&gic>;
730 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 /* iommus = <&smmu 0x872>; */
734 power-domains = <&zynqmp_firmware PD_NAND>;
735 };
736
737 gem0: ethernet@ff0b0000 {
738 compatible = "xlnx,zynqmp-gem", "cdns,gem";
739 status = "disabled";
740 interrupt-parent = <&gic>;
741 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
743 reg = <0x0 0xff0b0000 0x0 0x1000>;
744 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
745 /* iommus = <&smmu 0x874>; */
746 power-domains = <&zynqmp_firmware PD_ETH_0>;
747 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
748 reset-names = "gem0_rst";
749 };
750
751 gem1: ethernet@ff0c0000 {
752 compatible = "xlnx,zynqmp-gem", "cdns,gem";
753 status = "disabled";
754 interrupt-parent = <&gic>;
755 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
757 reg = <0x0 0xff0c0000 0x0 0x1000>;
758 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
759 /* iommus = <&smmu 0x875>; */
760 power-domains = <&zynqmp_firmware PD_ETH_1>;
761 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
762 reset-names = "gem1_rst";
763 };
764
765 gem2: ethernet@ff0d0000 {
766 compatible = "xlnx,zynqmp-gem", "cdns,gem";
767 status = "disabled";
768 interrupt-parent = <&gic>;
769 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
771 reg = <0x0 0xff0d0000 0x0 0x1000>;
772 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
773 /* iommus = <&smmu 0x876>; */
774 power-domains = <&zynqmp_firmware PD_ETH_2>;
775 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
776 reset-names = "gem2_rst";
777 };
778
779 gem3: ethernet@ff0e0000 {
780 compatible = "xlnx,zynqmp-gem", "cdns,gem";
781 status = "disabled";
782 interrupt-parent = <&gic>;
783 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
785 reg = <0x0 0xff0e0000 0x0 0x1000>;
786 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
787 /* iommus = <&smmu 0x877>; */
788 power-domains = <&zynqmp_firmware PD_ETH_3>;
789 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
790 reset-names = "gem3_rst";
791 };
792
793 gpio: gpio@ff0a0000 {
794 compatible = "xlnx,zynqmp-gpio-1.0";
795 status = "disabled";
796 #gpio-cells = <0x2>;
797 gpio-controller;
798 interrupt-parent = <&gic>;
799 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
800 interrupt-controller;
801 #interrupt-cells = <2>;
802 reg = <0x0 0xff0a0000 0x0 0x1000>;
803 power-domains = <&zynqmp_firmware PD_GPIO>;
804 };
805
806 i2c0: i2c@ff020000 {
807 compatible = "cdns,i2c-r1p14";
808 status = "disabled";
809 interrupt-parent = <&gic>;
810 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
811 clock-frequency = <400000>;
812 reg = <0x0 0xff020000 0x0 0x1000>;
813 #address-cells = <1>;
814 #size-cells = <0>;
815 power-domains = <&zynqmp_firmware PD_I2C_0>;
816 };
817
818 i2c1: i2c@ff030000 {
819 compatible = "cdns,i2c-r1p14";
820 status = "disabled";
821 interrupt-parent = <&gic>;
822 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
823 clock-frequency = <400000>;
824 reg = <0x0 0xff030000 0x0 0x1000>;
825 #address-cells = <1>;
826 #size-cells = <0>;
827 power-domains = <&zynqmp_firmware PD_I2C_1>;
828 };
829
830 ocm: memory-controller@ff960000 {
831 compatible = "xlnx,zynqmp-ocmc-1.0";
832 reg = <0x0 0xff960000 0x0 0x1000>;
833 interrupt-parent = <&gic>;
834 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
835 };
836
837 pcie: pcie@fd0e0000 {
838 compatible = "xlnx,nwl-pcie-2.11";
839 status = "disabled";
840 #address-cells = <3>;
841 #size-cells = <2>;
842 #interrupt-cells = <1>;
843 msi-controller;
844 device_type = "pci";
845 interrupt-parent = <&gic>;
846 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */
850 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
851 interrupt-names = "misc", "dummy", "intx",
852 "msi1", "msi0";
853 msi-parent = <&pcie>;
854 reg = <0x0 0xfd0e0000 0x0 0x1000>,
855 <0x0 0xfd480000 0x0 0x1000>,
856 <0x80 0x00000000 0x0 0x10000000>;
857 reg-names = "breg", "pcireg", "cfg";
858 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
859 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
860 bus-range = <0x00 0xff>;
861 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
862 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
863 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
864 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
865 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
866 /* iommus = <&smmu 0x4d0>; */
867 power-domains = <&zynqmp_firmware PD_PCIE>;
868 pcie_intc: legacy-interrupt-controller {
869 interrupt-controller;
870 #address-cells = <0>;
871 #interrupt-cells = <1>;
872 };
873 };
874
875 qspi: spi@ff0f0000 {
876 bootph-all;
877 compatible = "xlnx,zynqmp-qspi-1.0";
878 status = "disabled";
879 clock-names = "ref_clk", "pclk";
880 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
881 interrupt-parent = <&gic>;
882 num-cs = <1>;
883 reg = <0x0 0xff0f0000 0x0 0x1000>,
884 <0x0 0xc0000000 0x0 0x8000000>;
885 #address-cells = <1>;
886 #size-cells = <0>;
887 /* iommus = <&smmu 0x873>; */
888 power-domains = <&zynqmp_firmware PD_QSPI>;
889 };
890
891 psgtr: phy@fd400000 {
892 compatible = "xlnx,zynqmp-psgtr-v1.1";
893 status = "disabled";
894 reg = <0x0 0xfd400000 0x0 0x40000>,
895 <0x0 0xfd3d0000 0x0 0x1000>;
896 reg-names = "serdes", "siou";
897 #phy-cells = <4>;
898 };
899
900 rtc: rtc@ffa60000 {
901 compatible = "xlnx,zynqmp-rtc";
902 status = "disabled";
903 reg = <0x0 0xffa60000 0x0 0x100>;
904 interrupt-parent = <&gic>;
905 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
907 interrupt-names = "alarm", "sec";
908 calibration = <0x7FFF>;
909 };
910
911 sata: ahci@fd0c0000 {
912 compatible = "ceva,ahci-1v84";
913 status = "disabled";
914 reg = <0x0 0xfd0c0000 0x0 0x2000>;
915 interrupt-parent = <&gic>;
916 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
917 power-domains = <&zynqmp_firmware PD_SATA>;
918 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
919 /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
920 };
921
922 sdhci0: mmc@ff160000 {
923 bootph-all;
924 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
925 status = "disabled";
926 interrupt-parent = <&gic>;
927 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
928 reg = <0x0 0xff160000 0x0 0x1000>;
929 clock-names = "clk_xin", "clk_ahb";
930 /* iommus = <&smmu 0x870>; */
931 #clock-cells = <1>;
932 clock-output-names = "clk_out_sd0", "clk_in_sd0";
933 power-domains = <&zynqmp_firmware PD_SD_0>;
934 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
935 };
936
937 sdhci1: mmc@ff170000 {
938 bootph-all;
939 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
940 status = "disabled";
941 interrupt-parent = <&gic>;
942 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
943 reg = <0x0 0xff170000 0x0 0x1000>;
944 clock-names = "clk_xin", "clk_ahb";
945 /* iommus = <&smmu 0x871>; */
946 #clock-cells = <1>;
947 clock-output-names = "clk_out_sd1", "clk_in_sd1";
948 power-domains = <&zynqmp_firmware PD_SD_1>;
949 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
950 };
951
952 smmu: iommu@fd800000 {
953 compatible = "arm,mmu-500";
954 reg = <0x0 0xfd800000 0x0 0x20000>;
955 #iommu-cells = <1>;
956 status = "disabled";
957 #global-interrupts = <1>;
958 interrupt-parent = <&gic>;
959 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
976 };
977
978 spi0: spi@ff040000 {
979 compatible = "cdns,spi-r1p6";
980 status = "disabled";
981 interrupt-parent = <&gic>;
982 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
983 reg = <0x0 0xff040000 0x0 0x1000>;
984 clock-names = "ref_clk", "pclk";
985 #address-cells = <1>;
986 #size-cells = <0>;
987 power-domains = <&zynqmp_firmware PD_SPI_0>;
988 };
989
990 spi1: spi@ff050000 {
991 compatible = "cdns,spi-r1p6";
992 status = "disabled";
993 interrupt-parent = <&gic>;
994 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
995 reg = <0x0 0xff050000 0x0 0x1000>;
996 clock-names = "ref_clk", "pclk";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 power-domains = <&zynqmp_firmware PD_SPI_1>;
1000 };
1001
1002 ttc0: timer@ff110000 {
1003 compatible = "cdns,ttc";
1004 status = "disabled";
1005 interrupt-parent = <&gic>;
1006 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1009 reg = <0x0 0xff110000 0x0 0x1000>;
1010 timer-width = <32>;
1011 power-domains = <&zynqmp_firmware PD_TTC_0>;
1012 };
1013
1014 ttc1: timer@ff120000 {
1015 compatible = "cdns,ttc";
1016 status = "disabled";
1017 interrupt-parent = <&gic>;
1018 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1021 reg = <0x0 0xff120000 0x0 0x1000>;
1022 timer-width = <32>;
1023 power-domains = <&zynqmp_firmware PD_TTC_1>;
1024 };
1025
1026 ttc2: timer@ff130000 {
1027 compatible = "cdns,ttc";
1028 status = "disabled";
1029 interrupt-parent = <&gic>;
1030 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1033 reg = <0x0 0xff130000 0x0 0x1000>;
1034 timer-width = <32>;
1035 power-domains = <&zynqmp_firmware PD_TTC_2>;
1036 };
1037
1038 ttc3: timer@ff140000 {
1039 compatible = "cdns,ttc";
1040 status = "disabled";
1041 interrupt-parent = <&gic>;
1042 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1045 reg = <0x0 0xff140000 0x0 0x1000>;
1046 timer-width = <32>;
1047 power-domains = <&zynqmp_firmware PD_TTC_3>;
1048 };
1049
1050 uart0: serial@ff000000 {
1051 bootph-all;
1052 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
1053 status = "disabled";
1054 interrupt-parent = <&gic>;
1055 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1056 reg = <0x0 0xff000000 0x0 0x1000>;
1057 clock-names = "uart_clk", "pclk";
1058 power-domains = <&zynqmp_firmware PD_UART_0>;
1059 resets = <&zynqmp_reset ZYNQMP_RESET_UART0>;
1060 };
1061
1062 uart1: serial@ff010000 {
1063 bootph-all;
1064 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
1065 status = "disabled";
1066 interrupt-parent = <&gic>;
1067 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1068 reg = <0x0 0xff010000 0x0 0x1000>;
1069 clock-names = "uart_clk", "pclk";
1070 power-domains = <&zynqmp_firmware PD_UART_1>;
1071 resets = <&zynqmp_reset ZYNQMP_RESET_UART1>;
1072 };
1073
1074 usb0: usb@ff9d0000 {
1075 #address-cells = <2>;
1076 #size-cells = <2>;
1077 status = "disabled";
1078 compatible = "xlnx,zynqmp-dwc3";
1079 reg = <0x0 0xff9d0000 0x0 0x100>;
1080 clock-names = "bus_clk", "ref_clk";
1081 power-domains = <&zynqmp_firmware PD_USB_0>;
1082 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
1083 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
1084 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
1085 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
1086 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
1087 ranges;
1088
1089 dwc3_0: usb@fe200000 {
1090 compatible = "snps,dwc3";
1091 status = "disabled";
1092 reg = <0x0 0xfe200000 0x0 0x40000>;
1093 interrupt-parent = <&gic>;
1094 interrupt-names = "host", "peripheral", "otg", "wakeup";
1095 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1099 clock-names = "ref";
1100 /* iommus = <&smmu 0x860>; */
1101 snps,quirk-frame-length-adjustment = <0x20>;
1102 snps,resume-hs-terminations;
1103 /* dma-coherent; */
1104 };
1105 };
1106
1107 usb1: usb@ff9e0000 {
1108 #address-cells = <2>;
1109 #size-cells = <2>;
1110 status = "disabled";
1111 compatible = "xlnx,zynqmp-dwc3";
1112 reg = <0x0 0xff9e0000 0x0 0x100>;
1113 clock-names = "bus_clk", "ref_clk";
1114 power-domains = <&zynqmp_firmware PD_USB_1>;
1115 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
1116 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
1117 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
1118 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
1119 ranges;
1120
1121 dwc3_1: usb@fe300000 {
1122 compatible = "snps,dwc3";
1123 status = "disabled";
1124 reg = <0x0 0xfe300000 0x0 0x40000>;
1125 interrupt-parent = <&gic>;
1126 interrupt-names = "host", "peripheral", "otg", "wakeup";
1127 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1128 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1131 clock-names = "ref";
1132 /* iommus = <&smmu 0x861>; */
1133 snps,quirk-frame-length-adjustment = <0x20>;
1134 snps,resume-hs-terminations;
1135 /* dma-coherent; */
1136 };
1137 };
1138
1139 watchdog0: watchdog@fd4d0000 {
1140 compatible = "cdns,wdt-r1p2";
1141 status = "disabled";
1142 interrupt-parent = <&gic>;
1143 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
1144 reg = <0x0 0xfd4d0000 0x0 0x1000>;
1145 timeout-sec = <60>;
1146 reset-on-timeout;
1147 };
1148
1149 lpd_watchdog: watchdog@ff150000 {
1150 compatible = "cdns,wdt-r1p2";
1151 status = "disabled";
1152 interrupt-parent = <&gic>;
1153 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
1154 reg = <0x0 0xff150000 0x0 0x1000>;
1155 timeout-sec = <10>;
1156 };
1157
1158 xilinx_ams: ams@ffa50000 {
1159 compatible = "xlnx,zynqmp-ams";
1160 status = "disabled";
1161 interrupt-parent = <&gic>;
1162 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1163 reg = <0x0 0xffa50000 0x0 0x800>;
1164 #address-cells = <1>;
1165 #size-cells = <1>;
1166 #io-channel-cells = <1>;
1167 ranges = <0 0 0xffa50800 0x800>;
1168
1169 ams_ps: ams-ps@0 {
1170 compatible = "xlnx,zynqmp-ams-ps";
1171 status = "disabled";
1172 reg = <0x0 0x400>;
1173 };
1174
1175 ams_pl: ams-pl@400 {
1176 compatible = "xlnx,zynqmp-ams-pl";
1177 status = "disabled";
1178 reg = <0x400 0x400>;
1179 };
1180 };
1181
1182 zynqmp_dpdma: dma-controller@fd4c0000 {
1183 compatible = "xlnx,zynqmp-dpdma";
1184 status = "disabled";
1185 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1186 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1187 interrupt-parent = <&gic>;
1188 clock-names = "axi_clk";
1189 power-domains = <&zynqmp_firmware PD_DP>;
1190 /* iommus = <&smmu 0xce4>; */
1191 #dma-cells = <1>;
1192 };
1193
1194 zynqmp_dpsub: display@fd4a0000 {
1195 bootph-all;
1196 compatible = "xlnx,zynqmp-dpsub-1.7";
1197 status = "disabled";
1198 reg = <0x0 0xfd4a0000 0x0 0x1000>,
1199 <0x0 0xfd4aa000 0x0 0x1000>,
1200 <0x0 0xfd4ab000 0x0 0x1000>,
1201 <0x0 0xfd4ac000 0x0 0x1000>;
1202 reg-names = "dp", "blend", "av_buf", "aud";
1203 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1204 interrupt-parent = <&gic>;
1205 /* iommus = <&smmu 0xce3>; */
1206 clock-names = "dp_apb_clk", "dp_aud_clk",
1207 "dp_vtc_pixel_clk_in";
1208 power-domains = <&zynqmp_firmware PD_DP>;
1209 resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
1210 dma-names = "vid0", "vid1", "vid2", "gfx0";
1211 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
1212 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
1213 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
1214 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
1215
1216 ports {
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219
1220 port@0 {
1221 reg = <0>;
1222 };
1223 port@1 {
1224 reg = <1>;
1225 };
1226 port@2 {
1227 reg = <2>;
1228 };
1229 port@3 {
1230 reg = <3>;
1231 };
1232 port@4 {
1233 reg = <4>;
1234 };
1235 port@5 {
1236 reg = <5>;
1237 };
1238 };
1239 };
1240 };
1241 };
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