1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Device Tree binding constants for Actions Semi S500 Clock Management Unit 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Copyright (c) 2018 LSI-TEC - Caninos Loucos 7 */ 8 9 #ifndef __DT_BINDINGS_CLOCK_S500_CMU_H 10 #define __DT_BINDINGS_CLOCK_S500_CMU_H 11 12 #define CLK_NONE 0 13 14 /* fixed rate clocks */ 15 #define CLK_LOSC 1 16 #define CLK_HOSC 2 17 18 /* pll clocks */ 19 #define CLK_CORE_PLL 3 20 #define CLK_DEV_PLL 4 21 #define CLK_DDR_PLL 5 22 #define CLK_NAND_PLL 6 23 #define CLK_DISPLAY_PLL 7 24 #define CLK_ETHERNET_PLL 8 25 #define CLK_AUDIO_PLL 9 26 27 /* system clock */ 28 #define CLK_DEV 10 29 #define CLK_H 11 30 #define CLK_AHBPREDIV 12 31 #define CLK_AHB 13 32 #define CLK_DE 14 33 #define CLK_BISP 15 34 #define CLK_VCE 16 35 #define CLK_VDE 17 36 37 /* peripheral device clock */ 38 #define CLK_TIMER 18 39 #define CLK_I2C0 19 40 #define CLK_I2C1 20 41 #define CLK_I2C2 21 42 #define CLK_I2C3 22 43 #define CLK_PWM0 23 44 #define CLK_PWM1 24 45 #define CLK_PWM2 25 46 #define CLK_PWM3 26 47 #define CLK_PWM4 27 48 #define CLK_PWM5 28 49 #define CLK_SD0 29 50 #define CLK_SD1 30 51 #define CLK_SD2 31 52 #define CLK_SENSOR0 32 53 #define CLK_SENSOR1 33 54 #define CLK_SPI0 34 55 #define CLK_SPI1 35 56 #define CLK_SPI2 36 57 #define CLK_SPI3 37 58 #define CLK_UART0 38 59 #define CLK_UART1 39 60 #define CLK_UART2 40 61 #define CLK_UART3 41 62 #define CLK_UART4 42 63 #define CLK_UART5 43 64 #define CLK_UART6 44 65 #define CLK_DE1 45 66 #define CLK_DE2 46 67 #define CLK_I2SRX 47 68 #define CLK_I2STX 48 69 #define CLK_HDMI_AUDIO 49 70 #define CLK_HDMI 50 71 #define CLK_SPDIF 51 72 #define CLK_NAND 52 73 #define CLK_ECC 53 74 #define CLK_RMII_REF 54 75 #define CLK_GPIO 55 76 77 /* additional clocks */ 78 #define CLK_APB 56 79 #define CLK_DMAC 57 80 #define CLK_NIC 58 81 #define CLK_ETHERNET 59 82 83 #define CLK_NR_CLKS (CLK_ETHERNET + 1) 84 85 #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ 86
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