1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H 7 #define __DT_BINDINGS_CLOCK_IMX6QDL_H 8 9 #define IMX6QDL_CLK_DUMMY 0 10 #define IMX6QDL_CLK_CKIL 1 11 #define IMX6QDL_CLK_CKIH 2 12 #define IMX6QDL_CLK_OSC 3 13 #define IMX6QDL_CLK_PLL2_PFD0_352M 4 14 #define IMX6QDL_CLK_PLL2_PFD1_594M 5 15 #define IMX6QDL_CLK_PLL2_PFD2_396M 6 16 #define IMX6QDL_CLK_PLL3_PFD0_720M 7 17 #define IMX6QDL_CLK_PLL3_PFD1_540M 8 18 #define IMX6QDL_CLK_PLL3_PFD2_508M 9 19 #define IMX6QDL_CLK_PLL3_PFD3_454M 10 20 #define IMX6QDL_CLK_PLL2_198M 11 21 #define IMX6QDL_CLK_PLL3_120M 12 22 #define IMX6QDL_CLK_PLL3_80M 13 23 #define IMX6QDL_CLK_PLL3_60M 14 24 #define IMX6QDL_CLK_TWD 15 25 #define IMX6QDL_CLK_STEP 16 26 #define IMX6QDL_CLK_PLL1_SW 17 27 #define IMX6QDL_CLK_PERIPH_PRE 18 28 #define IMX6QDL_CLK_PERIPH2_PRE 19 29 #define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 30 #define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 31 #define IMX6QDL_CLK_AXI_SEL 22 32 #define IMX6QDL_CLK_ESAI_SEL 23 33 #define IMX6QDL_CLK_ASRC_SEL 24 34 #define IMX6QDL_CLK_SPDIF_SEL 25 35 #define IMX6QDL_CLK_GPU2D_AXI 26 36 #define IMX6QDL_CLK_GPU3D_AXI 27 37 #define IMX6QDL_CLK_GPU2D_CORE_SEL 28 38 #define IMX6QDL_CLK_GPU3D_CORE_SEL 29 39 #define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 40 #define IMX6QDL_CLK_IPU1_SEL 31 41 #define IMX6QDL_CLK_IPU2_SEL 32 42 #define IMX6QDL_CLK_LDB_DI0_SEL 33 43 #define IMX6QDL_CLK_LDB_DI1_SEL 34 44 #define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 45 #define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 46 #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 47 #define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 48 #define IMX6QDL_CLK_IPU1_DI0_SEL 39 49 #define IMX6QDL_CLK_IPU1_DI1_SEL 40 50 #define IMX6QDL_CLK_IPU2_DI0_SEL 41 51 #define IMX6QDL_CLK_IPU2_DI1_SEL 42 52 #define IMX6QDL_CLK_HSI_TX_SEL 43 53 #define IMX6QDL_CLK_PCIE_AXI_SEL 44 54 #define IMX6QDL_CLK_SSI1_SEL 45 55 #define IMX6QDL_CLK_SSI2_SEL 46 56 #define IMX6QDL_CLK_SSI3_SEL 47 57 #define IMX6QDL_CLK_USDHC1_SEL 48 58 #define IMX6QDL_CLK_USDHC2_SEL 49 59 #define IMX6QDL_CLK_USDHC3_SEL 50 60 #define IMX6QDL_CLK_USDHC4_SEL 51 61 #define IMX6QDL_CLK_ENFC_SEL 52 62 #define IMX6QDL_CLK_EIM_SEL 53 63 #define IMX6QDL_CLK_EIM_SLOW_SEL 54 64 #define IMX6QDL_CLK_VDO_AXI_SEL 55 65 #define IMX6QDL_CLK_VPU_AXI_SEL 56 66 #define IMX6QDL_CLK_CKO1_SEL 57 67 #define IMX6QDL_CLK_PERIPH 58 68 #define IMX6QDL_CLK_PERIPH2 59 69 #define IMX6QDL_CLK_PERIPH_CLK2 60 70 #define IMX6QDL_CLK_PERIPH2_CLK2 61 71 #define IMX6QDL_CLK_IPG 62 72 #define IMX6QDL_CLK_IPG_PER 63 73 #define IMX6QDL_CLK_ESAI_PRED 64 74 #define IMX6QDL_CLK_ESAI_PODF 65 75 #define IMX6QDL_CLK_ASRC_PRED 66 76 #define IMX6QDL_CLK_ASRC_PODF 67 77 #define IMX6QDL_CLK_SPDIF_PRED 68 78 #define IMX6QDL_CLK_SPDIF_PODF 69 79 #define IMX6QDL_CLK_CAN_ROOT 70 80 #define IMX6QDL_CLK_ECSPI_ROOT 71 81 #define IMX6QDL_CLK_GPU2D_CORE_PODF 72 82 #define IMX6QDL_CLK_GPU3D_CORE_PODF 73 83 #define IMX6QDL_CLK_GPU3D_SHADER 74 84 #define IMX6QDL_CLK_IPU1_PODF 75 85 #define IMX6QDL_CLK_IPU2_PODF 76 86 #define IMX6QDL_CLK_LDB_DI0_PODF 77 87 #define IMX6QDL_CLK_LDB_DI1_PODF 78 88 #define IMX6QDL_CLK_IPU1_DI0_PRE 79 89 #define IMX6QDL_CLK_IPU1_DI1_PRE 80 90 #define IMX6QDL_CLK_IPU2_DI0_PRE 81 91 #define IMX6QDL_CLK_IPU2_DI1_PRE 82 92 #define IMX6QDL_CLK_HSI_TX_PODF 83 93 #define IMX6QDL_CLK_SSI1_PRED 84 94 #define IMX6QDL_CLK_SSI1_PODF 85 95 #define IMX6QDL_CLK_SSI2_PRED 86 96 #define IMX6QDL_CLK_SSI2_PODF 87 97 #define IMX6QDL_CLK_SSI3_PRED 88 98 #define IMX6QDL_CLK_SSI3_PODF 89 99 #define IMX6QDL_CLK_UART_SERIAL_PODF 90 100 #define IMX6QDL_CLK_USDHC1_PODF 91 101 #define IMX6QDL_CLK_USDHC2_PODF 92 102 #define IMX6QDL_CLK_USDHC3_PODF 93 103 #define IMX6QDL_CLK_USDHC4_PODF 94 104 #define IMX6QDL_CLK_ENFC_PRED 95 105 #define IMX6QDL_CLK_ENFC_PODF 96 106 #define IMX6QDL_CLK_EIM_PODF 97 107 #define IMX6QDL_CLK_EIM_SLOW_PODF 98 108 #define IMX6QDL_CLK_VPU_AXI_PODF 99 109 #define IMX6QDL_CLK_CKO1_PODF 100 110 #define IMX6QDL_CLK_AXI 101 111 #define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 112 #define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 113 #define IMX6QDL_CLK_ARM 104 114 #define IMX6QDL_CLK_AHB 105 115 #define IMX6QDL_CLK_APBH_DMA 106 116 #define IMX6QDL_CLK_ASRC 107 117 #define IMX6QDL_CLK_CAN1_IPG 108 118 #define IMX6QDL_CLK_CAN1_SERIAL 109 119 #define IMX6QDL_CLK_CAN2_IPG 110 120 #define IMX6QDL_CLK_CAN2_SERIAL 111 121 #define IMX6QDL_CLK_ECSPI1 112 122 #define IMX6QDL_CLK_ECSPI2 113 123 #define IMX6QDL_CLK_ECSPI3 114 124 #define IMX6QDL_CLK_ECSPI4 115 125 #define IMX6Q_CLK_ECSPI5 116 126 #define IMX6DL_CLK_I2C4 116 127 #define IMX6QDL_CLK_ENET 117 128 #define IMX6QDL_CLK_ESAI_EXTAL 118 129 #define IMX6QDL_CLK_GPT_IPG 119 130 #define IMX6QDL_CLK_GPT_IPG_PER 120 131 #define IMX6QDL_CLK_GPU2D_CORE 121 132 #define IMX6QDL_CLK_GPU3D_CORE 122 133 #define IMX6QDL_CLK_HDMI_IAHB 123 134 #define IMX6QDL_CLK_HDMI_ISFR 124 135 #define IMX6QDL_CLK_I2C1 125 136 #define IMX6QDL_CLK_I2C2 126 137 #define IMX6QDL_CLK_I2C3 127 138 #define IMX6QDL_CLK_IIM 128 139 #define IMX6QDL_CLK_ENFC 129 140 #define IMX6QDL_CLK_IPU1 130 141 #define IMX6QDL_CLK_IPU1_DI0 131 142 #define IMX6QDL_CLK_IPU1_DI1 132 143 #define IMX6QDL_CLK_IPU2 133 144 #define IMX6QDL_CLK_IPU2_DI0 134 145 #define IMX6QDL_CLK_LDB_DI0 135 146 #define IMX6QDL_CLK_LDB_DI1 136 147 #define IMX6QDL_CLK_IPU2_DI1 137 148 #define IMX6QDL_CLK_HSI_TX 138 149 #define IMX6QDL_CLK_MLB 139 150 #define IMX6QDL_CLK_MMDC_CH0_AXI 140 151 #define IMX6QDL_CLK_MMDC_CH1_AXI 141 152 #define IMX6QDL_CLK_OCRAM 142 153 #define IMX6QDL_CLK_OPENVG_AXI 143 154 #define IMX6QDL_CLK_PCIE_AXI 144 155 #define IMX6QDL_CLK_PWM1 145 156 #define IMX6QDL_CLK_PWM2 146 157 #define IMX6QDL_CLK_PWM3 147 158 #define IMX6QDL_CLK_PWM4 148 159 #define IMX6QDL_CLK_PER1_BCH 149 160 #define IMX6QDL_CLK_GPMI_BCH_APB 150 161 #define IMX6QDL_CLK_GPMI_BCH 151 162 #define IMX6QDL_CLK_GPMI_IO 152 163 #define IMX6QDL_CLK_GPMI_APB 153 164 #define IMX6QDL_CLK_SATA 154 165 #define IMX6QDL_CLK_SDMA 155 166 #define IMX6QDL_CLK_SPBA 156 167 #define IMX6QDL_CLK_SSI1 157 168 #define IMX6QDL_CLK_SSI2 158 169 #define IMX6QDL_CLK_SSI3 159 170 #define IMX6QDL_CLK_UART_IPG 160 171 #define IMX6QDL_CLK_UART_SERIAL 161 172 #define IMX6QDL_CLK_USBOH3 162 173 #define IMX6QDL_CLK_USDHC1 163 174 #define IMX6QDL_CLK_USDHC2 164 175 #define IMX6QDL_CLK_USDHC3 165 176 #define IMX6QDL_CLK_USDHC4 166 177 #define IMX6QDL_CLK_VDO_AXI 167 178 #define IMX6QDL_CLK_VPU_AXI 168 179 #define IMX6QDL_CLK_CKO1 169 180 #define IMX6QDL_CLK_PLL1_SYS 170 181 #define IMX6QDL_CLK_PLL2_BUS 171 182 #define IMX6QDL_CLK_PLL3_USB_OTG 172 183 #define IMX6QDL_CLK_PLL4_AUDIO 173 184 #define IMX6QDL_CLK_PLL5_VIDEO 174 185 #define IMX6QDL_CLK_PLL8_MLB 175 186 #define IMX6QDL_CLK_PLL7_USB_HOST 176 187 #define IMX6QDL_CLK_PLL6_ENET 177 188 #define IMX6QDL_CLK_SSI1_IPG 178 189 #define IMX6QDL_CLK_SSI2_IPG 179 190 #define IMX6QDL_CLK_SSI3_IPG 180 191 #define IMX6QDL_CLK_ROM 181 192 #define IMX6QDL_CLK_USBPHY1 182 193 #define IMX6QDL_CLK_USBPHY2 183 194 #define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 195 #define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 196 #define IMX6QDL_CLK_SATA_REF 186 197 #define IMX6QDL_CLK_SATA_REF_100M 187 198 #define IMX6QDL_CLK_PCIE_REF 188 199 #define IMX6QDL_CLK_PCIE_REF_125M 189 200 #define IMX6QDL_CLK_ENET_REF 190 201 #define IMX6QDL_CLK_USBPHY1_GATE 191 202 #define IMX6QDL_CLK_USBPHY2_GATE 192 203 #define IMX6QDL_CLK_PLL4_POST_DIV 193 204 #define IMX6QDL_CLK_PLL5_POST_DIV 194 205 #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 206 #define IMX6QDL_CLK_EIM_SLOW 196 207 #define IMX6QDL_CLK_SPDIF 197 208 #define IMX6QDL_CLK_CKO2_SEL 198 209 #define IMX6QDL_CLK_CKO2_PODF 199 210 #define IMX6QDL_CLK_CKO2 200 211 #define IMX6QDL_CLK_CKO 201 212 #define IMX6QDL_CLK_VDOA 202 213 #define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 214 #define IMX6QDL_CLK_LVDS1_SEL 204 215 #define IMX6QDL_CLK_LVDS2_SEL 205 216 #define IMX6QDL_CLK_LVDS1_GATE 206 217 #define IMX6QDL_CLK_LVDS2_GATE 207 218 #define IMX6QDL_CLK_ESAI_IPG 208 219 #define IMX6QDL_CLK_ESAI_MEM 209 220 #define IMX6QDL_CLK_ASRC_IPG 210 221 #define IMX6QDL_CLK_ASRC_MEM 211 222 #define IMX6QDL_CLK_LVDS1_IN 212 223 #define IMX6QDL_CLK_LVDS2_IN 213 224 #define IMX6QDL_CLK_ANACLK1 214 225 #define IMX6QDL_CLK_ANACLK2 215 226 #define IMX6QDL_PLL1_BYPASS_SRC 216 227 #define IMX6QDL_PLL2_BYPASS_SRC 217 228 #define IMX6QDL_PLL3_BYPASS_SRC 218 229 #define IMX6QDL_PLL4_BYPASS_SRC 219 230 #define IMX6QDL_PLL5_BYPASS_SRC 220 231 #define IMX6QDL_PLL6_BYPASS_SRC 221 232 #define IMX6QDL_PLL7_BYPASS_SRC 222 233 #define IMX6QDL_CLK_PLL1 223 234 #define IMX6QDL_CLK_PLL2 224 235 #define IMX6QDL_CLK_PLL3 225 236 #define IMX6QDL_CLK_PLL4 226 237 #define IMX6QDL_CLK_PLL5 227 238 #define IMX6QDL_CLK_PLL6 228 239 #define IMX6QDL_CLK_PLL7 229 240 #define IMX6QDL_PLL1_BYPASS 230 241 #define IMX6QDL_PLL2_BYPASS 231 242 #define IMX6QDL_PLL3_BYPASS 232 243 #define IMX6QDL_PLL4_BYPASS 233 244 #define IMX6QDL_PLL5_BYPASS 234 245 #define IMX6QDL_PLL6_BYPASS 235 246 #define IMX6QDL_PLL7_BYPASS 236 247 #define IMX6QDL_CLK_GPT_3M 237 248 #define IMX6QDL_CLK_VIDEO_27M 238 249 #define IMX6QDL_CLK_MIPI_CORE_CFG 239 250 #define IMX6QDL_CLK_MIPI_IPG 240 251 #define IMX6QDL_CLK_CAAM_MEM 241 252 #define IMX6QDL_CLK_CAAM_ACLK 242 253 #define IMX6QDL_CLK_CAAM_IPG 243 254 #define IMX6QDL_CLK_SPDIF_GCLK 244 255 #define IMX6QDL_CLK_UART_SEL 245 256 #define IMX6QDL_CLK_IPG_PER_SEL 246 257 #define IMX6QDL_CLK_ECSPI_SEL 247 258 #define IMX6QDL_CLK_CAN_SEL 248 259 #define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 260 #define IMX6QDL_CLK_PRE0 250 261 #define IMX6QDL_CLK_PRE1 251 262 #define IMX6QDL_CLK_PRE2 252 263 #define IMX6QDL_CLK_PRE3 253 264 #define IMX6QDL_CLK_PRG0_AXI 254 265 #define IMX6QDL_CLK_PRG1_AXI 255 266 #define IMX6QDL_CLK_PRG0_APB 256 267 #define IMX6QDL_CLK_PRG1_APB 257 268 #define IMX6QDL_CLK_PRE_AXI 258 269 #define IMX6QDL_CLK_MLB_SEL 259 270 #define IMX6QDL_CLK_MLB_PODF 260 271 #define IMX6QDL_CLK_EPIT1 261 272 #define IMX6QDL_CLK_EPIT2 262 273 #define IMX6QDL_CLK_MMDC_P0_IPG 263 274 #define IMX6QDL_CLK_DCIC1 264 275 #define IMX6QDL_CLK_DCIC2 265 276 #define IMX6QDL_CLK_ENET_REF_SEL 266 277 #define IMX6QDL_CLK_ENET_REF_PAD 267 278 #define IMX6QDL_CLK_END 268 279 280 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ 281
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