1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This header provides clock numbers for the ingenic,x1830-cgu DT binding. 4 * 5 * They are roughly ordered as: 6 * - external clocks 7 * - PLLs 8 * - muxes/dividers in the order they appear in the x1830 programmers manual 9 * - gates in order of their bit in the CLKGR* registers 10 */ 11 12 #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ 13 #define __DT_BINDINGS_CLOCK_X1830_CGU_H__ 14 15 #define X1830_CLK_EXCLK 0 16 #define X1830_CLK_RTCLK 1 17 #define X1830_CLK_APLL 2 18 #define X1830_CLK_MPLL 3 19 #define X1830_CLK_EPLL 4 20 #define X1830_CLK_VPLL 5 21 #define X1830_CLK_OTGPHY 6 22 #define X1830_CLK_SCLKA 7 23 #define X1830_CLK_CPUMUX 8 24 #define X1830_CLK_CPU 9 25 #define X1830_CLK_L2CACHE 10 26 #define X1830_CLK_AHB0 11 27 #define X1830_CLK_AHB2PMUX 12 28 #define X1830_CLK_AHB2 13 29 #define X1830_CLK_PCLK 14 30 #define X1830_CLK_DDR 15 31 #define X1830_CLK_MAC 16 32 #define X1830_CLK_LCD 17 33 #define X1830_CLK_MSCMUX 18 34 #define X1830_CLK_MSC0 19 35 #define X1830_CLK_MSC1 20 36 #define X1830_CLK_SSIPLL 21 37 #define X1830_CLK_SSIPLL_DIV2 22 38 #define X1830_CLK_SSIMUX 23 39 #define X1830_CLK_EMC 24 40 #define X1830_CLK_EFUSE 25 41 #define X1830_CLK_OTG 26 42 #define X1830_CLK_SSI0 27 43 #define X1830_CLK_SMB0 28 44 #define X1830_CLK_SMB1 29 45 #define X1830_CLK_SMB2 30 46 #define X1830_CLK_UART0 31 47 #define X1830_CLK_UART1 32 48 #define X1830_CLK_SSI1 33 49 #define X1830_CLK_SFC 34 50 #define X1830_CLK_PDMA 35 51 #define X1830_CLK_TCU 36 52 #define X1830_CLK_DTRNG 37 53 #define X1830_CLK_OST 38 54 #define X1830_CLK_EXCLK_DIV512 39 55 #define X1830_CLK_RTC 40 56 57 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ 58
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