1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H 7 #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H 8 9 /* CAM_CC clocks */ 10 #define CAM_CC_PLL2_OUT_EARLY 0 11 #define CAM_CC_PLL0 1 12 #define CAM_CC_PLL1 2 13 #define CAM_CC_PLL2 3 14 #define CAM_CC_PLL2_OUT_AUX 4 15 #define CAM_CC_PLL3 5 16 #define CAM_CC_CAMNOC_AXI_CLK 6 17 #define CAM_CC_CCI_0_CLK 7 18 #define CAM_CC_CCI_0_CLK_SRC 8 19 #define CAM_CC_CCI_1_CLK 9 20 #define CAM_CC_CCI_1_CLK_SRC 10 21 #define CAM_CC_CORE_AHB_CLK 11 22 #define CAM_CC_CPAS_AHB_CLK 12 23 #define CAM_CC_CPHY_RX_CLK_SRC 13 24 #define CAM_CC_CSI0PHYTIMER_CLK 14 25 #define CAM_CC_CSI0PHYTIMER_CLK_SRC 15 26 #define CAM_CC_CSI1PHYTIMER_CLK 16 27 #define CAM_CC_CSI1PHYTIMER_CLK_SRC 17 28 #define CAM_CC_CSI2PHYTIMER_CLK 18 29 #define CAM_CC_CSI2PHYTIMER_CLK_SRC 19 30 #define CAM_CC_CSI3PHYTIMER_CLK 20 31 #define CAM_CC_CSI3PHYTIMER_CLK_SRC 21 32 #define CAM_CC_CSIPHY0_CLK 22 33 #define CAM_CC_CSIPHY1_CLK 23 34 #define CAM_CC_CSIPHY2_CLK 24 35 #define CAM_CC_CSIPHY3_CLK 25 36 #define CAM_CC_FAST_AHB_CLK_SRC 26 37 #define CAM_CC_ICP_APB_CLK 27 38 #define CAM_CC_ICP_ATB_CLK 28 39 #define CAM_CC_ICP_CLK 29 40 #define CAM_CC_ICP_CLK_SRC 30 41 #define CAM_CC_ICP_CTI_CLK 31 42 #define CAM_CC_ICP_TS_CLK 32 43 #define CAM_CC_IFE_0_AXI_CLK 33 44 #define CAM_CC_IFE_0_CLK 34 45 #define CAM_CC_IFE_0_CLK_SRC 35 46 #define CAM_CC_IFE_0_CPHY_RX_CLK 36 47 #define CAM_CC_IFE_0_CSID_CLK 37 48 #define CAM_CC_IFE_0_CSID_CLK_SRC 38 49 #define CAM_CC_IFE_0_DSP_CLK 39 50 #define CAM_CC_IFE_1_AXI_CLK 40 51 #define CAM_CC_IFE_1_CLK 41 52 #define CAM_CC_IFE_1_CLK_SRC 42 53 #define CAM_CC_IFE_1_CPHY_RX_CLK 43 54 #define CAM_CC_IFE_1_CSID_CLK 44 55 #define CAM_CC_IFE_1_CSID_CLK_SRC 45 56 #define CAM_CC_IFE_1_DSP_CLK 46 57 #define CAM_CC_IFE_LITE_CLK 47 58 #define CAM_CC_IFE_LITE_CLK_SRC 48 59 #define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 60 #define CAM_CC_IFE_LITE_CSID_CLK 50 61 #define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 62 #define CAM_CC_IPE_0_AHB_CLK 52 63 #define CAM_CC_IPE_0_AREG_CLK 53 64 #define CAM_CC_IPE_0_AXI_CLK 54 65 #define CAM_CC_IPE_0_CLK 55 66 #define CAM_CC_IPE_0_CLK_SRC 56 67 #define CAM_CC_JPEG_CLK 57 68 #define CAM_CC_JPEG_CLK_SRC 58 69 #define CAM_CC_LRME_CLK 59 70 #define CAM_CC_LRME_CLK_SRC 60 71 #define CAM_CC_MCLK0_CLK 61 72 #define CAM_CC_MCLK0_CLK_SRC 62 73 #define CAM_CC_MCLK1_CLK 63 74 #define CAM_CC_MCLK1_CLK_SRC 64 75 #define CAM_CC_MCLK2_CLK 65 76 #define CAM_CC_MCLK2_CLK_SRC 66 77 #define CAM_CC_MCLK3_CLK 67 78 #define CAM_CC_MCLK3_CLK_SRC 68 79 #define CAM_CC_MCLK4_CLK 69 80 #define CAM_CC_MCLK4_CLK_SRC 70 81 #define CAM_CC_BPS_AHB_CLK 71 82 #define CAM_CC_BPS_AREG_CLK 72 83 #define CAM_CC_BPS_AXI_CLK 73 84 #define CAM_CC_BPS_CLK 74 85 #define CAM_CC_BPS_CLK_SRC 75 86 #define CAM_CC_SLOW_AHB_CLK_SRC 76 87 #define CAM_CC_SOC_AHB_CLK 77 88 #define CAM_CC_SYS_TMR_CLK 78 89 90 /* CAM_CC power domains */ 91 #define BPS_GDSC 0 92 #define IFE_0_GDSC 1 93 #define IFE_1_GDSC 2 94 #define IPE_0_GDSC 3 95 #define TITAN_TOP_GDSC 4 96 97 /* CAM_CC resets */ 98 #define CAM_CC_BPS_BCR 0 99 #define CAM_CC_CAMNOC_BCR 1 100 #define CAM_CC_CCI_0_BCR 2 101 #define CAM_CC_CCI_1_BCR 3 102 #define CAM_CC_CPAS_BCR 4 103 #define CAM_CC_CSI0PHY_BCR 5 104 #define CAM_CC_CSI1PHY_BCR 6 105 #define CAM_CC_CSI2PHY_BCR 7 106 #define CAM_CC_CSI3PHY_BCR 8 107 #define CAM_CC_ICP_BCR 9 108 #define CAM_CC_IFE_0_BCR 10 109 #define CAM_CC_IFE_1_BCR 11 110 #define CAM_CC_IFE_LITE_BCR 12 111 #define CAM_CC_IPE_0_BCR 13 112 #define CAM_CC_JPEG_BCR 14 113 #define CAM_CC_LRME_BCR 15 114 #define CAM_CC_MCLK0_BCR 16 115 #define CAM_CC_MCLK1_BCR 17 116 #define CAM_CC_MCLK2_BCR 18 117 #define CAM_CC_MCLK3_BCR 19 118 #define CAM_CC_MCLK4_BCR 20 119 #define CAM_CC_TITAN_TOP_BCR 21 120 121 #endif 122
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