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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-sm8350.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 /*
  3  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4  */
  5 
  6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
  7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
  8 
  9 /* DISP_CC clock registers */
 10 #define DISP_CC_MDSS_AHB_CLK                    0
 11 #define DISP_CC_MDSS_AHB_CLK_SRC                1
 12 #define DISP_CC_MDSS_BYTE0_CLK                  2
 13 #define DISP_CC_MDSS_BYTE0_CLK_SRC              3
 14 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC          4
 15 #define DISP_CC_MDSS_BYTE0_INTF_CLK             5
 16 #define DISP_CC_MDSS_BYTE1_CLK                  6
 17 #define DISP_CC_MDSS_BYTE1_CLK_SRC              7
 18 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC          8
 19 #define DISP_CC_MDSS_BYTE1_INTF_CLK             9
 20 #define DISP_CC_MDSS_DP_AUX1_CLK                10
 21 #define DISP_CC_MDSS_DP_AUX1_CLK_SRC            11
 22 #define DISP_CC_MDSS_DP_AUX_CLK                 12
 23 #define DISP_CC_MDSS_DP_AUX_CLK_SRC             13
 24 #define DISP_CC_MDSS_DP_LINK1_CLK               14
 25 #define DISP_CC_MDSS_DP_LINK1_CLK_SRC           15
 26 #define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC       16
 27 #define DISP_CC_MDSS_DP_LINK1_INTF_CLK          17
 28 #define DISP_CC_MDSS_DP_LINK_CLK                18
 29 #define DISP_CC_MDSS_DP_LINK_CLK_SRC            19
 30 #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC        20
 31 #define DISP_CC_MDSS_DP_LINK_INTF_CLK           21
 32 #define DISP_CC_MDSS_DP_PIXEL1_CLK              22
 33 #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC          23
 34 #define DISP_CC_MDSS_DP_PIXEL2_CLK              24
 35 #define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC          25
 36 #define DISP_CC_MDSS_DP_PIXEL_CLK               26
 37 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC           27
 38 #define DISP_CC_MDSS_ESC0_CLK                   28
 39 #define DISP_CC_MDSS_ESC0_CLK_SRC               29
 40 #define DISP_CC_MDSS_ESC1_CLK                   30
 41 #define DISP_CC_MDSS_ESC1_CLK_SRC               31
 42 #define DISP_CC_MDSS_MDP_CLK                    32
 43 #define DISP_CC_MDSS_MDP_CLK_SRC                33
 44 #define DISP_CC_MDSS_MDP_LUT_CLK                34
 45 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK           35
 46 #define DISP_CC_MDSS_PCLK0_CLK                  36
 47 #define DISP_CC_MDSS_PCLK0_CLK_SRC              37
 48 #define DISP_CC_MDSS_PCLK1_CLK                  38
 49 #define DISP_CC_MDSS_PCLK1_CLK_SRC              39
 50 #define DISP_CC_MDSS_ROT_CLK                    40
 51 #define DISP_CC_MDSS_ROT_CLK_SRC                41
 52 #define DISP_CC_MDSS_RSCC_AHB_CLK               42
 53 #define DISP_CC_MDSS_RSCC_VSYNC_CLK             43
 54 #define DISP_CC_MDSS_VSYNC_CLK                  44
 55 #define DISP_CC_MDSS_VSYNC_CLK_SRC              45
 56 #define DISP_CC_PLL0                            46
 57 #define DISP_CC_PLL1                            47
 58 #define DISP_CC_MDSS_EDP_AUX_CLK                48
 59 #define DISP_CC_MDSS_EDP_AUX_CLK_SRC            49
 60 #define DISP_CC_MDSS_EDP_GTC_CLK                50
 61 #define DISP_CC_MDSS_EDP_GTC_CLK_SRC            51
 62 #define DISP_CC_MDSS_EDP_LINK_CLK               52
 63 #define DISP_CC_MDSS_EDP_LINK_CLK_SRC           53
 64 #define DISP_CC_MDSS_EDP_LINK_INTF_CLK          54
 65 #define DISP_CC_MDSS_EDP_PIXEL_CLK              55
 66 #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC          56
 67 #define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC       57
 68 
 69 /* DISP_CC Reset */
 70 #define DISP_CC_MDSS_CORE_BCR                   0
 71 #define DISP_CC_MDSS_RSCC_BCR                   1
 72 
 73 /* DISP_CC GDSCR */
 74 #define MDSS_GDSC                               0
 75 
 76 #endif
 77 

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