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Linux/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-msm8974.h

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  1 /* SPDX-License-Identifier: GPL-2.0-only */
  2 /*
  3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  4  */
  5 
  6 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H
  7 #define _DT_BINDINGS_CLK_MSM_MMCC_8974_H
  8 
  9 #define MMSS_AHB_CLK_SRC                                0
 10 #define MMSS_AXI_CLK_SRC                                1
 11 #define MMPLL0                                          2
 12 #define MMPLL0_VOTE                                     3
 13 #define MMPLL1                                          4
 14 #define MMPLL1_VOTE                                     5
 15 #define MMPLL2                                          6
 16 #define MMPLL3                                          7
 17 #define CSI0_CLK_SRC                                    8
 18 #define CSI1_CLK_SRC                                    9
 19 #define CSI2_CLK_SRC                                    10
 20 #define CSI3_CLK_SRC                                    11
 21 #define VFE0_CLK_SRC                                    12
 22 #define VFE1_CLK_SRC                                    13
 23 #define MDP_CLK_SRC                                     14
 24 #define GFX3D_CLK_SRC                                   15
 25 #define JPEG0_CLK_SRC                                   16
 26 #define JPEG1_CLK_SRC                                   17
 27 #define JPEG2_CLK_SRC                                   18
 28 #define PCLK0_CLK_SRC                                   19
 29 #define PCLK1_CLK_SRC                                   20
 30 #define VCODEC0_CLK_SRC                                 21
 31 #define CCI_CLK_SRC                                     22
 32 #define CAMSS_GP0_CLK_SRC                               23
 33 #define CAMSS_GP1_CLK_SRC                               24
 34 #define MCLK0_CLK_SRC                                   25
 35 #define MCLK1_CLK_SRC                                   26
 36 #define MCLK2_CLK_SRC                                   27
 37 #define MCLK3_CLK_SRC                                   28
 38 #define CSI0PHYTIMER_CLK_SRC                            29
 39 #define CSI1PHYTIMER_CLK_SRC                            30
 40 #define CSI2PHYTIMER_CLK_SRC                            31
 41 #define CPP_CLK_SRC                                     32
 42 #define BYTE0_CLK_SRC                                   33
 43 #define BYTE1_CLK_SRC                                   34
 44 #define EDPAUX_CLK_SRC                                  35
 45 #define EDPLINK_CLK_SRC                                 36
 46 #define EDPPIXEL_CLK_SRC                                37
 47 #define ESC0_CLK_SRC                                    38
 48 #define ESC1_CLK_SRC                                    39
 49 #define EXTPCLK_CLK_SRC                                 40
 50 #define HDMI_CLK_SRC                                    41
 51 #define VSYNC_CLK_SRC                                   42
 52 #define MMSS_RBCPR_CLK_SRC                              43
 53 #define CAMSS_CCI_CCI_AHB_CLK                           44
 54 #define CAMSS_CCI_CCI_CLK                               45
 55 #define CAMSS_CSI0_AHB_CLK                              46
 56 #define CAMSS_CSI0_CLK                                  47
 57 #define CAMSS_CSI0PHY_CLK                               48
 58 #define CAMSS_CSI0PIX_CLK                               49
 59 #define CAMSS_CSI0RDI_CLK                               50
 60 #define CAMSS_CSI1_AHB_CLK                              51
 61 #define CAMSS_CSI1_CLK                                  52
 62 #define CAMSS_CSI1PHY_CLK                               53
 63 #define CAMSS_CSI1PIX_CLK                               54
 64 #define CAMSS_CSI1RDI_CLK                               55
 65 #define CAMSS_CSI2_AHB_CLK                              56
 66 #define CAMSS_CSI2_CLK                                  57
 67 #define CAMSS_CSI2PHY_CLK                               58
 68 #define CAMSS_CSI2PIX_CLK                               59
 69 #define CAMSS_CSI2RDI_CLK                               60
 70 #define CAMSS_CSI3_AHB_CLK                              61
 71 #define CAMSS_CSI3_CLK                                  62
 72 #define CAMSS_CSI3PHY_CLK                               63
 73 #define CAMSS_CSI3PIX_CLK                               64
 74 #define CAMSS_CSI3RDI_CLK                               65
 75 #define CAMSS_CSI_VFE0_CLK                              66
 76 #define CAMSS_CSI_VFE1_CLK                              67
 77 #define CAMSS_GP0_CLK                                   68
 78 #define CAMSS_GP1_CLK                                   69
 79 #define CAMSS_ISPIF_AHB_CLK                             70
 80 #define CAMSS_JPEG_JPEG0_CLK                            71
 81 #define CAMSS_JPEG_JPEG1_CLK                            72
 82 #define CAMSS_JPEG_JPEG2_CLK                            73
 83 #define CAMSS_JPEG_JPEG_AHB_CLK                         74
 84 #define CAMSS_JPEG_JPEG_AXI_CLK                         75
 85 #define CAMSS_JPEG_JPEG_OCMEMNOC_CLK                    76
 86 #define CAMSS_MCLK0_CLK                                 77
 87 #define CAMSS_MCLK1_CLK                                 78
 88 #define CAMSS_MCLK2_CLK                                 79
 89 #define CAMSS_MCLK3_CLK                                 80
 90 #define CAMSS_MICRO_AHB_CLK                             81
 91 #define CAMSS_PHY0_CSI0PHYTIMER_CLK                     82
 92 #define CAMSS_PHY1_CSI1PHYTIMER_CLK                     83
 93 #define CAMSS_PHY2_CSI2PHYTIMER_CLK                     84
 94 #define CAMSS_TOP_AHB_CLK                               85
 95 #define CAMSS_VFE_CPP_AHB_CLK                           86
 96 #define CAMSS_VFE_CPP_CLK                               87
 97 #define CAMSS_VFE_VFE0_CLK                              88
 98 #define CAMSS_VFE_VFE1_CLK                              89
 99 #define CAMSS_VFE_VFE_AHB_CLK                           90
100 #define CAMSS_VFE_VFE_AXI_CLK                           91
101 #define CAMSS_VFE_VFE_OCMEMNOC_CLK                      92
102 #define MDSS_AHB_CLK                                    93
103 #define MDSS_AXI_CLK                                    94
104 #define MDSS_BYTE0_CLK                                  95
105 #define MDSS_BYTE1_CLK                                  96
106 #define MDSS_EDPAUX_CLK                                 97
107 #define MDSS_EDPLINK_CLK                                98
108 #define MDSS_EDPPIXEL_CLK                               99
109 #define MDSS_ESC0_CLK                                   100
110 #define MDSS_ESC1_CLK                                   101
111 #define MDSS_EXTPCLK_CLK                                102
112 #define MDSS_HDMI_AHB_CLK                               103
113 #define MDSS_HDMI_CLK                                   104
114 #define MDSS_MDP_CLK                                    105
115 #define MDSS_MDP_LUT_CLK                                106
116 #define MDSS_PCLK0_CLK                                  107
117 #define MDSS_PCLK1_CLK                                  108
118 #define MDSS_VSYNC_CLK                                  109
119 #define MMSS_MISC_AHB_CLK                               110
120 #define MMSS_MMSSNOC_AHB_CLK                            111
121 #define MMSS_MMSSNOC_BTO_AHB_CLK                        112
122 #define MMSS_MMSSNOC_AXI_CLK                            113
123 #define MMSS_S0_AXI_CLK                                 114
124 #define OCMEMCX_OCMEMNOC_CLK                            116
125 #define OXILI_OCMEMGX_CLK                               117
126 #define OCMEMNOC_CLK                                    118
127 #define OXILI_GFX3D_CLK                                 119
128 #define OXILICX_AHB_CLK                                 120
129 #define OXILICX_AXI_CLK                                 121
130 #define VENUS0_AHB_CLK                                  122
131 #define VENUS0_AXI_CLK                                  123
132 #define VENUS0_OCMEMNOC_CLK                             124
133 #define VENUS0_VCODEC0_CLK                              125
134 #define OCMEMNOC_CLK_SRC                                126
135 #define SPDM_JPEG0                                      127
136 #define SPDM_JPEG1                                      128
137 #define SPDM_MDP                                        129
138 #define SPDM_AXI                                        130
139 #define SPDM_VCODEC0                                    131
140 #define SPDM_VFE0                                       132
141 #define SPDM_VFE1                                       133
142 #define SPDM_JPEG2                                      134
143 #define SPDM_PCLK1                                      135
144 #define SPDM_GFX3D                                      136
145 #define SPDM_AHB                                        137
146 #define SPDM_PCLK0                                      138
147 #define SPDM_OCMEMNOC                                   139
148 #define SPDM_CSI0                                       140
149 #define SPDM_RM_AXI                                     141
150 #define SPDM_RM_OCMEMNOC                                142
151 
152 /* gdscs */
153 #define VENUS0_GDSC                                     0
154 #define MDSS_GDSC                                       1
155 #define CAMSS_JPEG_GDSC                                 2
156 #define CAMSS_VFE_GDSC                                  3
157 #define OXILI_GDSC                                      4
158 #define OXILICX_GDSC                                    5
159 
160 #endif
161 

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