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Linux/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm7150-camcc.h

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  1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*
  3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4  * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
  5  */
  6 
  7 #ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H
  8 #define _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H
  9 
 10 /* Hardware clocks */
 11 #define CAMCC_PLL0_OUT_EVEN                                     0
 12 #define CAMCC_PLL0_OUT_ODD                                      1
 13 #define CAMCC_PLL1_OUT_EVEN                                     2
 14 #define CAMCC_PLL2_OUT_EARLY                                    3
 15 #define CAMCC_PLL3_OUT_EVEN                                     4
 16 #define CAMCC_PLL4_OUT_EVEN                                     5
 17 
 18 /* CAMCC clock registers */
 19 #define CAMCC_PLL0                                              6
 20 #define CAMCC_PLL1                                              7
 21 #define CAMCC_PLL2                                              8
 22 #define CAMCC_PLL2_OUT_AUX                                      9
 23 #define CAMCC_PLL2_OUT_MAIN                                     10
 24 #define CAMCC_PLL3                                              11
 25 #define CAMCC_PLL4                                              12
 26 #define CAMCC_BPS_AHB_CLK                                       13
 27 #define CAMCC_BPS_AREG_CLK                                      14
 28 #define CAMCC_BPS_AXI_CLK                                       15
 29 #define CAMCC_BPS_CLK                                           16
 30 #define CAMCC_BPS_CLK_SRC                                       17
 31 #define CAMCC_CAMNOC_AXI_CLK                                    18
 32 #define CAMCC_CAMNOC_AXI_CLK_SRC                                19
 33 #define CAMCC_CAMNOC_DCD_XO_CLK                                 20
 34 #define CAMCC_CCI_0_CLK                                         21
 35 #define CAMCC_CCI_0_CLK_SRC                                     22
 36 #define CAMCC_CCI_1_CLK                                         23
 37 #define CAMCC_CCI_1_CLK_SRC                                     24
 38 #define CAMCC_CORE_AHB_CLK                                      25
 39 #define CAMCC_CPAS_AHB_CLK                                      26
 40 #define CAMCC_CPHY_RX_CLK_SRC                                   27
 41 #define CAMCC_CSI0PHYTIMER_CLK                                  28
 42 #define CAMCC_CSI0PHYTIMER_CLK_SRC                              29
 43 #define CAMCC_CSI1PHYTIMER_CLK                                  30
 44 #define CAMCC_CSI1PHYTIMER_CLK_SRC                              31
 45 #define CAMCC_CSI2PHYTIMER_CLK                                  32
 46 #define CAMCC_CSI2PHYTIMER_CLK_SRC                              33
 47 #define CAMCC_CSI3PHYTIMER_CLK                                  34
 48 #define CAMCC_CSI3PHYTIMER_CLK_SRC                              35
 49 #define CAMCC_CSIPHY0_CLK                                       36
 50 #define CAMCC_CSIPHY1_CLK                                       37
 51 #define CAMCC_CSIPHY2_CLK                                       38
 52 #define CAMCC_CSIPHY3_CLK                                       39
 53 #define CAMCC_FAST_AHB_CLK_SRC                                  40
 54 #define CAMCC_FD_CORE_CLK                                       41
 55 #define CAMCC_FD_CORE_CLK_SRC                                   42
 56 #define CAMCC_FD_CORE_UAR_CLK                                   43
 57 #define CAMCC_ICP_AHB_CLK                                       44
 58 #define CAMCC_ICP_CLK                                           45
 59 #define CAMCC_ICP_CLK_SRC                                       46
 60 #define CAMCC_IFE_0_AXI_CLK                                     47
 61 #define CAMCC_IFE_0_CLK                                         48
 62 #define CAMCC_IFE_0_CLK_SRC                                     49
 63 #define CAMCC_IFE_0_CPHY_RX_CLK                                 50
 64 #define CAMCC_IFE_0_CSID_CLK                                    51
 65 #define CAMCC_IFE_0_CSID_CLK_SRC                                52
 66 #define CAMCC_IFE_0_DSP_CLK                                     53
 67 #define CAMCC_IFE_1_AXI_CLK                                     54
 68 #define CAMCC_IFE_1_CLK                                         55
 69 #define CAMCC_IFE_1_CLK_SRC                                     56
 70 #define CAMCC_IFE_1_CPHY_RX_CLK                                 57
 71 #define CAMCC_IFE_1_CSID_CLK                                    58
 72 #define CAMCC_IFE_1_CSID_CLK_SRC                                59
 73 #define CAMCC_IFE_1_DSP_CLK                                     60
 74 #define CAMCC_IFE_LITE_CLK                                      61
 75 #define CAMCC_IFE_LITE_CLK_SRC                                  62
 76 #define CAMCC_IFE_LITE_CPHY_RX_CLK                              63
 77 #define CAMCC_IFE_LITE_CSID_CLK                                 64
 78 #define CAMCC_IFE_LITE_CSID_CLK_SRC                             65
 79 #define CAMCC_IPE_0_AHB_CLK                                     66
 80 #define CAMCC_IPE_0_AREG_CLK                                    67
 81 #define CAMCC_IPE_0_AXI_CLK                                     68
 82 #define CAMCC_IPE_0_CLK                                         69
 83 #define CAMCC_IPE_0_CLK_SRC                                     70
 84 #define CAMCC_IPE_1_AHB_CLK                                     71
 85 #define CAMCC_IPE_1_AREG_CLK                                    72
 86 #define CAMCC_IPE_1_AXI_CLK                                     73
 87 #define CAMCC_IPE_1_CLK                                         74
 88 #define CAMCC_JPEG_CLK                                          75
 89 #define CAMCC_JPEG_CLK_SRC                                      76
 90 #define CAMCC_LRME_CLK                                          77
 91 #define CAMCC_LRME_CLK_SRC                                      78
 92 #define CAMCC_MCLK0_CLK                                         79
 93 #define CAMCC_MCLK0_CLK_SRC                                     80
 94 #define CAMCC_MCLK1_CLK                                         81
 95 #define CAMCC_MCLK1_CLK_SRC                                     82
 96 #define CAMCC_MCLK2_CLK                                         83
 97 #define CAMCC_MCLK2_CLK_SRC                                     84
 98 #define CAMCC_MCLK3_CLK                                         85
 99 #define CAMCC_MCLK3_CLK_SRC                                     86
100 #define CAMCC_SLEEP_CLK                                         87
101 #define CAMCC_SLEEP_CLK_SRC                                     88
102 #define CAMCC_SLOW_AHB_CLK_SRC                                  89
103 #define CAMCC_XO_CLK_SRC                                        90
104 
105 /* CAMCC GDSCRs */
106 #define BPS_GDSC                                                0
107 #define IFE_0_GDSC                                              1
108 #define IFE_1_GDSC                                              2
109 #define IPE_0_GDSC                                              3
110 #define IPE_1_GDSC                                              4
111 #define TITAN_TOP_GDSC                                          5
112 
113 #endif
114 

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