1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2014 Ulrich Hecht 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_R8A7740_H__ 7 #define __DT_BINDINGS_CLOCK_R8A7740_H__ 8 9 /* CPG */ 10 #define R8A7740_CLK_SYSTEM 0 11 #define R8A7740_CLK_PLLC0 1 12 #define R8A7740_CLK_PLLC1 2 13 #define R8A7740_CLK_PLLC2 3 14 #define R8A7740_CLK_R 4 15 #define R8A7740_CLK_USB24S 5 16 #define R8A7740_CLK_I 6 17 #define R8A7740_CLK_ZG 7 18 #define R8A7740_CLK_B 8 19 #define R8A7740_CLK_M1 9 20 #define R8A7740_CLK_HP 10 21 #define R8A7740_CLK_HPP 11 22 #define R8A7740_CLK_USBP 12 23 #define R8A7740_CLK_S 13 24 #define R8A7740_CLK_ZB 14 25 #define R8A7740_CLK_M3 15 26 #define R8A7740_CLK_CP 16 27 28 /* MSTP1 */ 29 #define R8A7740_CLK_CEU21 28 30 #define R8A7740_CLK_CEU20 27 31 #define R8A7740_CLK_TMU0 25 32 #define R8A7740_CLK_LCDC1 17 33 #define R8A7740_CLK_IIC0 16 34 #define R8A7740_CLK_TMU1 11 35 #define R8A7740_CLK_LCDC0 0 36 37 /* MSTP2 */ 38 #define R8A7740_CLK_SCIFA6 30 39 #define R8A7740_CLK_INTCA 29 40 #define R8A7740_CLK_SCIFA7 22 41 #define R8A7740_CLK_DMAC1 18 42 #define R8A7740_CLK_DMAC2 17 43 #define R8A7740_CLK_DMAC3 16 44 #define R8A7740_CLK_USBDMAC 14 45 #define R8A7740_CLK_SCIFA5 7 46 #define R8A7740_CLK_SCIFB 6 47 #define R8A7740_CLK_SCIFA0 4 48 #define R8A7740_CLK_SCIFA1 3 49 #define R8A7740_CLK_SCIFA2 2 50 #define R8A7740_CLK_SCIFA3 1 51 #define R8A7740_CLK_SCIFA4 0 52 53 /* MSTP3 */ 54 #define R8A7740_CLK_CMT1 29 55 #define R8A7740_CLK_FSI 28 56 #define R8A7740_CLK_IIC1 23 57 #define R8A7740_CLK_USBF 20 58 #define R8A7740_CLK_SDHI0 14 59 #define R8A7740_CLK_SDHI1 13 60 #define R8A7740_CLK_MMC 12 61 #define R8A7740_CLK_GETHER 9 62 #define R8A7740_CLK_TPU0 4 63 64 /* MSTP4 */ 65 #define R8A7740_CLK_USBH 16 66 #define R8A7740_CLK_SDHI2 15 67 #define R8A7740_CLK_USBFUNC 7 68 #define R8A7740_CLK_USBPHY 6 69 70 /* SUBCK* */ 71 #define R8A7740_CLK_SUBCK 9 72 #define R8A7740_CLK_SUBCK2 10 73 74 #endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */ 75
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