1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Copyright (c) 2022 Collabora Ltd. 5 * 6 * Author: Elaine Zhang <zhangqing@rock-chips.com> 7 * Author: Sebastian Reichel <sebastian.reichel@collabora.com> 8 */ 9 10 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H 11 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H 12 13 /* cru-clocks indices */ 14 15 #define PLL_B0PLL 0 16 #define PLL_B1PLL 1 17 #define PLL_LPLL 2 18 #define PLL_V0PLL 3 19 #define PLL_AUPLL 4 20 #define PLL_CPLL 5 21 #define PLL_GPLL 6 22 #define PLL_NPLL 7 23 #define PLL_PPLL 8 24 #define ARMCLK_L 9 25 #define ARMCLK_B01 10 26 #define ARMCLK_B23 11 27 #define PCLK_BIGCORE0_ROOT 12 28 #define PCLK_BIGCORE0_PVTM 13 29 #define PCLK_BIGCORE1_ROOT 14 30 #define PCLK_BIGCORE1_PVTM 15 31 #define PCLK_DSU_S_ROOT 16 32 #define PCLK_DSU_ROOT 17 33 #define PCLK_DSU_NS_ROOT 18 34 #define PCLK_LITCORE_PVTM 19 35 #define PCLK_DBG 20 36 #define PCLK_DSU 21 37 #define PCLK_S_DAPLITE 22 38 #define PCLK_M_DAPLITE 23 39 #define MBIST_MCLK_PDM1 24 40 #define MBIST_CLK_ACDCDIG 25 41 #define HCLK_I2S2_2CH 26 42 #define HCLK_I2S3_2CH 27 43 #define CLK_I2S2_2CH_SRC 28 44 #define CLK_I2S2_2CH_FRAC 29 45 #define CLK_I2S2_2CH 30 46 #define MCLK_I2S2_2CH 31 47 #define I2S2_2CH_MCLKOUT 32 48 #define CLK_DAC_ACDCDIG 33 49 #define CLK_I2S3_2CH_SRC 34 50 #define CLK_I2S3_2CH_FRAC 35 51 #define CLK_I2S3_2CH 36 52 #define MCLK_I2S3_2CH 37 53 #define I2S3_2CH_MCLKOUT 38 54 #define PCLK_ACDCDIG 39 55 #define HCLK_I2S0_8CH 40 56 #define CLK_I2S0_8CH_TX_SRC 41 57 #define CLK_I2S0_8CH_TX_FRAC 42 58 #define MCLK_I2S0_8CH_TX 43 59 #define CLK_I2S0_8CH_TX 44 60 #define CLK_I2S0_8CH_RX_SRC 45 61 #define CLK_I2S0_8CH_RX_FRAC 46 62 #define MCLK_I2S0_8CH_RX 47 63 #define CLK_I2S0_8CH_RX 48 64 #define I2S0_8CH_MCLKOUT 49 65 #define HCLK_PDM1 50 66 #define MCLK_PDM1 51 67 #define HCLK_AUDIO_ROOT 52 68 #define PCLK_AUDIO_ROOT 53 69 #define HCLK_SPDIF0 54 70 #define CLK_SPDIF0_SRC 55 71 #define CLK_SPDIF0_FRAC 56 72 #define MCLK_SPDIF0 57 73 #define CLK_SPDIF0 58 74 #define CLK_SPDIF1 59 75 #define HCLK_SPDIF1 60 76 #define CLK_SPDIF1_SRC 61 77 #define CLK_SPDIF1_FRAC 62 78 #define MCLK_SPDIF1 63 79 #define ACLK_AV1_ROOT 64 80 #define ACLK_AV1 65 81 #define PCLK_AV1_ROOT 66 82 #define PCLK_AV1 67 83 #define PCLK_MAILBOX0 68 84 #define PCLK_MAILBOX1 69 85 #define PCLK_MAILBOX2 70 86 #define PCLK_PMU2 71 87 #define PCLK_PMUCM0_INTMUX 72 88 #define PCLK_DDRCM0_INTMUX 73 89 #define PCLK_TOP 74 90 #define PCLK_PWM1 75 91 #define CLK_PWM1 76 92 #define CLK_PWM1_CAPTURE 77 93 #define PCLK_PWM2 78 94 #define CLK_PWM2 79 95 #define CLK_PWM2_CAPTURE 80 96 #define PCLK_PWM3 81 97 #define CLK_PWM3 82 98 #define CLK_PWM3_CAPTURE 83 99 #define PCLK_BUSTIMER0 84 100 #define PCLK_BUSTIMER1 85 101 #define CLK_BUS_TIMER_ROOT 86 102 #define CLK_BUSTIMER0 87 103 #define CLK_BUSTIMER1 88 104 #define CLK_BUSTIMER2 89 105 #define CLK_BUSTIMER3 90 106 #define CLK_BUSTIMER4 91 107 #define CLK_BUSTIMER5 92 108 #define CLK_BUSTIMER6 93 109 #define CLK_BUSTIMER7 94 110 #define CLK_BUSTIMER8 95 111 #define CLK_BUSTIMER9 96 112 #define CLK_BUSTIMER10 97 113 #define CLK_BUSTIMER11 98 114 #define PCLK_WDT0 99 115 #define TCLK_WDT0 100 116 #define PCLK_CAN0 101 117 #define CLK_CAN0 102 118 #define PCLK_CAN1 103 119 #define CLK_CAN1 104 120 #define PCLK_CAN2 105 121 #define CLK_CAN2 106 122 #define ACLK_DECOM 107 123 #define PCLK_DECOM 108 124 #define DCLK_DECOM 109 125 #define ACLK_DMAC0 110 126 #define ACLK_DMAC1 111 127 #define ACLK_DMAC2 112 128 #define ACLK_BUS_ROOT 113 129 #define ACLK_GIC 114 130 #define PCLK_GPIO1 115 131 #define DBCLK_GPIO1 116 132 #define PCLK_GPIO2 117 133 #define DBCLK_GPIO2 118 134 #define PCLK_GPIO3 119 135 #define DBCLK_GPIO3 120 136 #define PCLK_GPIO4 121 137 #define DBCLK_GPIO4 122 138 #define PCLK_I2C1 123 139 #define PCLK_I2C2 124 140 #define PCLK_I2C3 125 141 #define PCLK_I2C4 126 142 #define PCLK_I2C5 127 143 #define PCLK_I2C6 128 144 #define PCLK_I2C7 129 145 #define PCLK_I2C8 130 146 #define CLK_I2C1 131 147 #define CLK_I2C2 132 148 #define CLK_I2C3 133 149 #define CLK_I2C4 134 150 #define CLK_I2C5 135 151 #define CLK_I2C6 136 152 #define CLK_I2C7 137 153 #define CLK_I2C8 138 154 #define PCLK_OTPC_NS 139 155 #define CLK_OTPC_NS 140 156 #define CLK_OTPC_ARB 141 157 #define CLK_OTPC_AUTO_RD_G 142 158 #define CLK_OTP_PHY_G 143 159 #define PCLK_SARADC 144 160 #define CLK_SARADC 145 161 #define PCLK_SPI0 146 162 #define PCLK_SPI1 147 163 #define PCLK_SPI2 148 164 #define PCLK_SPI3 149 165 #define PCLK_SPI4 150 166 #define CLK_SPI0 151 167 #define CLK_SPI1 152 168 #define CLK_SPI2 153 169 #define CLK_SPI3 154 170 #define CLK_SPI4 155 171 #define ACLK_SPINLOCK 156 172 #define PCLK_TSADC 157 173 #define CLK_TSADC 158 174 #define PCLK_UART1 159 175 #define PCLK_UART2 160 176 #define PCLK_UART3 161 177 #define PCLK_UART4 162 178 #define PCLK_UART5 163 179 #define PCLK_UART6 164 180 #define PCLK_UART7 165 181 #define PCLK_UART8 166 182 #define PCLK_UART9 167 183 #define CLK_UART1_SRC 168 184 #define CLK_UART1_FRAC 169 185 #define CLK_UART1 170 186 #define SCLK_UART1 171 187 #define CLK_UART2_SRC 172 188 #define CLK_UART2_FRAC 173 189 #define CLK_UART2 174 190 #define SCLK_UART2 175 191 #define CLK_UART3_SRC 176 192 #define CLK_UART3_FRAC 177 193 #define CLK_UART3 178 194 #define SCLK_UART3 179 195 #define CLK_UART4_SRC 180 196 #define CLK_UART4_FRAC 181 197 #define CLK_UART4 182 198 #define SCLK_UART4 183 199 #define CLK_UART5_SRC 184 200 #define CLK_UART5_FRAC 185 201 #define CLK_UART5 186 202 #define SCLK_UART5 187 203 #define CLK_UART6_SRC 188 204 #define CLK_UART6_FRAC 189 205 #define CLK_UART6 190 206 #define SCLK_UART6 191 207 #define CLK_UART7_SRC 192 208 #define CLK_UART7_FRAC 193 209 #define CLK_UART7 194 210 #define SCLK_UART7 195 211 #define CLK_UART8_SRC 196 212 #define CLK_UART8_FRAC 197 213 #define CLK_UART8 198 214 #define SCLK_UART8 199 215 #define CLK_UART9_SRC 200 216 #define CLK_UART9_FRAC 201 217 #define CLK_UART9 202 218 #define SCLK_UART9 203 219 #define ACLK_CENTER_ROOT 204 220 #define ACLK_CENTER_LOW_ROOT 205 221 #define HCLK_CENTER_ROOT 206 222 #define PCLK_CENTER_ROOT 207 223 #define ACLK_DMA2DDR 208 224 #define ACLK_DDR_SHAREMEM 209 225 #define ACLK_CENTER_S200_ROOT 210 226 #define ACLK_CENTER_S400_ROOT 211 227 #define FCLK_DDR_CM0_CORE 212 228 #define CLK_DDR_TIMER_ROOT 213 229 #define CLK_DDR_TIMER0 214 230 #define CLK_DDR_TIMER1 215 231 #define TCLK_WDT_DDR 216 232 #define CLK_DDR_CM0_RTC 217 233 #define PCLK_WDT 218 234 #define PCLK_TIMER 219 235 #define PCLK_DMA2DDR 220 236 #define PCLK_SHAREMEM 221 237 #define CLK_50M_SRC 222 238 #define CLK_100M_SRC 223 239 #define CLK_150M_SRC 224 240 #define CLK_200M_SRC 225 241 #define CLK_250M_SRC 226 242 #define CLK_300M_SRC 227 243 #define CLK_350M_SRC 228 244 #define CLK_400M_SRC 229 245 #define CLK_450M_SRC 230 246 #define CLK_500M_SRC 231 247 #define CLK_600M_SRC 232 248 #define CLK_650M_SRC 233 249 #define CLK_700M_SRC 234 250 #define CLK_800M_SRC 235 251 #define CLK_1000M_SRC 236 252 #define CLK_1200M_SRC 237 253 #define ACLK_TOP_M300_ROOT 238 254 #define ACLK_TOP_M500_ROOT 239 255 #define ACLK_TOP_M400_ROOT 240 256 #define ACLK_TOP_S200_ROOT 241 257 #define ACLK_TOP_S400_ROOT 242 258 #define CLK_MIPI_CAMARAOUT_M0 243 259 #define CLK_MIPI_CAMARAOUT_M1 244 260 #define CLK_MIPI_CAMARAOUT_M2 245 261 #define CLK_MIPI_CAMARAOUT_M3 246 262 #define CLK_MIPI_CAMARAOUT_M4 247 263 #define MCLK_GMAC0_OUT 248 264 #define REFCLKO25M_ETH0_OUT 249 265 #define REFCLKO25M_ETH1_OUT 250 266 #define CLK_CIFOUT_OUT 251 267 #define PCLK_MIPI_DCPHY0 252 268 #define PCLK_MIPI_DCPHY1 253 269 #define PCLK_CSIPHY0 254 270 #define PCLK_CSIPHY1 255 271 #define ACLK_TOP_ROOT 256 272 #define PCLK_TOP_ROOT 257 273 #define ACLK_LOW_TOP_ROOT 258 274 #define PCLK_CRU 259 275 #define PCLK_GPU_ROOT 260 276 #define CLK_GPU_SRC 261 277 #define CLK_GPU 262 278 #define CLK_GPU_COREGROUP 263 279 #define CLK_GPU_STACKS 264 280 #define PCLK_GPU_PVTM 265 281 #define CLK_GPU_PVTM 266 282 #define CLK_CORE_GPU_PVTM 267 283 #define PCLK_GPU_GRF 268 284 #define ACLK_ISP1_ROOT 269 285 #define HCLK_ISP1_ROOT 270 286 #define CLK_ISP1_CORE 271 287 #define CLK_ISP1_CORE_MARVIN 272 288 #define CLK_ISP1_CORE_VICAP 273 289 #define ACLK_ISP1 274 290 #define HCLK_ISP1 275 291 #define ACLK_NPU1 276 292 #define HCLK_NPU1 277 293 #define ACLK_NPU2 278 294 #define HCLK_NPU2 279 295 #define HCLK_NPU_CM0_ROOT 280 296 #define FCLK_NPU_CM0_CORE 281 297 #define CLK_NPU_CM0_RTC 282 298 #define PCLK_NPU_PVTM 283 299 #define PCLK_NPU_GRF 284 300 #define CLK_NPU_PVTM 285 301 #define CLK_CORE_NPU_PVTM 286 302 #define ACLK_NPU0 287 303 #define HCLK_NPU0 288 304 #define HCLK_NPU_ROOT 289 305 #define CLK_NPU_DSU0 290 306 #define PCLK_NPU_ROOT 291 307 #define PCLK_NPU_TIMER 292 308 #define CLK_NPUTIMER_ROOT 293 309 #define CLK_NPUTIMER0 294 310 #define CLK_NPUTIMER1 295 311 #define PCLK_NPU_WDT 296 312 #define TCLK_NPU_WDT 297 313 #define HCLK_EMMC 298 314 #define ACLK_EMMC 299 315 #define CCLK_EMMC 300 316 #define BCLK_EMMC 301 317 #define TMCLK_EMMC 302 318 #define SCLK_SFC 303 319 #define HCLK_SFC 304 320 #define HCLK_SFC_XIP 305 321 #define HCLK_NVM_ROOT 306 322 #define ACLK_NVM_ROOT 307 323 #define CLK_GMAC0_PTP_REF 308 324 #define CLK_GMAC1_PTP_REF 309 325 #define CLK_GMAC_125M 310 326 #define CLK_GMAC_50M 311 327 #define ACLK_PHP_GIC_ITS 312 328 #define ACLK_MMU_PCIE 313 329 #define ACLK_MMU_PHP 314 330 #define ACLK_PCIE_4L_DBI 315 331 #define ACLK_PCIE_2L_DBI 316 332 #define ACLK_PCIE_1L0_DBI 317 333 #define ACLK_PCIE_1L1_DBI 318 334 #define ACLK_PCIE_1L2_DBI 319 335 #define ACLK_PCIE_4L_MSTR 320 336 #define ACLK_PCIE_2L_MSTR 321 337 #define ACLK_PCIE_1L0_MSTR 322 338 #define ACLK_PCIE_1L1_MSTR 323 339 #define ACLK_PCIE_1L2_MSTR 324 340 #define ACLK_PCIE_4L_SLV 325 341 #define ACLK_PCIE_2L_SLV 326 342 #define ACLK_PCIE_1L0_SLV 327 343 #define ACLK_PCIE_1L1_SLV 328 344 #define ACLK_PCIE_1L2_SLV 329 345 #define PCLK_PCIE_4L 330 346 #define PCLK_PCIE_2L 331 347 #define PCLK_PCIE_1L0 332 348 #define PCLK_PCIE_1L1 333 349 #define PCLK_PCIE_1L2 334 350 #define CLK_PCIE_AUX0 335 351 #define CLK_PCIE_AUX1 336 352 #define CLK_PCIE_AUX2 337 353 #define CLK_PCIE_AUX3 338 354 #define CLK_PCIE_AUX4 339 355 #define CLK_PIPEPHY0_REF 340 356 #define CLK_PIPEPHY1_REF 341 357 #define CLK_PIPEPHY2_REF 342 358 #define PCLK_PHP_ROOT 343 359 #define PCLK_GMAC0 344 360 #define PCLK_GMAC1 345 361 #define ACLK_PCIE_ROOT 346 362 #define ACLK_PHP_ROOT 347 363 #define ACLK_PCIE_BRIDGE 348 364 #define ACLK_GMAC0 349 365 #define ACLK_GMAC1 350 366 #define CLK_PMALIVE0 351 367 #define CLK_PMALIVE1 352 368 #define CLK_PMALIVE2 353 369 #define ACLK_SATA0 354 370 #define ACLK_SATA1 355 371 #define ACLK_SATA2 356 372 #define CLK_RXOOB0 357 373 #define CLK_RXOOB1 358 374 #define CLK_RXOOB2 359 375 #define ACLK_USB3OTG2 360 376 #define SUSPEND_CLK_USB3OTG2 361 377 #define REF_CLK_USB3OTG2 362 378 #define CLK_UTMI_OTG2 363 379 #define CLK_PIPEPHY0_PIPE_G 364 380 #define CLK_PIPEPHY1_PIPE_G 365 381 #define CLK_PIPEPHY2_PIPE_G 366 382 #define CLK_PIPEPHY0_PIPE_ASIC_G 367 383 #define CLK_PIPEPHY1_PIPE_ASIC_G 368 384 #define CLK_PIPEPHY2_PIPE_ASIC_G 369 385 #define CLK_PIPEPHY2_PIPE_U3_G 370 386 #define CLK_PCIE1L2_PIPE 371 387 #define CLK_PCIE4L_PIPE 372 388 #define CLK_PCIE2L_PIPE 373 389 #define PCLK_PCIE_COMBO_PIPE_PHY0 374 390 #define PCLK_PCIE_COMBO_PIPE_PHY1 375 391 #define PCLK_PCIE_COMBO_PIPE_PHY2 376 392 #define PCLK_PCIE_COMBO_PIPE_PHY 377 393 #define HCLK_RGA3_1 378 394 #define ACLK_RGA3_1 379 395 #define CLK_RGA3_1_CORE 380 396 #define ACLK_RGA3_ROOT 381 397 #define HCLK_RGA3_ROOT 382 398 #define ACLK_RKVDEC_CCU 383 399 #define HCLK_RKVDEC0 384 400 #define ACLK_RKVDEC0 385 401 #define CLK_RKVDEC0_CA 386 402 #define CLK_RKVDEC0_HEVC_CA 387 403 #define CLK_RKVDEC0_CORE 388 404 #define HCLK_RKVDEC1 389 405 #define ACLK_RKVDEC1 390 406 #define CLK_RKVDEC1_CA 391 407 #define CLK_RKVDEC1_HEVC_CA 392 408 #define CLK_RKVDEC1_CORE 393 409 #define HCLK_SDIO 394 410 #define CCLK_SRC_SDIO 395 411 #define ACLK_USB_ROOT 396 412 #define HCLK_USB_ROOT 397 413 #define HCLK_HOST0 398 414 #define HCLK_HOST_ARB0 399 415 #define HCLK_HOST1 400 416 #define HCLK_HOST_ARB1 401 417 #define ACLK_USB3OTG0 402 418 #define SUSPEND_CLK_USB3OTG0 403 419 #define REF_CLK_USB3OTG0 404 420 #define ACLK_USB3OTG1 405 421 #define SUSPEND_CLK_USB3OTG1 406 422 #define REF_CLK_USB3OTG1 407 423 #define UTMI_OHCI_CLK48_HOST0 408 424 #define UTMI_OHCI_CLK48_HOST1 409 425 #define HCLK_IEP2P0 410 426 #define ACLK_IEP2P0 411 427 #define CLK_IEP2P0_CORE 412 428 #define ACLK_JPEG_ENCODER0 413 429 #define HCLK_JPEG_ENCODER0 414 430 #define ACLK_JPEG_ENCODER1 415 431 #define HCLK_JPEG_ENCODER1 416 432 #define ACLK_JPEG_ENCODER2 417 433 #define HCLK_JPEG_ENCODER2 418 434 #define ACLK_JPEG_ENCODER3 419 435 #define HCLK_JPEG_ENCODER3 420 436 #define ACLK_JPEG_DECODER 421 437 #define HCLK_JPEG_DECODER 422 438 #define HCLK_RGA2 423 439 #define ACLK_RGA2 424 440 #define CLK_RGA2_CORE 425 441 #define HCLK_RGA3_0 426 442 #define ACLK_RGA3_0 427 443 #define CLK_RGA3_0_CORE 428 444 #define ACLK_VDPU_ROOT 429 445 #define ACLK_VDPU_LOW_ROOT 430 446 #define HCLK_VDPU_ROOT 431 447 #define ACLK_JPEG_DECODER_ROOT 432 448 #define ACLK_VPU 433 449 #define HCLK_VPU 434 450 #define HCLK_RKVENC0_ROOT 435 451 #define ACLK_RKVENC0_ROOT 436 452 #define HCLK_RKVENC0 437 453 #define ACLK_RKVENC0 438 454 #define CLK_RKVENC0_CORE 439 455 #define HCLK_RKVENC1_ROOT 440 456 #define ACLK_RKVENC1_ROOT 441 457 #define HCLK_RKVENC1 442 458 #define ACLK_RKVENC1 443 459 #define CLK_RKVENC1_CORE 444 460 #define ICLK_CSIHOST01 445 461 #define ICLK_CSIHOST0 446 462 #define ICLK_CSIHOST1 447 463 #define PCLK_CSI_HOST_0 448 464 #define PCLK_CSI_HOST_1 449 465 #define PCLK_CSI_HOST_2 450 466 #define PCLK_CSI_HOST_3 451 467 #define PCLK_CSI_HOST_4 452 468 #define PCLK_CSI_HOST_5 453 469 #define ACLK_FISHEYE0 454 470 #define HCLK_FISHEYE0 455 471 #define CLK_FISHEYE0_CORE 456 472 #define ACLK_FISHEYE1 457 473 #define HCLK_FISHEYE1 458 474 #define CLK_FISHEYE1_CORE 459 475 #define CLK_ISP0_CORE 460 476 #define CLK_ISP0_CORE_MARVIN 461 477 #define CLK_ISP0_CORE_VICAP 462 478 #define ACLK_ISP0 463 479 #define HCLK_ISP0 464 480 #define ACLK_VI_ROOT 465 481 #define HCLK_VI_ROOT 466 482 #define PCLK_VI_ROOT 467 483 #define DCLK_VICAP 468 484 #define ACLK_VICAP 469 485 #define HCLK_VICAP 470 486 #define PCLK_DP0 471 487 #define PCLK_DP1 472 488 #define PCLK_S_DP0 473 489 #define PCLK_S_DP1 474 490 #define CLK_DP0 475 491 #define CLK_DP1 476 492 #define HCLK_HDCP_KEY0 477 493 #define ACLK_HDCP0 478 494 #define HCLK_HDCP0 479 495 #define PCLK_HDCP0 480 496 #define HCLK_I2S4_8CH 481 497 #define ACLK_TRNG0 482 498 #define PCLK_TRNG0 483 499 #define ACLK_VO0_ROOT 484 500 #define HCLK_VO0_ROOT 485 501 #define HCLK_VO0_S_ROOT 486 502 #define PCLK_VO0_ROOT 487 503 #define PCLK_VO0_S_ROOT 488 504 #define PCLK_VO0GRF 489 505 #define CLK_I2S4_8CH_TX_SRC 490 506 #define CLK_I2S4_8CH_TX_FRAC 491 507 #define MCLK_I2S4_8CH_TX 492 508 #define CLK_I2S4_8CH_TX 493 509 #define HCLK_I2S8_8CH 494 510 #define CLK_I2S8_8CH_TX_SRC 495 511 #define CLK_I2S8_8CH_TX_FRAC 496 512 #define MCLK_I2S8_8CH_TX 497 513 #define CLK_I2S8_8CH_TX 498 514 #define HCLK_SPDIF2_DP0 499 515 #define CLK_SPDIF2_DP0_SRC 500 516 #define CLK_SPDIF2_DP0_FRAC 501 517 #define MCLK_SPDIF2_DP0 502 518 #define CLK_SPDIF2_DP0 503 519 #define MCLK_SPDIF2 504 520 #define HCLK_SPDIF5_DP1 505 521 #define CLK_SPDIF5_DP1_SRC 506 522 #define CLK_SPDIF5_DP1_FRAC 507 523 #define MCLK_SPDIF5_DP1 508 524 #define CLK_SPDIF5_DP1 509 525 #define MCLK_SPDIF5 510 526 #define PCLK_EDP0 511 527 #define CLK_EDP0_24M 512 528 #define CLK_EDP0_200M 513 529 #define PCLK_EDP1 514 530 #define CLK_EDP1_24M 515 531 #define CLK_EDP1_200M 516 532 #define HCLK_HDCP_KEY1 517 533 #define ACLK_HDCP1 518 534 #define HCLK_HDCP1 519 535 #define PCLK_HDCP1 520 536 #define ACLK_HDMIRX 521 537 #define PCLK_HDMIRX 522 538 #define CLK_HDMIRX_REF 523 539 #define CLK_HDMIRX_AUD_SRC 524 540 #define CLK_HDMIRX_AUD_FRAC 525 541 #define CLK_HDMIRX_AUD 526 542 #define CLK_HDMIRX_AUD_P_MUX 527 543 #define PCLK_HDMITX0 528 544 #define CLK_HDMITX0_EARC 529 545 #define CLK_HDMITX0_REF 530 546 #define PCLK_HDMITX1 531 547 #define CLK_HDMITX1_EARC 532 548 #define CLK_HDMITX1_REF 533 549 #define CLK_HDMITRX_REFSRC 534 550 #define ACLK_TRNG1 535 551 #define PCLK_TRNG1 536 552 #define ACLK_HDCP1_ROOT 537 553 #define ACLK_HDMIRX_ROOT 538 554 #define HCLK_VO1_ROOT 539 555 #define HCLK_VO1_S_ROOT 540 556 #define PCLK_VO1_ROOT 541 557 #define PCLK_VO1_S_ROOT 542 558 #define PCLK_S_EDP0 543 559 #define PCLK_S_EDP1 544 560 #define PCLK_S_HDMIRX 545 561 #define HCLK_I2S10_8CH 546 562 #define CLK_I2S10_8CH_RX_SRC 547 563 #define CLK_I2S10_8CH_RX_FRAC 548 564 #define CLK_I2S10_8CH_RX 549 565 #define MCLK_I2S10_8CH_RX 550 566 #define HCLK_I2S7_8CH 551 567 #define CLK_I2S7_8CH_RX_SRC 552 568 #define CLK_I2S7_8CH_RX_FRAC 553 569 #define CLK_I2S7_8CH_RX 554 570 #define MCLK_I2S7_8CH_RX 555 571 #define HCLK_I2S9_8CH 556 572 #define CLK_I2S9_8CH_RX_SRC 557 573 #define CLK_I2S9_8CH_RX_FRAC 558 574 #define CLK_I2S9_8CH_RX 559 575 #define MCLK_I2S9_8CH_RX 560 576 #define CLK_I2S5_8CH_TX_SRC 561 577 #define CLK_I2S5_8CH_TX_FRAC 562 578 #define CLK_I2S5_8CH_TX 563 579 #define MCLK_I2S5_8CH_TX 564 580 #define HCLK_I2S5_8CH 565 581 #define CLK_I2S6_8CH_TX_SRC 566 582 #define CLK_I2S6_8CH_TX_FRAC 567 583 #define CLK_I2S6_8CH_TX 568 584 #define MCLK_I2S6_8CH_TX 569 585 #define CLK_I2S6_8CH_RX_SRC 570 586 #define CLK_I2S6_8CH_RX_FRAC 571 587 #define CLK_I2S6_8CH_RX 572 588 #define MCLK_I2S6_8CH_RX 573 589 #define I2S6_8CH_MCLKOUT 574 590 #define HCLK_I2S6_8CH 575 591 #define HCLK_SPDIF3 576 592 #define CLK_SPDIF3_SRC 577 593 #define CLK_SPDIF3_FRAC 578 594 #define CLK_SPDIF3 579 595 #define MCLK_SPDIF3 580 596 #define HCLK_SPDIF4 581 597 #define CLK_SPDIF4_SRC 582 598 #define CLK_SPDIF4_FRAC 583 599 #define CLK_SPDIF4 584 600 #define MCLK_SPDIF4 585 601 #define HCLK_SPDIFRX0 586 602 #define MCLK_SPDIFRX0 587 603 #define HCLK_SPDIFRX1 588 604 #define MCLK_SPDIFRX1 589 605 #define HCLK_SPDIFRX2 590 606 #define MCLK_SPDIFRX2 591 607 #define ACLK_VO1USB_TOP_ROOT 592 608 #define HCLK_VO1USB_TOP_ROOT 593 609 #define CLK_HDMIHDP0 594 610 #define CLK_HDMIHDP1 595 611 #define PCLK_HDPTX0 596 612 #define PCLK_HDPTX1 597 613 #define PCLK_USBDPPHY0 598 614 #define PCLK_USBDPPHY1 599 615 #define ACLK_VOP_ROOT 600 616 #define ACLK_VOP_LOW_ROOT 601 617 #define HCLK_VOP_ROOT 602 618 #define PCLK_VOP_ROOT 603 619 #define HCLK_VOP 604 620 #define ACLK_VOP 605 621 #define DCLK_VOP0_SRC 606 622 #define DCLK_VOP1_SRC 607 623 #define DCLK_VOP2_SRC 608 624 #define DCLK_VOP0 609 625 #define DCLK_VOP1 610 626 #define DCLK_VOP2 611 627 #define DCLK_VOP3 612 628 #define PCLK_DSIHOST0 613 629 #define PCLK_DSIHOST1 614 630 #define CLK_DSIHOST0 615 631 #define CLK_DSIHOST1 616 632 #define CLK_VOP_PMU 617 633 #define ACLK_VOP_DOBY 618 634 #define ACLK_VOP_SUB_SRC 619 635 #define CLK_USBDP_PHY0_IMMORTAL 620 636 #define CLK_USBDP_PHY1_IMMORTAL 621 637 #define CLK_PMU0 622 638 #define PCLK_PMU0 623 639 #define PCLK_PMU0IOC 624 640 #define PCLK_GPIO0 625 641 #define DBCLK_GPIO0 626 642 #define PCLK_I2C0 627 643 #define CLK_I2C0 628 644 #define HCLK_I2S1_8CH 629 645 #define CLK_I2S1_8CH_TX_SRC 630 646 #define CLK_I2S1_8CH_TX_FRAC 631 647 #define CLK_I2S1_8CH_TX 632 648 #define MCLK_I2S1_8CH_TX 633 649 #define CLK_I2S1_8CH_RX_SRC 634 650 #define CLK_I2S1_8CH_RX_FRAC 635 651 #define CLK_I2S1_8CH_RX 636 652 #define MCLK_I2S1_8CH_RX 637 653 #define I2S1_8CH_MCLKOUT 638 654 #define CLK_PMU1_50M_SRC 639 655 #define CLK_PMU1_100M_SRC 640 656 #define CLK_PMU1_200M_SRC 641 657 #define CLK_PMU1_300M_SRC 642 658 #define CLK_PMU1_400M_SRC 643 659 #define HCLK_PMU1_ROOT 644 660 #define PCLK_PMU1_ROOT 645 661 #define PCLK_PMU0_ROOT 646 662 #define HCLK_PMU_CM0_ROOT 647 663 #define PCLK_PMU1 648 664 #define CLK_DDR_FAIL_SAFE 649 665 #define CLK_PMU1 650 666 #define HCLK_PDM0 651 667 #define MCLK_PDM0 652 668 #define HCLK_VAD 653 669 #define FCLK_PMU_CM0_CORE 654 670 #define CLK_PMU_CM0_RTC 655 671 #define PCLK_PMU1_IOC 656 672 #define PCLK_PMU1PWM 657 673 #define CLK_PMU1PWM 658 674 #define CLK_PMU1PWM_CAPTURE 659 675 #define PCLK_PMU1TIMER 660 676 #define CLK_PMU1TIMER_ROOT 661 677 #define CLK_PMU1TIMER0 662 678 #define CLK_PMU1TIMER1 663 679 #define CLK_UART0_SRC 664 680 #define CLK_UART0_FRAC 665 681 #define CLK_UART0 666 682 #define SCLK_UART0 667 683 #define PCLK_UART0 668 684 #define PCLK_PMU1WDT 669 685 #define TCLK_PMU1WDT 670 686 #define CLK_CR_PARA 671 687 #define CLK_USB2PHY_HDPTXRXPHY_REF 672 688 #define CLK_USBDPPHY_MIPIDCPPHY_REF 673 689 #define CLK_REF_PIPE_PHY0_OSC_SRC 674 690 #define CLK_REF_PIPE_PHY1_OSC_SRC 675 691 #define CLK_REF_PIPE_PHY2_OSC_SRC 676 692 #define CLK_REF_PIPE_PHY0_PLL_SRC 677 693 #define CLK_REF_PIPE_PHY1_PLL_SRC 678 694 #define CLK_REF_PIPE_PHY2_PLL_SRC 679 695 #define CLK_REF_PIPE_PHY0 680 696 #define CLK_REF_PIPE_PHY1 681 697 #define CLK_REF_PIPE_PHY2 682 698 #define SCLK_SDIO_DRV 683 699 #define SCLK_SDIO_SAMPLE 684 700 #define SCLK_SDMMC_DRV 685 701 #define SCLK_SDMMC_SAMPLE 686 702 #define CLK_PCIE1L0_PIPE 687 703 #define CLK_PCIE1L1_PIPE 688 704 #define CLK_BIGCORE0_PVTM 689 705 #define CLK_CORE_BIGCORE0_PVTM 690 706 #define CLK_BIGCORE1_PVTM 691 707 #define CLK_CORE_BIGCORE1_PVTM 692 708 #define CLK_LITCORE_PVTM 693 709 #define CLK_CORE_LITCORE_PVTM 694 710 #define CLK_AUX16M_0 695 711 #define CLK_AUX16M_1 696 712 #define CLK_PHY0_REF_ALT_P 697 713 #define CLK_PHY0_REF_ALT_M 698 714 #define CLK_PHY1_REF_ALT_P 699 715 #define CLK_PHY1_REF_ALT_M 700 716 #define ACLK_ISP1_PRE 701 717 #define HCLK_ISP1_PRE 702 718 #define HCLK_NVM 703 719 #define ACLK_USB 704 720 #define HCLK_USB 705 721 #define ACLK_JPEG_DECODER_PRE 706 722 #define ACLK_VDPU_LOW_PRE 707 723 #define ACLK_RKVENC1_PRE 708 724 #define HCLK_RKVENC1_PRE 709 725 #define HCLK_RKVDEC0_PRE 710 726 #define ACLK_RKVDEC0_PRE 711 727 #define HCLK_RKVDEC1_PRE 712 728 #define ACLK_RKVDEC1_PRE 713 729 #define ACLK_HDCP0_PRE 714 730 #define HCLK_VO0 715 731 #define ACLK_HDCP1_PRE 716 732 #define HCLK_VO1 717 733 #define ACLK_AV1_PRE 718 734 #define PCLK_AV1_PRE 719 735 #define HCLK_SDIO_PRE 720 736 #define PCLK_VO1GRF 721 737 738 /* scmi-clocks indices */ 739 740 #define SCMI_CLK_CPUL 0 741 #define SCMI_CLK_DSU 1 742 #define SCMI_CLK_CPUB01 2 743 #define SCMI_CLK_CPUB23 3 744 #define SCMI_CLK_DDR 4 745 #define SCMI_CLK_GPU 5 746 #define SCMI_CLK_NPU 6 747 #define SCMI_CLK_SBUS 7 748 #define SCMI_PCLK_SBUS 8 749 #define SCMI_CCLK_SD 9 750 #define SCMI_DCLK_SD 10 751 #define SCMI_ACLK_SECURE_NS 11 752 #define SCMI_HCLK_SECURE_NS 12 753 #define SCMI_TCLK_WDT 13 754 #define SCMI_KEYLADDER_CORE 14 755 #define SCMI_KEYLADDER_RNG 15 756 #define SCMI_ACLK_SECURE_S 16 757 #define SCMI_HCLK_SECURE_S 17 758 #define SCMI_PCLK_SECURE_S 18 759 #define SCMI_CRYPTO_RNG 19 760 #define SCMI_CRYPTO_CORE 20 761 #define SCMI_CRYPTO_PKA 21 762 #define SCMI_SPLL 22 763 #define SCMI_HCLK_SD 23 764 765 #endif 766
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