1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. 4 */ 5 6 #ifndef __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ 7 #define __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ 8 9 #define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0 10 #define DIV_CLK_MPLL_AXI_DDR_0 1 11 #define DIV_CLK_FPLL_DDR01_1 2 12 #define DIV_CLK_FPLL_DDR23_1 3 13 #define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4 14 #define DIV_CLK_FPLL_50M_A53 5 15 #define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6 16 #define DIV_CLK_FPLL_UART_500M 7 17 #define DIV_CLK_FPLL_AHB_LPC 8 18 #define DIV_CLK_FPLL_EFUSE 9 19 #define DIV_CLK_FPLL_TX_ETH0 10 20 #define DIV_CLK_FPLL_PTP_REF_I_ETH0 11 21 #define DIV_CLK_FPLL_REF_ETH0 12 22 #define DIV_CLK_FPLL_EMMC 13 23 #define DIV_CLK_FPLL_SD 14 24 #define DIV_CLK_FPLL_TOP_AXI0 15 25 #define DIV_CLK_FPLL_TOP_AXI_HSPERI 16 26 #define DIV_CLK_FPLL_AXI_DDR_1 17 27 #define DIV_CLK_FPLL_DIV_TIMER1 18 28 #define DIV_CLK_FPLL_DIV_TIMER2 19 29 #define DIV_CLK_FPLL_DIV_TIMER3 20 30 #define DIV_CLK_FPLL_DIV_TIMER4 21 31 #define DIV_CLK_FPLL_DIV_TIMER5 22 32 #define DIV_CLK_FPLL_DIV_TIMER6 23 33 #define DIV_CLK_FPLL_DIV_TIMER7 24 34 #define DIV_CLK_FPLL_DIV_TIMER8 25 35 #define DIV_CLK_FPLL_100K_EMMC 26 36 #define DIV_CLK_FPLL_100K_SD 27 37 #define DIV_CLK_FPLL_GPIO_DB 28 38 #define DIV_CLK_DPLL0_DDR01_0 29 39 #define DIV_CLK_DPLL1_DDR23_0 30 40 41 #define GATE_CLK_RP_CPU_NORMAL_DIV0 31 42 #define GATE_CLK_AXI_DDR_DIV0 32 43 44 #define GATE_CLK_RP_CPU_NORMAL_DIV1 33 45 #define GATE_CLK_A53_50M 34 46 #define GATE_CLK_TOP_RP_CMN_DIV2 35 47 #define GATE_CLK_HSDMA 36 48 #define GATE_CLK_EMMC_100M 37 49 #define GATE_CLK_SD_100M 38 50 #define GATE_CLK_TX_ETH0 39 51 #define GATE_CLK_PTP_REF_I_ETH0 40 52 #define GATE_CLK_REF_ETH0 41 53 #define GATE_CLK_UART_500M 42 54 #define GATE_CLK_EFUSE 43 55 56 #define GATE_CLK_AHB_LPC 44 57 #define GATE_CLK_AHB_ROM 45 58 #define GATE_CLK_AHB_SF 46 59 60 #define GATE_CLK_APB_UART 47 61 #define GATE_CLK_APB_TIMER 48 62 #define GATE_CLK_APB_EFUSE 49 63 #define GATE_CLK_APB_GPIO 50 64 #define GATE_CLK_APB_GPIO_INTR 51 65 #define GATE_CLK_APB_SPI 52 66 #define GATE_CLK_APB_I2C 53 67 #define GATE_CLK_APB_WDT 54 68 #define GATE_CLK_APB_PWM 55 69 #define GATE_CLK_APB_RTC 56 70 71 #define GATE_CLK_AXI_PCIE0 57 72 #define GATE_CLK_AXI_PCIE1 58 73 #define GATE_CLK_SYSDMA_AXI 59 74 #define GATE_CLK_AXI_DBG_I2C 60 75 #define GATE_CLK_AXI_SRAM 61 76 #define GATE_CLK_AXI_ETH0 62 77 #define GATE_CLK_AXI_EMMC 63 78 #define GATE_CLK_AXI_SD 64 79 #define GATE_CLK_TOP_AXI0 65 80 #define GATE_CLK_TOP_AXI_HSPERI 66 81 82 #define GATE_CLK_TIMER1 67 83 #define GATE_CLK_TIMER2 68 84 #define GATE_CLK_TIMER3 69 85 #define GATE_CLK_TIMER4 70 86 #define GATE_CLK_TIMER5 71 87 #define GATE_CLK_TIMER6 72 88 #define GATE_CLK_TIMER7 73 89 #define GATE_CLK_TIMER8 74 90 #define GATE_CLK_100K_EMMC 75 91 #define GATE_CLK_100K_SD 76 92 #define GATE_CLK_GPIO_DB 77 93 94 #define GATE_CLK_AXI_DDR_DIV1 78 95 #define GATE_CLK_DDR01_DIV1 79 96 #define GATE_CLK_DDR23_DIV1 80 97 98 #define GATE_CLK_DDR01_DIV0 81 99 #define GATE_CLK_DDR23_DIV0 82 100 101 #define GATE_CLK_DDR01 83 102 #define GATE_CLK_DDR23 84 103 #define GATE_CLK_RP_CPU_NORMAL 85 104 #define GATE_CLK_AXI_DDR 86 105 106 #define MUX_CLK_DDR01 87 107 #define MUX_CLK_DDR23 88 108 #define MUX_CLK_RP_CPU_NORMAL 89 109 #define MUX_CLK_AXI_DDR 90 110 111 #endif /* __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ */ 112
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