1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H 7 #define _DT_BINDINGS_QCOM_SPMI_VADC_H 8 9 /* Voltage ADC channels */ 10 #define VADC_USBIN 0x00 11 #define VADC_DCIN 0x01 12 #define VADC_VCHG_SNS 0x02 13 #define VADC_SPARE1_03 0x03 14 #define VADC_USB_ID_MV 0x04 15 #define VADC_VCOIN 0x05 16 #define VADC_VBAT_SNS 0x06 17 #define VADC_VSYS 0x07 18 #define VADC_DIE_TEMP 0x08 19 #define VADC_REF_625MV 0x09 20 #define VADC_REF_1250MV 0x0a 21 #define VADC_CHG_TEMP 0x0b 22 #define VADC_SPARE1 0x0c 23 #define VADC_SPARE2 0x0d 24 #define VADC_GND_REF 0x0e 25 #define VADC_VDD_VADC 0x0f 26 27 #define VADC_P_MUX1_1_1 0x10 28 #define VADC_P_MUX2_1_1 0x11 29 #define VADC_P_MUX3_1_1 0x12 30 #define VADC_P_MUX4_1_1 0x13 31 #define VADC_P_MUX5_1_1 0x14 32 #define VADC_P_MUX6_1_1 0x15 33 #define VADC_P_MUX7_1_1 0x16 34 #define VADC_P_MUX8_1_1 0x17 35 #define VADC_P_MUX9_1_1 0x18 36 #define VADC_P_MUX10_1_1 0x19 37 #define VADC_P_MUX11_1_1 0x1a 38 #define VADC_P_MUX12_1_1 0x1b 39 #define VADC_P_MUX13_1_1 0x1c 40 #define VADC_P_MUX14_1_1 0x1d 41 #define VADC_P_MUX15_1_1 0x1e 42 #define VADC_P_MUX16_1_1 0x1f 43 44 #define VADC_P_MUX1_1_3 0x20 45 #define VADC_P_MUX2_1_3 0x21 46 #define VADC_P_MUX3_1_3 0x22 47 #define VADC_P_MUX4_1_3 0x23 48 #define VADC_P_MUX5_1_3 0x24 49 #define VADC_P_MUX6_1_3 0x25 50 #define VADC_P_MUX7_1_3 0x26 51 #define VADC_P_MUX8_1_3 0x27 52 #define VADC_P_MUX9_1_3 0x28 53 #define VADC_P_MUX10_1_3 0x29 54 #define VADC_P_MUX11_1_3 0x2a 55 #define VADC_P_MUX12_1_3 0x2b 56 #define VADC_P_MUX13_1_3 0x2c 57 #define VADC_P_MUX14_1_3 0x2d 58 #define VADC_P_MUX15_1_3 0x2e 59 #define VADC_P_MUX16_1_3 0x2f 60 61 #define VADC_LR_MUX1_BAT_THERM 0x30 62 #define VADC_LR_MUX2_BAT_ID 0x31 63 #define VADC_LR_MUX3_XO_THERM 0x32 64 #define VADC_LR_MUX4_AMUX_THM1 0x33 65 #define VADC_LR_MUX5_AMUX_THM2 0x34 66 #define VADC_LR_MUX6_AMUX_THM3 0x35 67 #define VADC_LR_MUX7_HW_ID 0x36 68 #define VADC_LR_MUX8_AMUX_THM4 0x37 69 #define VADC_LR_MUX9_AMUX_THM5 0x38 70 #define VADC_LR_MUX10_USB_ID 0x39 71 #define VADC_AMUX_PU1 0x3a 72 #define VADC_AMUX_PU2 0x3b 73 #define VADC_LR_MUX3_BUF_XO_THERM 0x3c 74 75 #define VADC_LR_MUX1_PU1_BAT_THERM 0x70 76 #define VADC_LR_MUX2_PU1_BAT_ID 0x71 77 #define VADC_LR_MUX3_PU1_XO_THERM 0x72 78 #define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 79 #define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 80 #define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 81 #define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 82 #define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 83 #define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 84 #define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 85 #define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c 86 87 #define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 88 #define VADC_LR_MUX2_PU2_BAT_ID 0xb1 89 #define VADC_LR_MUX3_PU2_XO_THERM 0xb2 90 #define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 91 #define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 92 #define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 93 #define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 94 #define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 95 #define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 96 #define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 97 #define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc 98 99 #define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 100 #define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 101 #define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 102 #define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 103 #define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 104 #define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 105 #define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 106 #define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 107 #define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 108 #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 109 #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc 110 111 /* ADC channels for SPMI PMIC5 */ 112 113 #define ADC5_REF_GND 0x00 114 #define ADC5_1P25VREF 0x01 115 #define ADC5_VREF_VADC 0x02 116 #define ADC5_VREF_VADC5_DIV_3 0x82 117 #define ADC5_VPH_PWR 0x83 118 #define ADC5_VBAT_SNS 0x84 119 #define ADC5_VCOIN 0x85 120 #define ADC5_DIE_TEMP 0x06 121 #define ADC5_USB_IN_I 0x07 122 #define ADC5_USB_IN_V_16 0x08 123 #define ADC5_CHG_TEMP 0x09 124 #define ADC5_BAT_THERM 0x0a 125 #define ADC5_BAT_ID 0x0b 126 #define ADC5_XO_THERM 0x0c 127 #define ADC5_AMUX_THM1 0x0d 128 #define ADC5_AMUX_THM2 0x0e 129 #define ADC5_AMUX_THM3 0x0f 130 #define ADC5_AMUX_THM4 0x10 131 #define ADC5_AMUX_THM5 0x11 132 #define ADC5_GPIO1 0x12 133 #define ADC5_GPIO2 0x13 134 #define ADC5_GPIO3 0x14 135 #define ADC5_GPIO4 0x15 136 #define ADC5_GPIO5 0x16 137 #define ADC5_GPIO6 0x17 138 #define ADC5_GPIO7 0x18 139 #define ADC5_SBUx 0x99 140 #define ADC5_MID_CHG_DIV6 0x1e 141 #define ADC5_OFF 0xff 142 143 /* 30k pull-up1 */ 144 #define ADC5_BAT_THERM_30K_PU 0x2a 145 #define ADC5_BAT_ID_30K_PU 0x2b 146 #define ADC5_XO_THERM_30K_PU 0x2c 147 #define ADC5_AMUX_THM1_30K_PU 0x2d 148 #define ADC5_AMUX_THM2_30K_PU 0x2e 149 #define ADC5_AMUX_THM3_30K_PU 0x2f 150 #define ADC5_AMUX_THM4_30K_PU 0x30 151 #define ADC5_AMUX_THM5_30K_PU 0x31 152 #define ADC5_GPIO1_30K_PU 0x32 153 #define ADC5_GPIO2_30K_PU 0x33 154 #define ADC5_GPIO3_30K_PU 0x34 155 #define ADC5_GPIO4_30K_PU 0x35 156 #define ADC5_GPIO5_30K_PU 0x36 157 #define ADC5_GPIO6_30K_PU 0x37 158 #define ADC5_GPIO7_30K_PU 0x38 159 #define ADC5_SBUx_30K_PU 0x39 160 161 /* 100k pull-up2 */ 162 #define ADC5_BAT_THERM_100K_PU 0x4a 163 #define ADC5_BAT_ID_100K_PU 0x4b 164 #define ADC5_XO_THERM_100K_PU 0x4c 165 #define ADC5_AMUX_THM1_100K_PU 0x4d 166 #define ADC5_AMUX_THM2_100K_PU 0x4e 167 #define ADC5_AMUX_THM3_100K_PU 0x4f 168 #define ADC5_AMUX_THM4_100K_PU 0x50 169 #define ADC5_AMUX_THM5_100K_PU 0x51 170 #define ADC5_GPIO1_100K_PU 0x52 171 #define ADC5_GPIO2_100K_PU 0x53 172 #define ADC5_GPIO3_100K_PU 0x54 173 #define ADC5_GPIO4_100K_PU 0x55 174 #define ADC5_GPIO5_100K_PU 0x56 175 #define ADC5_GPIO6_100K_PU 0x57 176 #define ADC5_GPIO7_100K_PU 0x58 177 #define ADC5_SBUx_100K_PU 0x59 178 179 /* 400k pull-up3 */ 180 #define ADC5_BAT_THERM_400K_PU 0x6a 181 #define ADC5_BAT_ID_400K_PU 0x6b 182 #define ADC5_XO_THERM_400K_PU 0x6c 183 #define ADC5_AMUX_THM1_400K_PU 0x6d 184 #define ADC5_AMUX_THM2_400K_PU 0x6e 185 #define ADC5_AMUX_THM3_400K_PU 0x6f 186 #define ADC5_AMUX_THM4_400K_PU 0x70 187 #define ADC5_AMUX_THM5_400K_PU 0x71 188 #define ADC5_GPIO1_400K_PU 0x72 189 #define ADC5_GPIO2_400K_PU 0x73 190 #define ADC5_GPIO3_400K_PU 0x74 191 #define ADC5_GPIO4_400K_PU 0x75 192 #define ADC5_GPIO5_400K_PU 0x76 193 #define ADC5_GPIO6_400K_PU 0x77 194 #define ADC5_GPIO7_400K_PU 0x78 195 #define ADC5_SBUx_400K_PU 0x79 196 197 /* 1/3 Divider */ 198 #define ADC5_GPIO1_DIV3 0x92 199 #define ADC5_GPIO2_DIV3 0x93 200 #define ADC5_GPIO3_DIV3 0x94 201 #define ADC5_GPIO4_DIV3 0x95 202 #define ADC5_GPIO5_DIV3 0x96 203 #define ADC5_GPIO6_DIV3 0x97 204 #define ADC5_GPIO7_DIV3 0x98 205 #define ADC5_SBUx_DIV3 0x99 206 207 /* Current and combined current/voltage channels */ 208 #define ADC5_INT_EXT_ISENSE 0xa1 209 #define ADC5_PARALLEL_ISENSE 0xa5 210 #define ADC5_CUR_REPLICA_VDS 0xa7 211 #define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 212 #define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab 213 #define ADC5_EXT_SENS_OFFSET 0xad 214 215 #define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 216 #define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 217 #define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 218 #define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 219 #define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 220 #define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 221 222 #define ADC5_MAX_CHANNEL 0xc0 223 224 /* ADC channels for ADC for PMIC7 */ 225 226 #define ADC7_REF_GND 0x00 227 #define ADC7_1P25VREF 0x01 228 #define ADC7_VREF_VADC 0x02 229 #define ADC7_DIE_TEMP 0x03 230 231 #define ADC7_AMUX_THM1 0x04 232 #define ADC7_AMUX_THM2 0x05 233 #define ADC7_AMUX_THM3 0x06 234 #define ADC7_AMUX_THM4 0x07 235 #define ADC7_AMUX_THM5 0x08 236 #define ADC7_AMUX_THM6 0x09 237 #define ADC7_GPIO1 0x0a 238 #define ADC7_GPIO2 0x0b 239 #define ADC7_GPIO3 0x0c 240 #define ADC7_GPIO4 0x0d 241 242 #define ADC7_SMB_TEMP 0x06 243 #define ADC7_CHG_TEMP 0x10 244 #define ADC7_USB_IN_V_16 0x11 245 #define ADC7_VDC_16 0x12 246 #define ADC7_CC1_ID 0x13 247 #define ADC7_VREF_BAT_THERM 0x15 248 #define ADC7_IIN_FB 0x17 249 #define ADC7_ICHG_SMB 0x18 250 #define ADC7_IIN_SMB 0x19 251 252 /* 30k pull-up1 */ 253 #define ADC7_AMUX_THM1_30K_PU 0x24 254 #define ADC7_AMUX_THM2_30K_PU 0x25 255 #define ADC7_AMUX_THM3_30K_PU 0x26 256 #define ADC7_AMUX_THM4_30K_PU 0x27 257 #define ADC7_AMUX_THM5_30K_PU 0x28 258 #define ADC7_AMUX_THM6_30K_PU 0x29 259 #define ADC7_GPIO1_30K_PU 0x2a 260 #define ADC7_GPIO2_30K_PU 0x2b 261 #define ADC7_GPIO3_30K_PU 0x2c 262 #define ADC7_GPIO4_30K_PU 0x2d 263 #define ADC7_CC1_ID_30K_PU 0x33 264 265 /* 100k pull-up2 */ 266 #define ADC7_AMUX_THM1_100K_PU 0x44 267 #define ADC7_AMUX_THM2_100K_PU 0x45 268 #define ADC7_AMUX_THM3_100K_PU 0x46 269 #define ADC7_AMUX_THM4_100K_PU 0x47 270 #define ADC7_AMUX_THM5_100K_PU 0x48 271 #define ADC7_AMUX_THM6_100K_PU 0x49 272 #define ADC7_GPIO1_100K_PU 0x4a 273 #define ADC7_GPIO2_100K_PU 0x4b 274 #define ADC7_GPIO3_100K_PU 0x4c 275 #define ADC7_GPIO4_100K_PU 0x4d 276 #define ADC7_CC1_ID_100K_PU 0x53 277 278 /* 400k pull-up3 */ 279 #define ADC7_AMUX_THM1_400K_PU 0x64 280 #define ADC7_AMUX_THM2_400K_PU 0x65 281 #define ADC7_AMUX_THM3_400K_PU 0x66 282 #define ADC7_AMUX_THM4_400K_PU 0x67 283 #define ADC7_AMUX_THM5_400K_PU 0x68 284 #define ADC7_AMUX_THM6_400K_PU 0x69 285 #define ADC7_GPIO1_400K_PU 0x6a 286 #define ADC7_GPIO2_400K_PU 0x6b 287 #define ADC7_GPIO3_400K_PU 0x6c 288 #define ADC7_GPIO4_400K_PU 0x6d 289 #define ADC7_CC1_ID_400K_PU 0x73 290 291 /* 1/3 Divider */ 292 #define ADC7_GPIO1_DIV3 0x8a 293 #define ADC7_GPIO2_DIV3 0x8b 294 #define ADC7_GPIO3_DIV3 0x8c 295 #define ADC7_GPIO4_DIV3 0x8d 296 297 #define ADC7_VPH_PWR 0x8e 298 #define ADC7_VBAT_SNS 0x8f 299 300 #define ADC7_SBUx 0x94 301 #define ADC7_VBAT_2S_MID 0x96 302 303 #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ 304
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