1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ 7 #define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ 8 9 #include <dt-bindings/memory/mtk-memory-port.h> 10 11 #define M4U_LARB0_ID 0 12 #define M4U_LARB1_ID 1 13 #define M4U_LARB2_ID 2 14 #define M4U_LARB3_ID 3 15 #define M4U_LARB4_ID 4 16 #define M4U_LARB5_ID 5 17 18 /* larb0 */ 19 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 20 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 21 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 22 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 23 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 24 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 25 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 26 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 27 28 /* larb1 */ 29 #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 30 #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 31 #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 32 #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 33 #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 34 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 35 #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 36 #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 37 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 38 #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 39 40 /* larb2 */ 41 #define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) 42 #define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) 43 #define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) 44 #define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) 45 #define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) 46 #define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5) 47 #define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) 48 #define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) 49 #define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) 50 #define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) 51 #define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) 52 #define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) 53 #define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) 54 #define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) 55 #define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) 56 #define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) 57 #define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) 58 #define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) 59 #define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18) 60 #define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19) 61 #define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20) 62 63 /* larb3 */ 64 #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 65 #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 66 #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 67 #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 68 #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 69 #define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) 70 #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) 71 #define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) 72 #define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) 73 #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) 74 #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) 75 #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) 76 #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) 77 #define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13) 78 #define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14) 79 80 /* larb4 */ 81 #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 82 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 83 #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2) 84 #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3) 85 #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4) 86 #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5) 87 88 /* larb5 */ 89 #define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0) 90 #define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1) 91 #define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2) 92 #define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3) 93 #define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4) 94 #define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5) 95 #define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6) 96 #define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7) 97 #define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8) 98 99 #endif 100
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